Integrating low temperature aligned carbon nanotubes as verticalinterconnects in Si technology

Sten Vollebregt, Ryoichi Ishihara, Jaber Derakhshandeh,

Johan van der Cingel, Hugo Schellevis and C.I.M. Beenakker

Abstract— For the application of carbon nanotubes (CNT) asinterconnects in integrated circuits low temperature verticallyaligned growth with a high tube density is required. Wefound that etching and cleaning steps used in semiconductortechnology can damage the catalyst or support layer, preventinglow temperature aligned CNT growth. We propose to use a lift-off process and sacrificial layer to prevent damage. Using thismethod we created low temperature electrical measurementstructures for CNT bundles. The bundles grown at 500 °Cdisplay a low resistivity and good Ohmic contact. Finally, wedemonstrate that CNT can be covered by PECVD silicon oxideand nitride without inducing damage, which is of interest forlow temperature bottom-up integration.

I. INTRODUCTION

Since their discovery, many applications have been pro-

posed for vertically aligned carbon nanotubes (CNT). One

promising application within microelectronics is vertical

interconnects [1]. Some other potential areas include super

capacitors [2], micro-mechanical electrical systems (MEMS)

[3] and displays [4].

For vertical interconnects (vias) a key requirement is

selective growth of vertically aligned CNT directly on top

of electrically conductive layers on a substrate with high

tube density. Low temperature deposition is important to

allow integration with already fabricated devices (e.g. CMOS

transistors) or to allow growth on transparent or flexible

substrates.

Two approaches can be defined to integrate intercon-

nects: the traditional top-down approach and the bottom-

up approach as presented by Li et al. [5]. In the top-down

approach a contact opening is etched through the dielectric

in-between the metal layers, followed by CNT growth inside

the opening and subsequent metallisation. In case of the

bottom-up approach CNT are first grown in the contact area

of the previous metal layer, covered by dielectric, planarized

and finally covered by the next metallisation. The distinct

advantage of the bottom-up method is that it allows the

creation of high aspect ratio (HAR) vias, without the need for

the etching of and metal deposition in HAR openings. The

bottom-up approach is also attractive for high-aspect ratio

MEMS [6].

However, few publications exist that use mainstream sil-

icon process technology to integrate low-temperature CNT

This project is kindly funded by the European ENIAC Joint Undertaking.All authors are with the Faculty of Electrical Engineering, Mathematics

and Computer Science, Delft Institute of Microsystems and Nanoelectron-ics, Delft University of Technology, Feldmannweg 17, 2628 CD Delft,The Netherlands. Phone: +31-15-2786788; fax: +31-15-2622163; e-mail:s.vollebregt@tudelft.nl

growth, and combine this with electrical characterisation of

the as-grown CNT bundles. In this paper we demonstrate

vertically-aligned high-density growth of CNT on sputtered

TiN layers at temperatures as low as 500 °C. We found that

specific processing steps used in silicon technology on an

exposed TiN diffusion barrier or catalyst layer can have a

large impact on the CNT growth at low temperature. We

will discuss the processing steps we found to be harmful to

CNT growth, and methods to prevent damage. Using this we

demonstrate successful integrated top-down CNT structures

to measure the bundle resistance of the vertically aligned

CNT grown at 500 °C. Finally, we demonstrate that it is

possible to use plasma-enhanced chemical vapour deposited

(PECVD) silicon oxide and nitride to cover CNT for bottom-

up integration.

II. EXPERIMENTAL

In this section we describe the process steps employed

to create structures to electrically characterise the vertically

grown CNT. Previously we demonstrated that resist residues

remaining after standard photo-lithography and wet etching

of the catalyst during cleaning can negatively impact growth

[7]. To prevent damage to the catalyst layer we changed

to a lift-off process using pure negative resist to pattern

the Ni or Fe catalyst layer. The minimum feature sizes

obtained recently with this method are 0.8 μm holes and

0.5 μm lines, which is limited by our ASMAL PAS 5500/80

waferstepper. Another advantage of lift-off is that it allows

patterning of Pd, which we recently demonstrated to allow

low temperature high-density vertically aligned growth [8].

CNTs are grown using a commercially available AIX-

TRON BlackMagic Pro 4" inch CVD reactor. We used 100

mm p-type Si wafers as substrate. For the measurement

samples we sputtered 500 nm of Ti and 50 nm of TiN on

the Si wafers using a Trikon (SPTS) Sigma sputter coater.

Then, 1.5 μm of tetraethyl orthosilicate (TEOS) is deposited

using a Novellus Concept One PECVD reactor. After this the

wafer is coated with 1.5 μm AZ nLOF2020 negative resist,

exposed and developed. This is followed by dry etching of

the oxide using a Drytek etcher with fluorine chemistry.

The resist is not stripped, but used to perform lift-off, thus

enabling automatic alignment. Before this 5 nm of Fe is

evaporated using a Solution CHA e-beam evaporator. Lift-off

is performed with n-methyl-2-pyrrolidone (NMP) at 70 °C.

Normally no ultrasonic treatment is required to completely

remove the resist.

2011 11th IEEE International Conference on NanotechnologyPortland MarriottAugust 15-18, 2011, Portland, Oregon, USA

978-1-4577-1515-0/11/$26.00 ©2011 IEEE 985

Fig. 1. SEM images of CNT grown on differently treated TiN substrates at 500 °C and 650 °C.

The catalyst layer is activated by annealing the sample

inside the CNT reactor at 500 °C with 700 sccm H2 flowing.

After three minutes 50 sccm of C2H2 is added and CNT are

grown for 5 minutes to reach the required height of 1.5 μm.

During both steps the pressure is regulated to 80 mbar. The

CNT are covered by a 2nd metallization of 100 nm of Ti and

3 μm of Al using sputtering. Finally, the Al and Ti layer are

patterned using wet etching.

To analyse the samples we used a FEI/Philips XL50 scan-

ning electron microscope (SEM), Renishaw inVia Raman

spectroscope with 633 nm laser, NT-MDT nTegra atomic

force microscope (AFM) and an HP 4156 parameter analyser

in combination with a probe station. In case of the Raman

spectroscopy three measurements are performed for each

sample, which are averaged to increase accuracy.

III. RESULTS AND DISCUSSION

In this section we discuss the effect of different surface

treatments on the TiN layer and the resulting low and high

temperature CNT growth. Using a sacrificial layer to protect

the TiN we use a top-down approach to electrically charac-

terise the as-grown CNT bundles. Finally, we investigate the

impact of covering CNT with PECVD oxide and nitride on

the crystal quality of the CNT for bottom-up integration.

A. Surface treatment of TiN

We use TiN as a diffusion barrier for our electrical mea-

surement structures, since it is not as sensitive to oxidation

in air as Ti while forming a good electrical contact to CNT

[9]. It was found that certain common process steps in

semiconductor technology can induce microscopic changes

in the TiN layer, preventing low temperature self-aligned

growth. We investigated the impact of chemical solutions

and plasma treatment on the TiN and the subsequent low

and high temperature CNT growth.

First we investigate which treatments prevent low temper-

ature growth. For this we created 5 different samples with

TiN layer and exposed the layer to different conditions (see

also table I): A: 10 min. 99.9 % HNO3 (our standard metal

clean); B: 1 min. 0.55 % HF; C: 1 kW oxygen plasma used

for resist stripping; D: 100 W fluorine chemistry soft landing

step used for oxide etching; E: pristine TiN. After this we

evaporated Fe and grew CNT at 500 °C (low temperature)

and 650 °C (high temperature).

In Fig. 1 the SEM images taken from the resulting CNT

growth on the five different samples at low and high temper-

ature can be found. As can be directly observed both plasma

treated samples display no self-aligned vertical growth on

low temperature. The other three samples grow self-aligned

CNT with a height of several microns. Interesting, sample B

displays the highest CNT (3.7 μm), followed by sample A

(3.3 μm) and E (2.5 μm). We’re unsure if this is caused by

slight differences in the treated surface (HF might passivate

the TiN surface), or due to small temperature differences as

growth rate is highly temperature dependent. We approxi-

mate the tube density to be in the order of 1011 cm-2 for all

aligned samples, and the tube diameter to be in the range of

20-40 nm.

The high temperature samples again display a difference

between samples A, B, E and C, D. Although self-aligned

growth is now possible on all samples, the CNT height

of sample C and D is approximately half of the other

samples. Also density and alignment suffers from the plasma

treatment. At high temperature the length of samples A and B

is found to be the same (31 μm), while E is slightly longer (35

μm), which is in contrast to the situation at low temperature.

Using Raman spectroscopy we investigated if the treat-

ment of the support layer influenced the crystal quality of the

CNT growth. In table II the intensity ratios and full-widths

at half maximum (FWHM) of the different Raman bands are

displayed. As is known from literature the ID/G and ID’/G ratio

normally show a decline for increasing crystallinity, while

IG’/G increases [10], [11]. A decreasing band FWHM is also

associated with increasing crystallinity [11], [12].

Table II clearly shows that CNT grown at higher temper-

TABLE I

OVERVIEW OF SURFACE TREATMENTS USED ON DIFFERENT SAMPLES

Sample TreatmentA 10 min. HNO3 (99.9 %)B 1 min. HF (0.55 %) )C 5 min. 1 kW oxygen plasmaD 1 min. 100 W fluorine plasmaE No treatment

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Fig. 2. AFM images taken from samples A, C, D and E displaying theeffect of the surface treatments on the TiN surface

ature have higher crystallinity. The band ratios and widths

of samples A, B and E are close to each other, indicating

that chemical treatment of the TiN surface with either HNO3

or HF has no profound impact on CNT crystallinity. On the

other hand, sample C and D display a different behaviour.

The ID/G ratio is significantly higher for the low temperature

C sample, and lower for the high temperature C and D

sample. This could indicate lower and higher crystallinity,

for respectively low and high temperature samples. On the

other hand, the FWHM of the low temperature growth on

sample C suggest a higher crystallinity compared to A, B,

D and E.

In order to investigate potential causes for the change in

low and high temperature CNT growth on plasma treated

surfaces we measured the samples after their treatment with

AFM, which are shown in Fig. 2. As can be seen no

significant difference exist between samples A and E (and

B, which is not displayed here). Sample C, on the other

hand, appears to have a more smoothed surface (i.e. less

sharp edges between the different TiN grains). The change

TABLE II

RAMAN DATA OBTAINED FROM CNT GROWN ON DIFFERENT SAMPLES

FWHM [cm-1]Sample ID/G ID’/G IG’/G D G D’ G’

A: 500 °C 2.84 1.24 0.30 81 63 44 148650 °C 2.22 0.81 0.88 54 47 39 92

B: 500 °C 2.80 1.18 0.27 81 62 43 151650 °C 2.28 0.75 0.63 52 47 37 90

C: 500 °C 3.13 1.30 0.44 69 59 44 116650 °C 1.56 0.57 0.78 50 42 33 75

D: 500 °C 2.66 1.29 0.37 85 63 45 136650 °C 1.63 0.73 0.79 57 45 38 81

E: 500 °C 2.74 1.14 0.30 80 62 43 148650 °C 2.13 0.68 0.60 53 46 36 93

Fig. 3. AFM images taken from samples A, C, D and E displaying thecatalyst nanoparticles after activation

in surface roughness is only minor, and unlikely to be the

cause for the change in growth. Sample D displays the

largest change. It appears the TiN layer was partly sputtered

forming clusters of small particles. The surface morphology

of sample D is changed extensively, which could account for

the observed change in CNT growth on these samples.

To further examine the influence of the TiN layer treatment

on the CNT growth we also performed AFM on samples on

which Fe was deposited and activated for catalyst growth.

The samples were placed in the CNT reactor after Fe

evaporation, followed by 3 minutes of annealing at 500 °C,

while H2 was flowing. After this the samples are cooled down

in a N2 environment. Fig. 3 displays the AFM results. As

can be seen both sample A and E display small nanoparticles

of similar size (the bigger bright spots on sample A are

most likely particles deposited on the wafer during HNO3

treatment). The same holds for sample B (not shown here).

On sample C and D, however, beside the small nanopar-

ticles a significant amount of larger nanoparticles can be

found. This will result in CNT growth with large diameter

distribution and, most likely, lower density. This can explain

the absence for self-alignment at low growth temperature

for samples C and D. It can also explain the higher crystal

quality observed by Raman spectroscopy on those samples.

As found by Antunes et al. [12] CNT grown from larger

nanoparticles at the same temperature show a lower ID/G,

ID’/G and FWHM, and a higher IG’/G. This does, however,

not account for the large ID/G ratio observed for the low

temperature C sample. Sample D has low temperature Raman

data which matches closer with that obtained from sample E.

Indeed the nanoparticle distribution of sample D is, compared

to sample C, more similar to that of sample E.

Increased surface roughness of sample D is most likely

the cause of the observed broader particle deposition. For

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Fig. 4. SEM images taken from CNT growth in contact openings a) before,and b) after metallisation.

sample C we believe that the oxidation of the TiN surface

due to the oxygen plasma (in case of our Ti/TiN stack sheet

resistance increases from 1.158 Ω/� to 1.165 Ω/�) alters

the surface properties in such a way that activation of the

catalyst layer becomes more difficult.

B. IV-characterisation of top-down integrated CNT

We created 4-point probe vertical interconnect measure-

ment structures using a top-down approach as described

in the experimental section. In order to protect the TiN

layer from damage during plasma etching we sputtered an

additional 100 nm of Ti on top of this layer before TEOS

deposition. During the contact opening etching we land

on this layer, without completely removing it. Before Fe

evaporation we remove the sacrificial layer by a short 60 sec.

etch in 0.55 % HF. Using this method we are able to grow

perfectly aligned high-density bundles of CNT within contact

openings at 500 °C, see also Fig. 4.a). As the CNT height

was controlled to be the same as the depth of the opening

no planarization is required for the 2nd metallisation. As can

be seen in Fig. 4.b) good contact is achieved, although some

irregularities exist between the bulk metal and the metal on

the CNT due to the small spacing between the oxide and

CNT bundle.

We measured the resisitivity of square and round CNT

bundles with different sizes. The resulting IV-characteristics

of the square structures can be found in Fig. 5. As can be

seen all structures display good linearity, indicating good

metal-CNT contact without large Schottky barriers.

The resistivities of the structures can be found in Fig 6.

For comparison we also added values of several publica-

tions found in literature [13]–[16]. As can be seen smaller

structures suffer from an increase in resistivity, probably

caused by a combination of a not yet optimized lithographic

process which slightly under-sizes the smaller structures and

more difficulty in growing CNT into smaller openings. A

good match can be found between the square and round

structures, indicating that for this size there is no preferential

morphology for creating CNT vertical interconnect bundles.

We also measured the resistivity of structures consisting of

four smaller bundles spaced by 3 μm with a total area of a

larger bundle (e.g. 4x 4 μm to get the same area as a single

8 μm bundle). As can be seen from Fig. 6 the resistivity of

a single large bundle is always lower than several smaller

bundles.

Fig. 5. IV-measurements of structures with different bundle size

Compared to other values found in literature our average

resistivity of 350 mΩ-cm is between the lowest and highest

found. It must be noted that the value from Yokoyama et al

[14] is achieved with structures fabricated with very specific

equipment after a long optimization process, while our re-

ported values are not yet optimized. Our growth temperature

(500 °C) is relative low compared to the temperatures used

by Dijon et al. (590 °C, [13]), Choi et al. (600 °C, [15])

and Kreupl et al. (700 °C, [16]). We believe our resistivity

can still be reduced by at least one order of magnitude by

optimizing our process.

As the CNT all have diameters between 20-40 nm the

grown CNT are multi-walled, which implies they are all

(semi-)metallic [17]. This is confirmed by the Raman spectra

(not shown here), which don’t show any radial breathing

modes, the fingerprints of single-walled CNT [18]. In or-

der to accurately determine the average tube resistivity we

require the contact resistance, which is non neglectable for

CNT. Currently we are working on fabricating structures with

different lengths in order to estimate the contact resistance,

and thus the tube resistivity.

C. Covering CNT for bottom-up

In order to allow low-temperature bottom-up integration

CNT have to be covered by a low-temperature dielectric, in

contrast to the high temperature LPCVD TEOS used by Li

et al. [5]. For low-temperature dielectric deposition PECVD

is the preferred method in the semiconductor industry. How-

ever, it is likely that the plasma might damage the grown

CNT by ion bombardment or oxidation. To investigate this

we grew free-standing bundles of CNT with a height of

approximately 5 μm on TiN substrates (Fig. 7.a)) and covered

them with PECVD TEOS (tetraethyl orthosilicate), silicon

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Fig. 6. Calculated resistivity of structures with different diameter andmorphology compared to other values found in literature.

Fig. 7. SEM images of: a) free-standing bundles grown on TiN, b) bundlescovered by 1 μm TEOS, c) bundles covered by 5 μm SiO2, d) bundlescovered by 200 nm Si3N4

oxide and nitride at temperatures of 350 °C for the TEOS

deposition, and 400 °C for the others.

Fig. 7.b) shows a SEM image taken of an array of 5x5

2 μm wide CNT bundles covered by 1 μm TEOS. As can

be seen good step coverage is achieved, although deposition

on the side-walls of the CNT is lower compared to the total

thickness of the TEOS layer (approximately 600 nm). In

Fig. 7.c) the same array is completely covered by 5 μm of

PECVD oxide (deposited from SiH4 and N2O). As can be

seen planarization will be necessary to remove the excess

oxide. Finally, Fig. 7.d) shows the array covered by 200 nm

silicon nitride (from SiH4 and NH3). As can be seen the

deposition is significantly less smooth compared to the oxide

depositions.

Using Raman spectroscopy we investigated the CNT crys-

tallinity before and after PECVD dielectric deposition of

1 μm of TEOS or oxide and 200 nm nitride. As can be

seen in Fig. 8 only minor changes to the crystallinity can

be observed. The TEOS deposition appears to induce the

Fig. 8. Raman spectra of CNT before and after covering with PECVDdielectrics. The intensity is normalized to the G-band at 1580 cm-1.

least amount of damage, with only the width of the D band

(around 1330 cm-1) increasing slightly. Oxide deposition

from silane, on the other hand, displays an increase of the D

band, indicating less crystallinity. The width of the D band is

similar to that of the D band after TEOS deposition. Finally,

nitride deposition has a D band intensity in between that

of CNT covered by TEOS and oxide. Again the width of

the D band is similar to that of TEOS covered CNT. In

the second order band region changes are even smaller (not

shown here). We can thus conclude that PECVD deposition

does not induce a significant amount of defects in the

CNT bundles, opening up the possibility to use this method

for low-temperature bottom-up integration. Especially TEOS

deposition appears to be an attractive candidate.

We are currently working on fabricating bottom-up mea-

surements structures, in order to compare both integration

schemes. Furthermore, we plan to perform reliability mea-

surements for both integration schemes.

IV. CONCLUSIONS

We demonstrated high density low-temperature vertically

aligned growth of CNT on conductive layers deposited

on Si substrates. It was found that plasma bombardment

can damage the TiN diffusion barrier, while wet chemical

cleaning has no apparent impact. From AFM measurements

it was observed that plasma treated samples show larger

catalyst nanoparticles after activation. This can account for

the lack of self-aligned vertical growth at low temperature.

With a sacrificial Ti layer damage can be prevented.

Using this approach we successfully created vertical CNT

measurement structures, displaying low resistivity and good

Ohmic contacts. Finally, we demonstrate that it is possible

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to use PECVD dielectrics to cover CNT without inducing

significant damage, which can be used for bottom-up pro-

cesses. Especially TEOS appears to be an attractive candi-

date, introducing hardly any changing in CNT crystallinity.

Both methods provide us with simple and effective methods

to fully integrate CNT as vertical interconnects in silicon

process technology.

V. ACKNOWLEDGMENTS

The authors would like to thank M. R. Tajari Mofrad for

assistance performing the electrical measurements.

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