led front-end manufacturing trends 2014 report by yole developpement

Copyrights © Yole Développement SA. All rights reserved.© 2014 1

75 cours Emile Zola, F-69001 Lyon-Villeurbanne, FranceTel : +33 472 83 01 80 - Fax : +33 472 83 01 83Web: http://www.yole.fr

LED FRONT-END MANUFACTURING TRENDS

A Comprehensive Survey of LED Front-End Manufacturing, Covering Main Process and Technological Trends

SAMPLE VERSION

http://www.yole.fr/

© 2014 2Copyrights © Yole Développement SA. All rights reserved.

About the Author of the Report

Pars MUKISH - Senior Analyst

Pars MUKISH holds a Master of Materials Science & Polymers and a Master of

Innovation & Technology Management (EM Lyon - France).

He works at Yole Développement as a Senior Market and Technology Analyst in the

fields of LED, Lighting Technologies, Compound Semiconductors and OLED to carry

out technical, economic and marketing analysis.

Previously, he has worked as Marketing and Techno-Economic Analyst for several

years at the CEA.

Pars MUKISH is also author / co-author of the following reports:

• LED Packaging

• Status of the LED Industry

• LED in Road and Street Lighting

• OLED for Lighting

• UV LED Technology and Application Trends

• LED Front End Equipment Market


Objectives of the Report

• To better understand process flow andtechnological trends in LED front-endmanufacturing.

• To better understand the importance of costreduction in LED front-end manufacturing.

• To evaluate emerging substrates / technologies(GaN-on-GaN LEDs and GaN-on-Si LEDs).


Company Index

ACC Silicon, Accretech, Advanced Dicing Technology, Advanced System Technology (AST), Advatool Semiconductor, Aixtron,ALSI, Altatech (Soitec), AM Technology, AMEC, AND Corporation, Applied Materials, APT, Arima, ASM Pacific Technology,ASML, Astri, Aurotek, Autec, Azzurro, Bayer, Beijing Yuji, Bergquist, Bridgelux, Bruker, Canon, Cascade Microtech, ChinaElectronics Technology Group Corporation (CETC), Chroma, Corial, Cree, Crystal Applied Technology (SAS), Crystal Optech,Crystalwise, Dai Nippon Kaken (DNK), Dai Nippon Screen Mfg, Daitron, Delphi Laser, Denka, Disco, Dow Corning, DowElectronic Materials, Dynatex, Edison Opto, Epiluxy, Epistar, Eplustek, ESI, Eulitha, EV Group (EVG), Evatec, EverlightElectronics, Fittech, Formosa Epitaxy (Forepi), Four N4, Fraunhofer IZM, FSE Corporation (Fulintec), Galaxia, GE, GloAB, HansLaser, Hansol Technics, Hauman, Heliodel, Hitachi Cable, Huga, Hybond, Iljin Display, IMEC, Intematix, InVacuo, Ismeca, JCT,JPSA, JT Corp, Jusung Engineering, K&S, KLA Tencor, Lattice Power, Laurier, Laytech, LG Innotek, Lightscape, LightwavePhotonic, Litec, Loomis, Luminus Devices, LWB, Maxis Co, Merk/Litec, Mitsubishi, Mitsubishi Diamond Industrial, MolecularImprint, Momentive, Monocrystal, MPI, Nanoco, Nanometrics, Nanosys, Nichia, Nihon Gartner, Nikon, NN Crystal, NorthMicroelectronics, Novellus, NTT, Nusil, Obducat, Oerlikon Systems, OP System, Optest, Opto Supply Ltd, Orbotech, Osram,Oxfrod Instrument Plasma Technology, Palomar Technology, Panasonic, Philips Lumileds, Phosphortech, Plasma-Therm,Procrystal, Proway, Puji Optical, QD Vision, QMC, Quatek, Rigidtek, Rose Street Lab, Rubicon, Rudolph, Samco, Samsung,Sanken, Semileds, Seoul Semiconductors, Sharp, Shibuya, Sino American Silicon (SAS), Sino Kristals Optoelectronics, SinoNitride, Sky Technology, SNTEK, SPTS, Stararc, Sumitomo Chemical, Suss Microtech, Synova, Tainics, Taiyo Nippon Sanso,Tamarack, Tecdia, Technology & Science Enabler (TSE), Tekcore, Temescal, TeraXtal, Toyoda Gosei, Transluscent, TSMC,Ultratech, Ulvac, Uni Via Technology, Ushio, Varian, Veeco, Verticle, Wacker, Waferworks, Wellypower, WentworthLaboratories, Withlight, YCChem, Ying Lyu, Zeon Chemical (…).


Table of Content (1/5)

• Objectives of the Report P8

• Company Index & Glossary P9

• Executive Summary P11

• LED Market Trends P30

– History of LED Industry

– Packaged LED Revenue Forecast by Application

– LED Adoption Rate - 2013 vs. 2020

– Recent Trends

– Packaged LED Price Trends

– LED Die Surface Forecast by Application

– GaN Reactor Capacity - Geographic Trends

– LED Reactors

• Geographic Trends & Impact on Global Demand

• GaN Reactor Capacity vs. Demand

• Key Constituents of LED Die P42

– Synthesis

– Overview

– Mirrors

• Overview

• Resonant Cavity LEDs

– Introduction

– Status

– Technology

– Pads, Electrodes and Contacts

• Overview

• Transparent Contact layers - ITO and Alternatives

• Deposition Process

• Trends

– Dielectric Layers

• Introduction

• Passivation

• Trends

• LED Die Manufacturing P61

– Synthesis

– LED Manufacturing Yield

• Overview

• Focus on Binning Yields

• Cost Aspects

– Cost Structure of Lighting Products

– The Path to Cost Reduction

– 1W Packaged LED Cost Analysis

• Overview

• Consumables and Labor

• Equipment Cost

– GaN LED Chip Design

• Simple MESA

• Flip Chip (FC)

• Vertical Thin Film (VTF)

• Thin Film Flip Chip (TFFC)

• Vertical Thin Film with Vias (VTFV)

• Trend - Increase of Flip Chip Technology

– LED Manufacturing Process Overview

– Front-End Manufacturing Process Flow

• Example - MESA Structure

• Example - VTF Structure

• Other Steps



• Light Extraction Techniques P84

– LED Chip Patterning

– Substrate Patterning or Die Shaping

– Novel Chip Geometries

• LED Substrates (1/2) P89

– Introduction

– Sapphire-based LED - Breakdown by Epitaxial Material (2008-2020)

– Focus on GaN and Si Substrates

– Penetration Rate by Substrate Type

– Sapphire Substrate

• Wafer ASP

– Introduction

– Trends

– Long Term Expectations

• Diameter Trends

– Overview

– Transition to Larger Size Wafer

– 8” or not 8”?

• Patterned Sapphire Substrate (PSS)

– Benefits

– Use

– Examples

– Pattern Types

– Manufacturing Process

– Key Players

– Adoption Trends

– Price Trends

• Market Forecast and Trends

– Si Substrate

• Introduction

• Benefits

• Challenges

– Overview

– Focus on TEC Mismatch

• Chip Design

• How to Grow LED structures on Si?

• Potential Impact of using Si for LED Manufacturing

• Conditions for Success

• Performance and Commercial Status

– Overview (1/2)

– Toshiba TL1F1 Teardown

• Binning Yields

• CMOS Compatibility

– Overview

– Gold Contamination

– Dedicated LED Equipment

• Si vs. Sapphire - LED Die Cost Simulations

• Overview of Potential Cost Reduction Claims

• Market Players

• Recent Comments

• Reality or Fiction?

• Scenarios of Evolution



• LED Substrates (2/2) P89

– GaN Substrate

• Introduction - Droop Effect

• Benefits

– Device Performance

– Manufacturing

– Vertical Structure

• Challenges

– Substrate Availability and Cost

– Thermal Management

• Applications Overview

• GaN vs. Sapphire - LED Die Cost Simulations

• Status

• LED Epitaxy (1/2) P154

– Synthesis

– GaN LED Epitaxy

• Introduction to MOCVD

• MOCVD Reactor System Overview

• GaN LED Structures

• GaN LED Epitaxy Challenges

– Overview

– Focus on Wafer Curvature

• Packaged LED Cost Structure

• Cost of Ownership

– Drivers

– Cost Reduction Opportunities

• Focus on Binning Yields

– GaN LED Epitaxy

• Focus on In Situ Metrology

– Overview

– Correlation with LED Parameters

– Wafer Curvature

• Focus on LED Epitaxy Cycle Time

– Downtime and Cleaning

– Hybrid Reactors

• Focus on Batch Size

• Focus on Growth Rate

• Focus on Precursor Efficiency

• Toward Larger Diameter Wafers – Incentive

– Overview

– Focus on MOCVD Throughput

– Focus on Manufacturing Cost

• Next Generation MOCVD Reactor

– MetalOrganic (MO) Precursors

• Introduction

• TMG

– Overview

– ASP

– Alternative - TEG

• TMI

– Overview

– ASP

– Challenge

• Purity Aspects



• LED Epitaxy (2/2) P154

– Nanowire LEDs

• Introduction

• Main Players

– Overview

– Company Profile - Aledia

– Company Profile - glō

– Company Profile - Nanocrystal

– Company Profile - Ecosparck

• Conclusion

• Lithography P212

– Synthesis

– LED Chip Manufacturing

• Main LED Lithography Steps

• Other LED Lithography Steps

• Example of a Vertical LED

• Requirements and Challenges

– Overview

– Focus on Mask Alignment / Overlay

• Lithography Techniques for LED

– Contact / Proximity (Aligners)

– Projection - Steppers

– Projection - Full Field

– Comparison

• Focus on Wafer Bowing

• Focus on Mask and Photoresist

• Legacy Lithography Tools for LED Manufacturing

• Dedicated Lithography Tools for LED Manufacturing

– PSS Manufacturing

• Overview of Lithography for PSS

• Nano-Imprint Lithography (NIL)

• Hard Stamps vs. Soft Stamps

• Displacement Talbot Lithography (DTL)

• Advanced Mask Aligner Lithography (AMALITH)

• Current Status

• Plasma Etching and Deposition (1/2) P242

– Synthesis

– Overview of Etching Techniques

– Plasma Etching

• Overview

• Illustrations

– Reactive Ion Etching (RIE)

• Overview

• Inductively Coupled Plasma-RIE (ICP-RIE)

– LED Etching Requirements

– LED Etching Specificities

– Dielectric Layer Deposition

• Overview

• Requirements

• LED Manufacturing

• Alternative Technologies for Passivation

– Process Control and Metrology

• Tool-Based

• Plasma Metrology

• Optical Measurement

• Conclusion



• Plasma Etching and Deposition (2/2) P242

– Reactor Cleaning

• Etching Tools

• Deposition Tools (PECVD)

– Examples of Etching and PECVD Equipment for LED Manufacturing

– Other Plasma Processes in LED Manufacturing - Surface Cleaning

• Physical Vapor Deposition for TCL and Metals P268

– Synthesis

– Transparent Contact Layer

• Overview

• Critical Parameters

• Deposition Technologies

– Metal Deposition

• Overview

• MESA and Flip Chip Structure

• Vertical Thin Film Structures

– TCL and Metal Deposition Equipment

• Automation

• Main Suppliers

• LED-Dedicated System Suppliers

• Examples

• Testing and Binning P284

– Synthesis

– Introduction

– Overview of LED Testing and Sorting/Binning

– Example of Testing Workflow in LED Manufacturing

– Measurement Challenges

– Wafer Level and Die Testing

– Optical Inspection and Probing

– Sorting & Binning

– Equipment, Capex and Throughput

– Examples

• Optical and Visual Inspection

• Wafer, Die Testers and Sorters

– Software

• Conclusion P299

• About Yole Développement and LED Activity P303


Overview of Key Constituents of LED Die

1. For details of the epitaxial structure, please refer to the chapter “LED Epitaxy” of the report.

Package Substrate (Ceramic, metal, MCPCB…)

n-GaN

p-GaN

MQW

Substrate

Mirror

Metal pads are where electrical

charges are injected into the

structure. They are connected via

wires of stud bumping to the

electrodes or connectors on the

package substrate.

Electrodes or transparent contacts

distribute and spread the electrical

carriers into the structure.

On some structures, insulation layers (not present here) provide

appropriate electrical isolation between the different elements

The light is generated in the Multi-

Quantum Well (MQW) where the

electrons and holes are injected

through the p-doped and n-doped

GaN layers1.

A mirror reflects the light

emitted in the direction of

the substrates. A diffusion

barrier is used on some

structures to prevent

diffusion of the Ag mirror into

the eutectic AuSn , or

diffusion and reaction of Al

with N atoms when using

Ti/Al contacts on n-side (not

necessary here).

The top layer can be textured to

improve light extraction (photonic

crystal of roughening).

The surface of the substrate

can be textured to improve

light extraction.

Passivation layers limit

parasitic surface currents

and degradation of the die.


MirrorsResonant Cavity LEDs - Technology

• Mirrors can be of 3 types:

– Metal.

– Metal / Dielectric layers combination (Hybrids).

– Full dielectric layers (Distributed Bragg Reflectors).

• Main criteria of choice are:

– Substrate material used.

– Wavelength range targeted (bin).

– LED chip geometry developed (and associatedangular range).

– LED packaging technique used.

Metal / Dielectric - Hybrids Full Dielectric - DBRs

Typical Number of Layers 6 - 20 15 - 70

Typical Thickness (µm) 0.5 - 2 1 - 6

Comments

• Increase reflectance in a limited wavelength

region is possible by adding some dielectric

layers.

• Highest reflectance over wide wavelength range.

• Can be designed with transparency window for

alignment laser of dicing tool.

• Very accurate thickness monitoring required.

Reflectance of a Sapphire-based LED with DBR and Silver mirror in package

Source: Evatec


Front End Cost Aspects1W Packaged LED Cost Analysis

• Front-end manufacturing represents 48% of the cost of the 1W packaged LED analyzed in this example.

• At 33% of the total Front-End cost, epitaxial layers (grown by MOCVD) represents the single largest costreduction opportunity.

• However, substrates (in this case sapphire + a carrier wafer on which the epiwafer is subsequentlybonded to) also represent a significant fraction (25%).


GaN LED Chip DesignTrend - Increase of Flip Chip Technology

• As flip chip technology gradually matures, LED manufacturers are actively developing this technology as itgives several advantages.

– Larger light-emitting area and highest luminosity.

– Better heat dissipation.

– Adjustable dimensions.

– No wire-bonding.

• Whereas such design was mostly in hand of big LED manufacturers (Cree, Lumileds…), in 2013, Taiwanesemanufacturers have also started to develop this technology.

• Additionally, and following the increased use of middle power LEDs for General lighting applications, flipchip technology should also make its way into the middle power LED market in 2014.

– Recently (Q4-2013), Lumileds has announced its plans to introduce flip-chip technology into the middle power LEDmarket as such type of device has drawn most attention from the market in 2013.

– Indeed, middle power LEDs (following the 2011 / 2012 overcapacity) have become mainstream in interior lightingapplications.

Flip Chip (FC) technology as the new battleground with Taiwanese companies racing to start production and some companies planning to develop FC LED for middle power market.


Light Extraction TechniquesNovel Chip Geometries

• Studies have been realized by the Semiconductor Lighting and Display Laboratory of The University ofHong Kong, which examined the light extraction efficiency of LEDs with different geometries:

• These studies have concluded that square LEDs have distinctively lower extraction efficiencies than anyother shape.

– Considering the fact that LED chips in the market are invariably diced into squares or rectangles, device designersshould give thought to redesigning the chip.

Novel chip geometries, such as triangular and hexagonal devices, can deliver massive increases in light extraction by cutting optical confinement in both the vertical and horizontal directions.

ShapeLight Extraction

Efficiency

Square 12.98%

Pentagon 15.09%

Triangle 15.07%

Heptagon 14.54%

Octagon 14.43%

Hexagon 14.39%

Circle 13.98%

Light Extraction Efficiencies of LED Chips

with Different Geometries

Source: Semiconductor Lighting and

Display Laboratory

Laser-Micromachined LED Chips

with Different Geometries

Source: Semiconductor Lighting

and Display Laboratory

Triangle Chip

manufactured by

Soraa

Source: Soraa

Hexagonal Chip

manufactured by

Verticle

Source: Verticle


Focus on GaN and Si Substrates

• GaN-on-Si LEDs aims at improving solid-state lighting Cost of Ownership (COO) by reducing thecomponent manufacturing cost.

– The success of GaN-on-Si LEDs will depend on development of associated LEDs performance (which should at leastbe equal to GaN-on-Sapphire LEDs) and development of manufacturing techniques (allowing to capitalize ondepreciated CMOS fab).

• GaN-on-GaN LEDs purports to reduce COO by improving the quantity of light per die area, and thereforeallow cost reduction at the system level through reduction of the number of packages.

– The success of GaN-on-GaN LEDs will depend on the availability of 2” and 4” GaN substrates in large volumes and ata lower cost than currently available.

COST =

$

LUMEN

Manufacturing Efficiency

• Higher equipment throughput and

yields

• Economy of scale

LED Performance

• Higher efficiency (lumen/W)

• More light per chip (driving current)

GaN-on-Si LEDs→ Reduce component

cost

GaN-on-GaN LEDs→ Improve performance

by reducing the number

of packages per System


Sapphire Substrates (CSS and PSS)Market Forecast and Trends (1/2)


GaN-on-Si LEDsSi vs. Sapphire - LED Die Cost Simulations

• In this simulation, GaN-on-Si LED chip structures were compared to the closest available Sapphire-basedstructure → Vertical LED with substrate removal by laser lift off.

• However other sapphire structure exist that are cheaper to manufacture. For example PSS-based LED nowoffer very competitive manufacturing cost and performance close to state of the art vertical LEDs.

The simulations show a potential cost reduction of -XX to XX% at the die level vs. a 4” sapphire vertical LED:

Notes:

• Front End = Epitaxy + Si carrier preparation

+ Wafer processing + Bonding + Epi

substrate removal.

• Back End 0 = Probe test + Scribing

Include yield costs (cumulated cost of all

the rejected die).


GaN-on-GaN LEDsApplications - Overview

• GaN-on-GaN LEDs are not for all applications:

– The benefit of GaN based LED is only realized at high current density (for very high luminous flux).

– Because droop is still present, GaN LED will often trade flux for efficiency.

• Initial penetration will start with applications requiring very high flux over small surfaces and were precisebeam shaping is critical.

• GaN based LED will not be favored in applications requiring a more diffuse light pattern or when energyefficiency is the main driver for LED adoption.

Potential for applications requiring

very high flux over small surfaces and

precise beam shaping

Not appropriate in applications

requiring a diffuse light pattern or

when energy efficiency is paramount

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GaN LED EpitaxyCost of Ownership - Drivers

The cost of ownership of a MOCVD system is driven by multiple factors:

YIELDS

Uniform gas flow: binning yields

Uniform substrate temperature:

binning yields

Process control, in situ metrology

THROUGHPUT

Number and size of wafer

per batch

Layer deposition speed

Equipment uptime (maintenance, cleaning, etc.)

Loading, unloading time,

Automation

Reactor and wafer temperature ramp

up and cooling

Operating and depreciation

costs

Upfront equipment

cost

Precursor utilization efficiency

Energy Costs

Labor cost

System Footprint


Toward Larger Diameter WafersIncentive - Focus on Manufacturing Cost (3/3)

• This indicates that the transition to 6” can be beneficial for LED makers with strong experience and “worldclass” manufacturing practices.

Source: Philips Lumileds (June 2013)

Last 2 Quarters of 3”

Manufacturing (mix) 150mm Manufacturing

Only


Nanowire LEDsIntroduction

Nanowires (also called nanorods, nanocolumns…) = 100 to 500nm diameter GaN wires.

Each nanowire acts as an individual LED. Blue, green and red GaN based LED can be realized.

Source: Glo


LithographyExample of a Vertical LED

For a vertical LED, 6 lithography steps are generally required.

Metal Layer

p-GaN

n-GaN

MQW

Metal Layer

Conductive Substrate

Backside Electrode

Step 6: n-Pad

Metal Contact

Resolution = XXum

Step 5: Passivation

XX

Resolution > 5µm

Step 3: n-GaN

XX

Resolution > 5µm

Step 4: Isolation

Hardmask for Dry Etch

Resolution > XXµm

Step 1: Current Blocking

XX

Resolution = 5µm

Step 2: p-Pad

Ohmic Contact

Resolution = XXµm


Plasma EtchingIllustrations

Patterned Sapphire Substrate

Source: Corial

Photonic Crystal

Source: SUSS MicroTec

GaN MESA

Source: Plasma-Therm

LED Die streets

Source: Plasma-Therm


TCL and Metal Deposition EquipmentExamples

SNTEK:

InVacuo:

• e-beam evaporation for deposition of metal or ITO layers

• Dome wafer holder (Lift-off or planetary type)

• Capacity → 186 x 2” for ITO and 100 x 2” for Metal

• Source → e-beam ( 4 ~ 6 pocket 40cc)

• ITO deposition Temperature → 300℃ on wafer

• Mark IV E-beam evaporation system for deposition of metal and ITO layers

• Hemispherical wafer holder → 42 x 2” for single planetary / 108 x 2” and 24 x 4”

for three planetary

Copyrights © Yole Développement SA. All rights reserved.© 2014 25

75 cours Emile Zola, F-69001 Lyon-Villeurbanne, FranceTel : +33 472 83 01 80 - Fax : +33 472 83 01 83

Web: http://www.yole.fr

Yole Développement and LED Activity

http://www.yole.fr/


Yole DéveloppementField of Research Activity

• Yole Développement is a market research and strategy consulting company founded in 1998.

• We are involved in the following areas:

• Our research is performed by in-house personnel conducting open-ended discussions based oninterviews.

– 30 full time analysts with technical and marketing degrees.

– Primary research including over 3,500 interviews per year.

Photovoltaic

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Sensors

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Power Electronics

LED, OLED and Laser Diode

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Packaging


Yole Développement4 Business Models

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Published Reports:

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Custom

Analysis

Breadth of the Analysis

Dep

th o

f th

e A

naly

sis

Standard Reports

Workshops

Q&A

Services

Research products - Content comparison


LED Activity Yole is Active All Over the LED Value Chain

We are active all over the value chain! And we interview industrial / R&D players from each level!

Substrate Front-end Level 0 - Epitaxy• Nucleation layer

• N-type layer

• Active layers (MQW)

• P-type layer

SiC / Sapphire / Silicon /

Bulk GaN / Composite

substrate

LED epi-wafer

Mesa LED structure

Flip Chip LED structure

Vertical LED structure

LED dies-on-waferLED dies

Back-End level 1 - Packaging• Die Attach & Interconnections

• Phosphors

• Encapsulation & optics

• Testing & Binning

Packaged LEDs

Front-end Level 1 - Device Making• Inspection

• Masking / Lithography

• Etching

• Metallization / Contacts / Mirrors

Back-End Level 0 - Packaging• Substrate separation & Bonding

• Die singulation

• Testing & Binning

LED systems and applications

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LED ActivityAbout Yole’s LED Analyst Team

Dr. Philippe ROUSSEL - Business Unit Manager

Philippe ROUSSEL holds a Ph-D in Integrated Electronics Systems from the National

Institute of Applied Sciences of Lyon (INSA - France). He joined Yole Développement

in 1998 and is Business Unit Manager of the Compound Semiconductors, Photovoltaic,

LED and Power Electronics department.

Dr. Eric VIREY - Senior Analyst

Eric VIREY holds a Ph-D in Optoelectronics from the National Polytechnic Institute of

Grenoble (INPG - France). In the last 12 years, he has held various R&D, engineering,

manufacturing and marketing positions with Saint-Gobain. Most recently, he was

Market Manager at Saint-Gobain Crystals, in charge of Sapphire and Optoelectronic

products.

Pars MUKISH - Senior Analyst

Pars MUKISH holds a master degree in Materials Science & Polymers and a master

degree in Innovation & Technology Management (EM Lyon - France). He works at Yole

Développement as Market and Technology Analyst in the fields of LED and Lighting

Technologies to carry out technical, economic and marketing analysis. Previously, he

has worked as Marketing and Techno-Economic Analyst for several years at the CEA.

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led front-end manufacturing trends 2014 report by yole developpement

Technology

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