issues in system on the chip clocking november 6th, 2003 soc design conference, seoul, korea

Issues in System on the Chip Clocking

November 6th, 2003SoC Design Conference, Seoul, KOREA

Vojin G. OklobdzijaAdvanced Computer System Engineering LaboratoryUniversity of California DavisPresentation available at: http://www.ece.ucdavis.edu/acsel

Prof. V.G. Oklobdzija, University of California

Directions in SoC Clocking

Synchronous / Asynchronous paradigmSynchronous solutions:Clock uncertainty absorptionTime borrowingSkew-Tolerant DominoUsing both edges of the clockConclusion


Clock frequency trendsISSCC-2002


PIII

IBM-G4

Cray-1 S

Cray-X-MP

CDC-Cyber

IBM 3090

MIPS-X

Alpha 21064

Alpha 21164

UltraSparc II

IBM S/390

Alpha 21264

Exponential

PowerPC

Alpha 21164

PIII Xeon

Athlon

Athlon

Pentium 4

Itanium

Pentium 4

Itanium

Athlon2100

Athlon1900

0

500

1000

1500

2000

2500

3000

1975

1980

1985

1990

1995

2000

2005

Year

Nominal Clock Frequency (MHz)

Processor Frequency Trends Frequency doubles each generation Number of gates/clock reduce by 25%Courtesy of: Intel, S. Borkar


Multi-GHz Clocking ProblemsFewer logic in-between pipeline stages: Out of 7-10 FO4 allocated delays, FF can take 2-4 FO4Clock uncertainty can take another FO4The total could be of the time allowed for computation


Clock Uncertainties


Ref_Clock

DRV_CLK

t

Received Clock

skew

t

RCV_CLK

t

T

jit

t

-

jit

t

+

skew

t

Clock uncertainty:jitter+skew

Motivation for Improving on Clocked Storage ElementsExample:In a 2.0 GHZ processor T=500pSTypically clocked storage element D-Q delay is in the order of 100-150pSIf one can design a faster CSE: e.g. 80-100pS D-Q, this represents 10-15% performance improvementIf in addition one can absorb 20pS of clock uncertainties and embedd one level of logic this can yield up to 20% performance improvement

Try to achieve 10-20% performance improvement by introducing new features in the architecture !This is sufficient to turn an architect into a circuit designer !


Consequences of multi-GHz ClocksPipeline boundaries start to blurClocked Storage Elements must include logicWave pipelining, domino style, signals used to clock ..Synchronous design only in a limited domainAsynchronous communication between synchronous domains


Synchronous / Asynchronous Design on the Chip1 Billion transistors on the chip by 2005-664-b, 4-way issue logic core requires ~2 MillionTable 1: Transistor count in typical RISC processors

FeatureDigital21164MIPS 10000PowerPC620HP 8000SunUSFreq. [MHz]500200200180250Pipeline Stg. 75-757-96-9Issue Rate44444Out-of-Ord. 6 loads321656noneReg-Ren./flpnone/832/328/856noneTotal Trans.9.3M5.9M6.9M3.9M3.8MLogic Trans.1.8M2.3M2.2M3.9M2.0M


Synchronous / Asynchronous Design on the Chip1 Billion Transistors Chip10 million transistors


Two views of the world:- Asynchronous- Synchronous


Asynchronous ParadigmLogic Stage can take any time it needsMax. Speed limited by Handshake overheadIncreased complexity of logic (de-glitching)


Logic 1

Logic 2

Logic 3

Hadnshake overhead

Hadnshake overhead

Compute time 1

Compute time 3

Compute time 2

Data

Handshake signals

Handshake signals

Data

Synchronous ParadigmMax Speed determined by the slowest logic blockLatch / FF timing overheadFixed clock frequency (set by longest path)


Logic 1

Logic 2

Logic 3

Compute time 1

Compute time 3

Compute time 2

Data

Data

CSEoverhead

CSEoverhead

CSEoverhead

Waiting

Waiting

Clock

Data

Data

Synchronous ParadigmClocked Storage Elements: Flip-Flops and Latches should be viewed as synchronization elements, not merely as storage elements ! Their main purpose is to synchronize fast and slow paths:prevent the fast path from corrupting the state


Present State:

S

n

Path Blocker

(CSE)

Clock

Next State

S

n+1

S

n+1

= f (S

n

, X)

Outputs (Y)

Y=Y(X, S

n

)

Inputs (X)

Combinational

Logic

Blocker

Transparent

logic signals

adjusted not to

arrive earlyer

Signal Blocked

can not corrupt present

state S

n

signals

blocked

Orderly change of

state from

S

n

to

S

n+1

at this point

Synchronous World: Tricks and SolutionsClocked Storage Elements with clock uncertainty absorption featuresTime BorrowingIncorporation of Synchronization features into the logicSkew Tolerant DominoUtilizing both edges of the Clock


Clocked Storage Element Overhead The time taken from the pipeline by the CSE is U and Clk-Q delay. Thus, D-Q delay is relevant, not Clk-Q :T = TClk-Q + TLogic + U+ TskewNDQClkDQClkLogicTLogicTClk-QUTTD-Q=TClk-Q + UTskew


Delay vs. Setup/Hold TimesSampling Window



]Chart21

0.00000000030.0000000002

0.00000000030.0000000002

0.00000000030.0000000002

0.00000000030.0000000002

0.00000000030.0000000002

0.00000000030.0000000002

0.00000000030.0000000002

0.00000000030.0000000002

0.00000000030.0000000002

0.00000000020.0000000002

0.00000000020.0000000002

0.00000000020.0000000002

0.00000000020.0000000002

0.00000000020.0000000002

0.00000000020.0000000003

0.00000000020.0000000003

0.00000000020.0000000003

0.00000000020.0000000003

0.00000000030.0000000004

0.00000000090.0000000009

tSU-OPT

tDQmin

Stable Region

Metastable Region

Failure

Td-q

Tclk-q

Clock to Data Delay

Data to Output Delay


]Sheet1

Borin FF1. T modif2. PT modmoj ffBorin FF1. T modif2. PT modmoj ff

d-qd-qb

3.30E-103.17E-103.09E-103.26E-103.20E-103.10E-10-1003.30E-103.20E-103.10E-10

3.11E-103.04E-102.99E-103.17E-103.04E-102.97E-10-903.17E-103.04E-102.99E-10

3.10E-102.97E-102.89E-103.05E-102.99E-102.93E-10-803.10E-102.99E-102.93E-10

2.93E-102.89E-102.82E-102.98E-102.86E-102.79E-10-702.98E-102.89E-102.82E-10

2.92E-102.80E-102.72E-102.87E-102.79E-102.75E-10-602.92E-102.80E-102.75E-10

2.78E-102.71E-102.63E-102.83E-102.69E-102.61E-10-502.83E-102.71E-102.63E-102.23E-102.63E-10

2.73E-102.63E-102.54E-102.68E-102.62E-102.56E-10-402.73E-102.63E-102.56E-102.56E-102.19E-10

2.56E-102.53E-102.45E-102.61E-102.53E-102.41E-10-302.61E-102.53E-102.45E-102.09E-102.44E-10

2.56E-102.46E-102.36E-102.50E-102.46E-102.39E-10-202.56E-102.46E-102.39E-102.38E-102.05E-10

2.40E-102.37E-102.29E-102.45E-102.34E-102.25E-10-102.45E-102.37E-102.29E-101.99E-102.27E-10

2.38E-102.30E-102.19E-102.23E-102.32E-102.31E-102.23E-102.63E-1002.38E-102.31E-102.23E-102.63E-102.23E-101.98E-10

2.24E-102.25E-102.17E-102.56E-102.31E-102.23E-102.12E-102.19E-10102.31E-102.25E-102.17E-102.56E-101.92E-102.14E-10

2.26E-102.20E-102.07E-102.09E-102.20E-102.19E-102.12E-102.44E-10202.26E-102.20E-102.12E-102.44E-102.09E-101.94E-10

2.16E-102.16E-102.09E-102.38E-102.23E-102.15E-102.03E-102.05E-10302.23E-102.16E-102.09E-102.38E-101.90E-102.01E-10

2.20E-102.12E-101.99E-101.99E-102.14E-102.13E-102.05E-102.27E-10402.20E-102.13E-102.05E-102.27E-101.99E-101.93E-10

2.13E-102.13E-102.05E-102.23E-102.19E-102.12E-101.99E-101.98E-10502.19E-102.13E-102.05E-102.23E-101.90E-101.94E-10

2.17E-102.13E-102.00E-101.92E-102.11E-102.14E-102.05E-102.14E-10602.17E-102.14E-102.05E-102.14E-101.95E-101.92E-10

2.15E-102.22E-102.07E-102.09E-102.20E-102.22E-102.02E-101.94E-10702.20E-102.22E-102.07E-102.09E-101.90E-101.93E-10

3.25E-102.56E-102.21E-101.90E-102.19E-102.53E-102.24E-102.01E-10803.25E-102.56E-102.24E-102.01E-101.95E-101.93E-10

2.38E-10failed5.35E-101.99E-108.51E-10failed6.96E-101.93E-10908.51E-106.96E-101.99E-101.91E-101.93E-10

failedfailedfailed1.90E-10failedfailedfailed1.94E-101001.94E-101.96E-101.95E-10

1.95E-101.92E-101101.95E-101.94E-101.94E-10

1.90E-101.93E-101201.93E-101.96E-101.98E-10

1.95E-101.93E-101301.95E-102.01E-101.95E-10

1.92E-101.91E-101.93E-101401.93E-101.97E-102.28E-10

1.95E-101.96E-101.95E-101501.96E-103.03E-101.93E-10

1.95E-101.94E-101.94E-101601.94E-10

1.92E-101.96E-101.98E-101701.98E-102.27E-102.67E-10

1.90E-102.01E-101.95E-101802.01E-102.67E-102.30E-10

1.93E-101.97E-102.28E-101902.28E-102.34E-102.69E-10

1.95E-103.05E-101.93E-102003.05E-102.70E-102.38E-10

1.93E-102.00E-107.09E-102107.09E-102.43E-102.72E-10

1.91E-102.74E-102.50E-10

1.93E-102.57E-102.79E-10

1.96E-102.80E-102.64E-10

1.95E-102.73E-102.84E-10

1.94E-102.91E-102.84E-10

1.94E-102.92E-102.96E-10

1.96E-103.07E-103.04E-10

1.98E-103.14E-103.18E-10

2.01E-103.27E-103.25E-10

1.95E-103.34E-103.37E-10

1.97E-103.47E-103.46E-10

2.28E-103.58E-103.58E-10

3.69E-103.70E-10

3.85E-103.79E-10

3.88E-104.19E-10

5.07E-103.97E-10

2.20E-102.10E-102.02E-102.16E-102.13E-102.04E-10-1002.20E-102.13E-102.04E-10

2.14E-102.10E-102.06E-102.20E-102.10E-102.03E-10-902.20E-102.10E-102.06E-10

2.21E-102.11E-102.03E-102.16E-102.13E-102.08E-10-802.21E-102.13E-102.08E-10

2.16E-102.15E-102.09E-102.21E-102.12E-102.05E-10-702.21E-102.15E-102.09E-10

2.96E-102.22E-102.13E-102.06E-102.16E-102.12E-102.09E-10-602.22E-102.13E-102.09E-10

2.99E-102.20E-102.16E-102.09E-102.25E-102.15E-102.07E-10-502.25E-102.16E-102.09E-10

3.07E-102.24E-102.17E-102.08E-102.18E-102.15E-102.10E-10-402.24E-102.17E-102.10E-10

3.04E-102.17E-102.17E-102.10E-102.23E-102.18E-102.06E-10-302.23E-102.18E-102.10E-10

3.14E-102.26E-102.19E-102.09E-102.20E-102.19E-102.12E-10-202.26E-102.19E-102.12E-10

3.18E-102.22E-102.23E-102.15E-102.28E-102.20E-102.11E-10-102.28E-102.23E-102.15E-10

3.27E-102.30E-102.25E-102.14E-102.27E-102.24E-102.25E-102.18E-102.91E-1002.30E-102.25E-102.18E-102.91E-10

3.25E-102.26E-102.31E-102.22E-102.67E-102.32E-102.29E-102.17E-102.63E-10102.32E-102.31E-102.22E-102.97E-10

3.34E-102.38E-102.36E-102.22E-102.34E-102.32E-102.34E-102.28E-102.95E-10202.38E-102.36E-102.28E-102.95E-10

3.37E-102.39E-102.42E-102.35E-102.70E-102.45E-102.41E-102.30E-102.67E-10302.45E-102.42E-102.35E-102.96E-10

3.47E-102.53E-102.49E-102.36E-102.43E-102.47E-102.50E-102.41E-102.94E-10402.53E-102.50E-102.41E-102.94E-10

3.47E-102.55E-102.58E-102.51E-102.74E-102.60E-102.57E-102.45E-102.72E-10502.60E-102.58E-102.51E-102.94E-10

3.58E-102.70E-102.69E-102.56E-102.57E-102.64E-102.70E-102.62E-102.97E-10602.70E-102.70E-102.62E-102.97E-10

3.58E-102.75E-102.86E-102.71E-102.80E-102.80E-102.86E-102.66E-102.80E-10702.80E-102.86E-102.71E-102.96E-10

3.69E-103.96E-103.30E-102.95E-102.73E-102.90E-103.27E-102.99E-103.00E-10803.96E-103.30E-102.99E-103.00E-10

3.70E-103.20E-10failed6.20E-102.91E-109.32E-10failed7.80E-102.93E-10909.32E-107.80E-102.98E-10

3.85E-10failedfailedfailed2.92E-10failedfailedfailed3.05E-101003.05E-10

3.79E-103.07E-103.09E-101103.09E-10

3.88E-103.14E-103.18E-101203.18E-10

4.19E-103.27E-103.26E-101303.27E-10

5.10E-103.34E-103.35E-101403.35E-10

3.97E-103.47E-103.47E-101503.47E-10

3.58E-103.56E-101603.58E-10

3.69E-103.65E-101703.69E-10

3.85E-103.77E-101803.85E-10

3.88E-103.84E-101903.88E-10

5.07E-103.98E-102005.07E-10

4.11E-109.20E-102109.20E-10

]Sheet1

000

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&A

Page &P

SAFF

First Modification

Second Modification

Clock to Data Delay [ps]

Data to Output Delay [s]


]Sheet2

0000

0000

0000

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&A

Page &P

SAFF

First Modification

Second Modification

New Realization




]Sheet3

000

000

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SAFF

First Modification

Second Modification


Clock to Output Delay [s]

Clock to Output Delay

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

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0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

SAFF

First Modification

Second Modification

New Realization




-1002.77E-102.71E-103.58E-102.62E-10

-902.40E-102.70E-104.06E-102.92E-10

-802.57E-102.47E-103.31E-102.39E-10

-702.25E-102.51E-103.87E-102.72E-10tdlaydq1=2.42E-10

-602.42E-102.28E-103.10E-102.21E-10tdlaydq2=2.04E-10

-502.13E-102.32E-103.63E-102.55E-10tdlaydq3=2.25E-10

-402.25E-102.09E-102.92E-102.01E-10tdlaydq4=1.97E-10

-302.03E-102.12E-103.46E-102.33E-10tdlaydq5=2.11E-10

-202.12E-101.93E-102.77E-101.83E-10tdlaydq6=1.95E-10

-101.97E-101.92E-103.29E-102.13E-10tdlaydq7=1.99E-10

02.02E-101.77E-102.63E-101.65E-102.42E-10tdlaydq8=1.93E-10

101.94E-101.72E-103.04E-101.92E-102.04E-10tdlaydq9=1.93E-10

201.99E-101.70E-102.56E-101.53E-102.25E-10tdlaydq10=1.95E-10

301.93E-101.55E-102.83E-101.71E-101.97E-10tdlaydq11=1.93E-10

401.96E-101.67E-102.51E-101.53E-102.11E-10tdlaydq12=1.95E-10

502.02E-101.53E-102.70E-101.53E-101.95E-10tdlaydq13=1.94E-10

604.09E-101.66E-102.50E-101.54E-101.99E-10tdlaydq14=1.94E-10

702.59E-102.50E-101.33E-101.93E-10tdlaydq15=1.95E-10

801.65E-102.56E-101.62E-101.93E-10tdlaydq16=1.93E-10

902.29E-101.14E-101.95E-10tdlaydq17=1.95E-10

1002.76E-101.90E-101.93E-10tdlaydq18=1.93E-10

1101.95E-10tdlaydq19=1.94E-10

1201.94E-10tdlaydq20=2.10E-10

1301.94E-10tdlaydq21=failed

1401.95E-10tdlayclkq1=2.51E-10

1501.93E-10tdlayclkq2=2.20E-10

1601.95E-10tdlayclkq3=2.56E-10

1701.93E-10tdlayclkq4=2.34E-10

1801.94E-10tdlayclkq5=2.62E-10

1902.10E-10tdlayclkq6=2.51E-10

200tdlayclkq7=2.69E-10










tdlayclkq17=3.64E-10




tdlayclkq21=failed

-1001.80E-101.64E-102.48E-101.54E-10

-901.53E-101.74E-103.10E-101.99E-10

-801.82E-101.61E-102.43E-101.53E-10

-701.57E-101.74E-103.09E-101.97E-10

-601.85E-101.61E-102.40E-101.52E-10

-501.65E-101.75E-103.05E-101.99E-10

-401.89E-101.62E-102.42E-101.52E-10

-301.75E-101.74E-103.08E-101.97E-10

-201.96E-101.65E-102.47E-101.54E-10

-101.90E-101.75E-103.12E-101.99E-10

02.08E-101.71E-102.54E-101.58E-102.51E-10

102.06E-101.75E-103.07E-101.98E-102.20E-10

202.25E-101.85E-102.67E-101.66E-102.56E-10

302.27E-101.78E-103.07E-101.98E-102.34E-10

402.43E-102.03E-102.82E-101.87E-102.62E-10

502.55E-101.95E-103.13E-101.99E-102.51E-10

603.67E-102.21E-103.02E-102.08E-102.69E-10

703.20E-103.12E-101.99E-102.69E-10

802.38E-103.26E-102.33E-102.82E-10

903.12E-102.00E-102.91E-10

1003.65E-102.82E-103.01E-10

1103.11E-10

1203.24E-10

1303.31E-10

1403.45E-10

1503.48E-10

1603.64E-10

1703.69E-10

1803.83E-10

1904.06E-10

200

210

220

230

240

250

260

270

280

290

0000

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CCFF

SDFF

ProposedStructure

Modified Structure




00000

00000

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0

CCFF

SDFF

ProposedStructure

Modified Structure

New Structure




0000

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&A

Page &P

CCFF

SDFF

Proposed Structure

Modified Structure




00000

00000

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00000

00000

00000

00000

00000

00000

00000

00000

0

0

0

0

CCFF

SDFF

Proposed Structure

Modified Structure

New Structure




ccffsdffproposedmodifiedmy

powff1010=2.60E-042.15E-045.73E-042.57E-042.15E-04powff1010=2.15E-04

powinv21010=1.03E-049.11E-058.93E-059.41E-051.01E-04powinv21010=1.01E-04


pow1010=5.49E-044.99E-048.56E-045.48E-044.94E-04pow1010=4.94E-04




pow1100=4.10E-044.18E-046.51E-044.50E-043.89E-04pow1100=3.89E-04




pow1111=2.42E-044.02E-047.81E-044.62E-042.75E-04pow1111=2.75E-04




pow0000=3.14E-042.44E-043.89E-043.22E-042.78E-04pow0000=2.78E-04

CircuitData PowerClock Power

oldsaffPT saff 1PT saff 2my

powff1010=2.58E-042.98E-043.08E-043.76E-04

powdata10101.76E-041.76E-041.77E-041.96E-04

powinv61010=1.90E-041.84E-041.84E-041.84E-04

pow1010=6.25E-046.59E-046.68E-047.56E-04

powff1100=1.86E-042.21E-042.27E-042.73E-04

powdata11009.21E-059.19E-059.22E-051.02E-04

powinv61100=1.90E-041.84E-041.84E-041.84E-04

pow1100=4.68E-044.97E-045.03E-045.60E-04

powff1111=1.06E-041.51E-041.53E-041.77E-04

powdata11117.21E-084.88E-087.87E-084.73E-09

powinv61111=1.90E-041.84E-041.84E-041.84E-04

pow1111=2.97E-043.35E-043.36E-043.60E-04powff1010=3.76E-04

powff0000=1.06E-041.51E-041.53E-041.77E-04powinv21010=9.81E-05

powdata00007.21E-084.88E-087.87E-084.73E-09powinv41010=9.81E-05

powinv60000=1.90E-041.84E-041.84E-041.84E-04powinv61010=1.84E-04

pow0000=2.97E-043.35E-043.36E-043.60E-04pow1010=7.56E-04

powff1100=2.73E-04

powinv21100=5.12E-05

powinv41100=5.12E-05

powinv61100=1.84E-04

pow1100=5.60E-04

powff1111=1.77E-04

powinv21111=4.20E-09



pow1111=3.60E-04

powinv21100=4.61E-054.59E-054.61E-055.12E-05powff0000=1.77E-04


powinv40000=4.20E-09


powinv41111=1.92E-091.53E-092.46E-095.31E-10pow0000=3.60E-04

powinv20000=1.92E-091.53E-092.46E-095.31E-10

powinv40000=7.02E-084.73E-087.62E-084.20E-09

1010110011110000

00000

00000

00000

CCFF

SDFF

Proposed

Modified

New Circuit

Power [W]

Power Consumption with Input Sequence 1010....

00000

00000

00000

CCFF

SDFF

Proposed

Modified

New Circuit

Power [W]


00000

00000

00000

CCFF

SDFF

Proposed

Modified

New Circuit

Power [W]


00000

00000

00000

CCFF

SDFF

Proposed

Modified

New Circuit

Power [W]


00000

00000

00000

00000

CCFF

SDFF

Proposed FF

Modified

New FF

Power [W]

Overall Power Consumption Comparison

0000

0000

0000

SAFF

PT SAFF 1

PT SAFF 2

New FF

Power [W]


0000

0000

0000

SAFF

PT SAFF 1

PT SAFF 2

New FF

Power [W]


0000

0000

0000

SAFF

PT SAFF 1

PT SAFF 2

New FF

Power [W]


0000

0000

0000

SAFF

PT SAFF 1

PT SAFF 2

New FF

Power [W]


0000

0000

0000

0000

SAFF

PT SAFF 1

PT SAFF 2

New FF

Power [W]

Overall Power Consumption Comparison

Clock Uncertainty Absorption


200

220

240

260

280

300

320

340

100

80

60

40

20

0

-20

-40

-60

D-Clk delay [ps]

D-Q delay [ps]

Early Clk

Nominal Clk

Late Clk

D

DQ

=238ps

Clk

Single-Ended Skew Tolerant Flip-FlopNedovic, Oklobdzija, Walker, ISSCC 2003


Clock Uncertainty AbsrobtionClock uncertainty tCUDQClkWorst-case DDQNominal DD-ClkDDQmDDQMEarly DD-ClkLate DD-ClkTNominal=0


Clock Uncertainty AbsorptiontCU=100ps44psUOpt=30psDDQM=261pstCU=30ps3psUOpt=-5psDDQM=220psClkDQClkDQ(b) tCU=100ps (aCU=56%)(a) tCU=30ps (aCU=90%)


Time Borrowing


D

Q

Q

D

Q

Q

Combinational

logic

Source

Destination

Clock

Clock

Clock

Data (cycle-

1)

sampling

window

T

CR

1

Cycle

2

Cycle

1

T

CR

2

T

CR

1

> T

CR

2

D

Clk-Q

D

D-Q

Clock

reference

edge

sampling

window

Critical Path with Time Borrowing


L3

D

Q

L2

D

Q

L1

D

Q

L7

D

Q

L6

D

Q

L5

D

Q

Logic 1a

Logic 1b

Logic 2a

L4

D

Q

Logic 2b

Logic 3a

Logic 3b

D1

D2

D3

D4

D5

D6

D7

Q1

Q2

Q3

Q4

Q5

Q6

F1

F1

F1

F1

F2

F2

F2

Logic 1a, L2, Logic 1b, L3, Logic 2a

Logic 2b, L5, Logic 3a, L6, Logic 3b

Stage 1

Stage 2

Stage 3

U

D1

Q1

D4

Q4

D7

3 P + W - tCU

F1

F2

DCQ

W

P

edge1 (late arrival)

edge8 (early arrival)

edge2

edge3

edge4

edge7

edge6

edge5

Latches as synchronizersThe purpose of CSE it is to synchronize data flow.We need to insert CSE to prevent fast paths from reaching the next logic stage too early.If the signal arrives late it is allowed to borrow time from the next stageHowever, borrowing can not go for ever ..


Using Single Pulsed Latch


Logic 1

Logic 2

Logic 3

T

Data

Data

Wopt

Fast path

Waiting

Slow path

Borrowed time

Clock Pulse

Data

Data

Single Pulsed Latch*Courtesy of D. Markovic & Intel MRL


Optimal Single Latch ClockingSingle Latch System (Unger & Tan 83):

Pm=P DLM+DDQM {miminal clock period}DLm>DLmBW+TT+TL+H-DCQm {shortest path}Wopt=TL+TT+U+DCQM-DDQM {minimal clock width}Example: 0.10m Technology

FO4=25-40pS, FF=80pS, Tunc=25-35pS, fmax=2.5-4. GHz, T=250-400pSWopt~2Tunc~50-70pSDLm~4Tunc+H-DCQm~100-140pS {this is close to of a cycle}


Synchronous World: Tricks and SolutionsClocked Storage Elements with clock uncertainty absorption featuresTime BorrowingIncorporation of Synchronization features into the logicSkew Tolerant Domino

Utilizing both edges of the Clock


Skew-Tolerant Domino

(a.k.a. Opportunistic Time Borrowing)Intel Patent No.5,517,136 May 14, 1996


CMOS Domino as Memory ElementAfter the input changes output remembers itPre-charge destroys the informationProper phasing of the clock can allow passing the information from stage to stage


Logic

Clock

evaluate

precharge

Monotonic transition of the output

Monotonic transition of the input

Dynamic node - acting as memory element

Memory element

Skew-Tolerant Domino


DominoLogic Stage 1

Clock F1

Clock F2

Clock F3

Clock F1

Clock F2

Clock F3

Transfer of data from 1 to 2

Could be eliminated: Footless Domino

Eliminated latches

Fast path stops here

Slow path has to pass its value to the next stage by now

Pipline stage 1

Pipline stage 3

Pipline stage 2

DominoLogic Stage 3

DominoLogicStage 2

Dual-Edge Triggered CSEDET-CSE samples the input data on both edges of the clockReducing power consumptionHalf of the original clock frequency for the same data throughputHalf of clock generation/distribution/SE-clock-related power is savedHowever, it may introduce an overhead


D

Q

Q

D

Clk

Q

Clk

D

Q

Dual-Edge Triggered Storage Element TopologiesStructurally, there are two different designs Latch-Mux (LM)Flip-Flop (FF)DET-Flip-FlopDET-LatchNon-transparency achieved by MUX


Q

C

D

Qb

Q

C

D

Qb

0

1

D

Clk

Q

S

C

D

R

S

C

D

R

Q

R

S

Qb

Clk

D

Q

Qb

Comparison with Single Edge SEs


Chart1

299.7322

353.6268

291.8374

SE

DE

Delay [ps]

Chart2

123.2111.6

141.1158.3

128.5125.7

SE

DE

Total Power [W]

Chart3

36.935.9

49.942.5

37.547.1

31.745.5

Single Edge

Dual Edge

EDP [fJ/500MHz], [fJ/250MHz

Sheet1

SEDESEDESingle EdgeDual Edge

TGLM/MS299.7322123.2111.636.935.9

C2MOS353.6268141.1158.349.942.5

TGFF291.8374128.5125.737.547.1

TSPC242.5329130.7140.331.745.5

Sheet2

Sheet3

Comparison with Single Edge CSEs


Chart1

213.9171

197.9179.7

216.9241

189.3210.2

SE

DE

Ptot[W] For Activity 1

Chart2

45.929.1

75.150.3

81.470.8

42.278.6

SE

DE

Ptot[W] for Activity Vdd

Chart3

3321

60.440.8

65.259.6

120.846.7

SE

DE

Ptot[W] for Activity gnd

Sheet1

SEDESEDESEDE

PowPC213.917145.929.13321

TG197.9179.775.150.360.440.8

C2MOS216.924181.470.865.259.6

TSPC189.3210.242.278.6120.846.7

Chart4

213.9171

216.9241

197.9179.7

189.3210.2

32.820.2

65.359.6

60.241.8

29.662

3321

65.259.6

60.440.8

120.846.7

SE

DE

Total Power [W]

Chart7

123.2111.6

141.1158.3

128.5125.7

130.7140.3

213.9171

216.9241

197.9179.7

189.3210.2

32.820.2

65.359.6

60.241.8

29.662

3321

65.259.6

60.440.8

120.846.7

SE

DE

Total Power [W]

Sheet2

SEDE

Activity = 0.5TGMS/LM123.2111.6

C2MOS141.1158.3

TGFF128.5125.7

TSPC130.7140.3

Activity = 1TGMS/LM213.9171

C2MOS216.9241

TGFF197.9179.7

TSPC189.3210.2

Activity = 0 [1s]TGMS/LM32.820.2

C2MOS65.359.6

TGFF60.241.8

TSPC29.662

Activity = 0 [0s]TGMS/LM3321

C2MOS65.259.6

TGFF60.440.8

TSPC120.846.7

Chart8

27.527.3

30.119.8

32.120.5

8.77.8

SE

DE

Clock Power [uW]

Chart9

110.8122.9

97.8115.4

8083.3

110.5104.7

SE

DE

Internal Power [uW]

Sheet3

SEDESEDE

PowPC27.527.3110.8122.9

TGCPFF30.119.897.8115.4

C2MOS32.120.58083.3

TSPC8.77.8110.5104.7

Single and Double Edge Triggered SE: Power Consumption (a=50%)


Chart10

8032.111.1

83.320.57.8

110.827.52.8

122.927.38.1

110.58.79.3

104.77.813.2

97.830.12.8

115.419.85.1

Internal Power

Clock Power

Data Power

Power [uW]

Sheet1

Delay [ps]

TGMS300

C2MOS354

HLFF188

SDFF169

SE CCFF247

SAbFF169

DE CCFF169

DTFF217

DTFF-rp166

DTFF-sym173

CPFF202

ACPFF203

imCCFF257

GFLFF155

Total Power

PowPCTGMS123.2

C2MOSC2MOS141.1

SAbFFHLFF183.8

HLFFSDFF224.9

SDFFSE CCFF153.4

DE CCFFSAbFF107.9

SE CCFFDE CCFF132.1

ICCD'00124.5

Izmena1166.2DTFF124.5

Izmena2157.4DTFF-rp166.2

CPFF146.3DTFF-sym157.4

ACPFF118.5CPFF146.3

imCCFF121.7ACPFF118.5

imCCFF121.7

PDP [fJ]PDP [fJ]

PowPC36.9TGMS36.9

C2MOS49.9C2MOS49.9

SAbFF18.2HLFF34.5

HLFF34.5SDFF38.1

SDFF38.1SE CCFF37.9

DE CCFF22.3SAbFF18.2

SE CCFF37.9DE CCFF22.3

ICCD'0027

Izmena130.7DTFF27

Izmena226.9DTFF-rp30.7

CPFF29.6DTFF-sym26.9

ACPFF30CPFF29.6

imCCFF31.3ACPFF30

imCCFF31.3

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

5

7

6

10

9

8

11

14

13

12

1

4

3

2

5

7

6

10

9

8

11

13

12

1

4

3

2

5

7

6

10

9

8

11

13

12

1

4

3

2

5

7

6

10

9

8

11

13

12

1

4

3

2

6

5

1

4

3

2

6

5

1

4

3

2

6

5

Sheet2

Delay [ps]Internal Power [uW]Clock Power uW]Data Power [uW]Total Power [uW]PDP [fJ]

TGMS3008032.111.1123.236.9

C2MOS354110.827.52.8141.149.9

HLFF188161.3184.718434.5

SDFF169188.634.12.2224.938.1

SE CCFF247112.518.51514637.9

DTFF217112.610.91124.527

DTFF-rp166149.315.31.6166.230.7

DTFF-sym173143.5112.8157.326.7

CPFF20211724.44.614629.6

ACPFF203118.524.45.114830

imCCFF257110.810.2112231.3

SAFF274875.21.393.525.7

SA 11028391.55.21.498.127.7

SA-Based169100.85.81.3107.918.2

DE CCFF169112.5172.6132.122.3

GFLFF15595.96.61.510416.1

DUAL EDGEPI [W]PCLK[W]PD[W]

PowerPC8032.111.1

DETTGLM83.320.57.8

SETC2MOS110.827.52.8

SETFFstsu [ps]tD [ps]PI [W]PCLK[W]PD[W]PTOT[W]PDP [fJ]DETC2MOS122.927.38.1

TGMS1603008032.111.1123.236.9SETTGFF110.58.79.3

C2MOS100354110.827.52.8141.149.9DETTGFF104.77.813.2

TGCPFF50292110.58.79.3128.537.5SETTSPC97.830.12.8

TSPC8024297.830.12.8130.731.7DETTSPC115.419.85.1

DETFFstrsu [ps]tf su [ps]tD1[ps]tD2 [ps]PI [W]PCLK[W]PD[W]PTOT[W]PDP [fJ]

TGLM12011532232283.320.57.8111.635.9

C2MOS5852266268122.927.38.1158.342.5

TGCPFF9368372374104.77.813.2125.747.1

TSPC7482319329115.419.85.1140.345.5

Sheet2

8032.111.1

110.827.52.8

161.3184.7

188.634.12.2

112.518.515

112.610.91

149.315.31.6

143.5112.8

11724.44.6

118.524.45.1

110.810.21

Internal Power

Clock Power

Data Power

Power [uW]

Power Consumption Break-up - Single-Ended Designs

Sheet4

000

000

000

000

Internal Power

Clock Power

Data Power

Power [uW]

Power Consumption Break-up - Differential Designs

Sheet3

000

000

000

000

000

Internal Power

Clock Power

Data Power

Power [uW]

Power Consumption Break-up - Single-Ended Designs

000

000

000

000

000

000

000

000

Internal Power

Clock Power

Data Power

TGMSC2MOSHLFFSDFFSE CCFFSAbFFDE CCFF

tD [ps]300354188169247169169

PI [mW]80110.8161.3188.6127.3100.8112.5

PCLK [mW]32.127.51834.118.55.817

PD [mW]11.12.84.42.77.71.32.6

PTOT [mW]123.2141.1183.8224.9153.4107.9132.1

PDP [fJ]36.949.934.538.137.918.222.3

name# XtorsWidthdelayinternalclockdatatotalpdp

1- TGMS1632.6403115.54502

2- HLFF2047.1301028.72.31133.4

3- SDFF2353.130132171.21514.6

4- C2MOS24823412414.671465

5- SA-F/F19753111716.81.41354.3

6- StrongArm2075.43312416.81.31424.7

1 2 3 4 5 6

50116154158154162

31102132124117124

91171388195100

9.55182835764

1- PowerPC 603

2- HLFF

3- SDFF

4- mC2MOS

5- SA-F/F

6- StrongArm

Data patterns

Internal Power [uW]

1 2 3 4 5 6

1 2 3 4 5 6

1 2 3 4 5 6

1 2 3 4 5 6

1 2 3 4 5 6

1 2 3 4 5 6

1 2 3 4 5 6

1 2 3 4 5 6

1 2 3 4 5 6

1 2 3 4 5 6

1- TGMS Latch

2- HLFF

3- SDFF

4- C2MOS

5- SA-F/F

6- StrongArm

Clock Power [uW]

15.5

8.7

17

14.6

16.8

16.8

1 2 3 4 5 6

1 2 3 4 5 6

1 2 3 4 5 6

MBD00019EF2.xls

MBD000A8E56.xls

MBD000AA60D.xls

MBD00158CA2.xls

Chart4

15.58.71714.616.816.8

1- TGMSLatch

2- HLFF

3- SDFF

4- C2MOS

5- SA-F/F

6- StrongArm

Clock Power [uW]

Sheet1

name# of transistorsTotal transistor Widthdelayinternalclockdatatotal

1- TGMSLatch1632.6403115.5450

2- HLFF2047.1301028.72.3113

3- SDFF2353.130132171.2151

4- C2MOS24823412414.67146

5- SA-F/F19753111716.81.4135

6- StrongArm2075.43312416.81.3142

7- K6 ETL3762.12529894.5311

Sheet1

1- TGMSLatch

2- HLFF

3- SDFF

4- C2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL

# of transistors

Sheet2

1- TGMSLatch

2- HLFF

3- SDFF

4- C2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL

Total transistor Width [um]

Sheet3

1- TGMSLatch

2- HLFF

3- SDFF

4- C2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL

Delay [ps]

1- TGMSLatch

2- HLFF

3- SDFF

4- C2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL

Internal Power [uW]

1- TGMSLatch

2- HLFF

3- SDFF

4- C2MOS

5- SA-F/F

6- StrongArm

Clock Power [uW]

MBD0015FE06.xls

Chart2

345.36.65.56

23.44.654.34.7

13.754.683.2643.4723.861

11.772.973.3322.2322.64

1- PowerPC 603

2- HLFF

3- SDFF

4- mC2MOS

5- SA-F/F

6- StrongArm

Data patterns

PDPtot [fJ]

Sheet1

name# of transistorsWidthdelayinternalclockdatatotalpdp

1- TGMS Latch1632.6403115.54502

2- HLFF2047.1301028.72.31133.4

3- SDFF2353.130132171.21514.6

4- C2MOS24823412414.671465

5- SA-F/F19753111716.81.41354.3

6- StrongArm2075.43312416.81.31424.7

7- K6 ETL3762.12529894.53118

Sheet1

1- TGMS Latch

2- HLFF

3- SDFF

4- C2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL

# of transistors

Sheet2

1- TGMS Latch

2- HLFF

3- SDFF

4- C2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL


Sheet3

1- TGMS Latch

2- HLFF

3- SDFF

4- C2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL

Delay [ps]

1- TGMS Latch

2- HLFF

3- SDFF

4- C2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL

Internal Power [uW]

0000000

1- TGMS Latch

2- HLFF

3- SDFF

4- C2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL

Clock Power [uW]

1- TGMS Latch

2- HLFF

3- SDFF

4- C2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL

PDP TOT [fJ]

internal powerActivity=1Activity=0.5Activity=0(vdd)Activity=0(gnd)

1- PowerPC 603503199.5

2- HLFF11610211751

3- SDFF15413213882

4- mC2MOS1581248183

5- SA-F/F1541179557

6- StrongArm16212410064

7- K6 ETL300298295293

PDP

1- PowerPC 6033211

2- HLFF43.43.751.77

3- SDFF5.34.64.682.97

4- mC2MOS6.653.2643.332

5- SA-F/F5.54.33.4722.232

6- StrongArm64.73.8612.64

7- K6 ETL8.187.67.5

total power

1- PowerPC 60374502525

2- HLFF13011312559

3- SDFF17415115699

4- mC2MOS1901469698

5- SA-F/F17413511272

6- StrongArm18114211780

7- K6 ETL320311304300

0000000

0000000

0000000

0000000

1- PowerPC 603

2- HLFF

3- SDFF

4- mC2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL

0000000

0000000

0000000

0000000

1- PowerPC 603

2- HLFF

3- SDFF

4- mC2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL

Data patterns

PDPtot [fJ]

MBD00F2B3AE.xls

Chart3

403030343133

1- TGMS Latch

2- HLFF

3- SDFF

4- C2MOS

5- SA-F/F

6- StrongArm

Delay [ps]

Sheet1

name# of transistorsTotal transistor Widthdelay

1- TGMS Latch1632.640

2- HLFF2047.130

3- SDFF2353.130

4- C2MOS248234

5- SA-F/F197531

6- StrongArm2075.433

7- K6 ETL3762.125

Sheet1

0000000

1- PowerPC 603

2- HLFF

3- SDFF

4- mC2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL

# of transistors

Sheet2

0000000

1- PowerPC 603

2- HLFF

3- SDFF

4- mC2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL


Sheet3

0000000

1- TGMS Latch

2- HLFF

3- SDFF

4- mC2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL

Delay [ps]

MBD00F2AED2.xls

Chart5

31102132124117124

1- TGMS Latch

2- HLFF

3- SDFF

4- C2MOS

5- SA-F/F

6- StrongArm

Internal Power [uW]

Sheet1


1- TGMS Latch1632.6403115.5450

2- HLFF2047.1301028.72.3113

3- SDFF2353.130132171.2151

4- C2MOS24823412414.67146

5- SA-F/F19753111716.81.4135

6- StrongArm2075.43312416.81.3142

7- K6 ETL3762.12529894.5311

Sheet1

0000000

1- PowerPC 603

2- HLFF

3- SDFF

4- mC2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL

# of transistors

Sheet2

0000000

1- PowerPC 603

2- HLFF

3- SDFF

4- mC2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL


Sheet3

0000000

1- PowerPC 603

2- HLFF

3- SDFF

4- mC2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL

Delay [ps]

0000000

1- TGMS Latch

2- HLFF

3- SDFF

4- C2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL

Internal Power [uW]

0000000

1- TGMS Latch

2- HLFF

3- SDFF

4- C2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL

Clock Power [uW]

MBD00158CA3.xls

Chart5

31102132124117124

1- TGMS Latch

2- HLFF

3- SDFF

4- C2MOS

5- SA-F/F

6- StrongArm

Internal Power [uW]

Sheet1


1- TGMS Latch1632.6403115.5450

2- HLFF2047.1301028.72.3113

3- SDFF2353.130132171.2151

4- C2MOS24823412414.67146

5- SA-F/F19753111716.81.4135

6- StrongArm2075.43312416.81.3142

7- K6 ETL3762.12529894.5311

Sheet1

0000000

1- PowerPC 603

2- HLFF

3- SDFF

4- mC2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL

# of transistors

Sheet2

0000000

1- PowerPC 603

2- HLFF

3- SDFF

4- mC2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL


Sheet3

0000000

1- PowerPC 603

2- HLFF

3- SDFF

4- mC2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL

Delay [ps]

0000000

1- TGMS Latch

2- HLFF

3- SDFF

4- C2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL

Internal Power [uW]

0000000

1- TGMS Latch

2- HLFF

3- SDFF

4- C2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL

Clock Power [uW]

MBD000AA60F.xls

MBD00158CA1.xls

Chart3

403030343133

1- TGMS Latch

2- HLFF

3- SDFF

4- C2MOS

5- SA-F/F

6- StrongArm

Delay [ps]

Sheet1

name# of transistorsTotal transistor Widthdelay

1- TGMS Latch1632.640

2- HLFF2047.130

3- SDFF2353.130

4- C2MOS248234

5- SA-F/F197531

6- StrongArm2075.433

7- K6 ETL3762.125

Sheet1

0000000

1- PowerPC 603

2- HLFF

3- SDFF

4- mC2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL

# of transistors

Sheet2

0000000

1- PowerPC 603

2- HLFF

3- SDFF

4- mC2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL


Sheet3

0000000

1- TGMS Latch

2- HLFF

3- SDFF

4- mC2MOS

5- SA-F/F

6- StrongArm

7- K6 ETL

Delay [ps]

MBD000AA60E.xls

MBD000AA60B.xls

MBD000AA60C.xls

MBD000A8E57.xls

MBD0006D3B2.xls

MBD000A8E54.xls

MBD000A8E55.xls

MBD000A8E51.xls

MBD00067645.xls

MBD00069ADF.xls

MBD0005C525.xls

MBD0000B281.xls

MBD00017754.xls

MBD00018195.xls

MBD00019116.xls

MBD00017755.xls

MBD0000BAFE.xls

MBD00017753.xls

MBD0000B8CF.xls

MBD0000770C.xls

MBD0000B0CA.xls

Fo4=2.9


Chart7

20.48960.91941.75447.38471.8373.00440.69155.5555555556111.1111111111166.6666666667222.2222222222277.7777777778

20.45763.48344.58367.03375.01476.165129.9652.6315789474105.2631578947157.8947368421210.5263157895263.1578947368

76.626129.27100.12111.58132.73134.11103.1850100150200250

112.09162.16128.47142.7162.03163.14133.847.61904761995.2380952381142.8571428571190.4761904762238.0952380952

201.65260.84209.38223.22249.16250.21183.9945.454545454590.9090909091136.3636363636181.8181818182227.2727272727

43.478260869686.9565217391130.4347826087173.9130434783217.3913043478

41.666666666783.3333333333125166.6666666667208.3333333333

4080120160200

38.461538461576.9230769231115.3846153846153.8461538462192.3076923077

37.03703703774.0740740741111.1111111111148.1481481481185.1851851852

35.714285714371.4285714286107.1428571429142.8571428571178.5714285714

34.482758620768.9655172414103.4482758621137.9310344828172.4137931034

33.333333333366.6666666667100133.3333333333166.6666666667

32.258064516164.516129032396.7741935484129.0322580645161.2903225806

31.2562.593.75125156.25

30.30303030360.606060606190.9090909091121.2121212121151.5151515152

29.411764705958.823529411888.2352941176117.6470588235147.0588235294

28.571428571457.142857142985.7142857143114.2857142857142.8571428571

27.777777777855.555555555683.3333333333111.1111111111138.8888888889

27.02702702754.054054054181.0810810811108.1081081081135.1351351351

26.315789473752.631578947478.9473684211105.2631578947131.5789473684

25.64102564151.282051282176.9230769231102.5641025641128.2051282051

255075100125

Our designs

50fJ/250MHz

40fJ/250MHz

30fJ/250MHz

20fJ/250MHz

10fJ/250MHz

TGLM

C2MOS

TGFF

TSPC

DETACPFF

DETCPFF

DETDTFF

10fJ/250MHz

20fJ/250MHz

30fJ/250MHz

40fJ/250MHz

50fJ/250MHz

Delay [ps]

Total Power [uW]

DET-CSE Power vs. Delay

Sheet1

SETFF'sfiletd Delay (50% act)0% act. (D=0) POWER0% act. (D=1) POWER33% act. PDP50% act. PDP100% act. PDP

003350100

Alternative CPFF2.03E-106.63E-057.80E-052.47E-143.03E-144.71E-14

SAbFF-Bora's FF1.69E-106.52E-057.22E-051.60E-141.85E-142.54E-14

CCFF double ended1.69E-104.54E-055.98E-051.77E-142.25E-143.67E-14

CCFF single ended2.69E-107.09E-056.43E-053.24E-144.07E-147.15E-14

CPFF2.02E-106.63E-057.78E-052.43E-142.99E-144.65E-14

HLFF1.88E-105.84E-051.98E-043.10E-143.48E-144.62E-14

DTFF-ICCD12.17E-104.30E-051.11E-042.36E-142.72E-143.83E-14

DTFF-ICCD21.85E-106.55E-051.48E-042.70E-143.10E-144.29E-14

Improved CCFF2.61E-104.58E-059.17E-052.65E-143.14E-144.62E-14

DTFF-Modified ICCD1.67E-106.42E-051.72E-042.43E-142.69E-143.43E-14

PowerPC3.00E-103.37E-054.22E-052.81E-143.72E-146.43E-14

SAFFsaff43.13E-103.23E-054.03E-052.04E-142.55E-144.02E-14

SDFF1.69E-107.40E-052.66E-043.49E-143.84E-144.79E-14

DTFF-SLFFslfflarge1.55E-104.28E-055.29E-051.30E-141.62E-142.58E-14

StrongArmjakaruka23.23E-103.66E-054.47E-052.24E-142.77E-144.30E-14

DETFF'std Delay (50% act)0% act. (D=0) POWER0% act. (D=1) POWER33% act. PDP50% act. PDP100% act. PDPPOWER 33% act.POWER 50% act.POWER 100% act.POWERINT 33%POWERINT 50%POWERINT 100%POWERDAT 0% (D=0)POWERDAT 0% (D=1)POWERDAT 33%POWERDAT 50%POWERDAT 100%POWERCLK 0% (D=0)POWERCLK 0% (D=1)POWERCLK 33%POWERCLK 50%POWERCLK 100%

TGLMdetff3clk2new3.22E-102.05E-052.05E-052.47E-143.61E-146.50E-14DETFF37.66E-051.12E-042.02E-045.60E-058.40E-051.66E-041.03E-091.20E-084.80E-067.19E-061.44E-052.03E-052.04E-051.05E-051.04E-052.04E-05

TGCPFFdetff4new13.74E-104.18E-054.46E-053.75E-144.81E-147.84E-14DETFF41.00E-041.28E-042.09E-048.29E-051.07E-041.75E-041.21E-071.50E-078.84E-061.33E-052.60E-058.03E-068.55E-068.36E-068.28E-068.16E-06

C2MOSdetff5new2.68E-106.09E-056.35E-053.47E-144.35E-147.00E-14DETFF51.29E-041.62E-042.61E-049.50E-051.25E-042.15E-045.53E-093.45E-095.40E-068.10E-061.62E-052.76E-052.87E-052.89E-052.90E-052.93E-05

TSPCdetffnew3.25E-104.74E-056.70E-053.64E-144.64E-147.19E-14DETFFdyn1.12E-041.43E-042.23E-048.74E-051.16E-041.92E-041.77E-092.21E-093.45E-065.18E-061.03E-051.95E-052.06E-052.08E-052.12E-052.10E-05

DETACPFF2.23E-107.18E-057.50E-052.96E-143.61E-145.57E-14DEACPFF1.33E-041.62E-042.49E-041.09E-041.36E-042.17E-044.92E-102.62E-093.76E-065.63E-061.13E-051.93E-052.02E-052.04E-052.06E-052.10E-05

DETCPFF2.17E-107.30E-057.62E-052.96E-143.54E-145.46E-14DECPFF1.34E-041.63E-042.50E-041.09E-041.36E-042.16E-045.60E-102.78E-094.03E-066.06E-061.21E-051.93E-052.02E-052.07E-052.10E-052.18E-05

DETDTFF2.36E-104.07E-051.30E-042.43E-143.16E-145.31E-14DETFF11.03E-041.34E-041.84E-049.01E-051.20E-041.67E-044.06E-106.73E-081.55E-062.33E-064.64E-061.11E-051.16E-051.17E-051.17E-051.17E-05

0% act. (D=0) POWER0% act. (D=1) POWERPOWER 33% act.POWER 50% act.POWER 100% act.

2.05E+012.05E+017.66E+011.12E+022.02E+02

1.00E+121.00E+061.00E+061.00E+151.00E+151.00E+151.00E+061.00E+061.00E+061.00E+061.00E+061.00E+061.00E+061.00E+061.00E+061.00E+061.00E+061.00E+061.00E+061.00E+061.00E+061.00E+066.09E+016.35E+011.29E+021.62E+022.61E+02

1.00E+121.00E+061.00E+061.00E+151.00E+151.00E+151.00E+061.00E+061.00E+061.00E+061.00E+061.00E+061.00E+061.00E+061.00E+061.00E+061.00E+061.00E+061.00E+061.00E+061.00E+061.00E+06






td Delay (50% act)0% act. (D=0) POWER0% act. (D=1) POWER33% act. PDP50% act. PDP100% act. PDPPOWER 33% act.POWER 50% act.POWER 100% act.POWERINT 33%POWERINT 50%POWERINT 100%POWERDAT 0% (D=0)POWERDAT 0% (D=1)POWERDAT 33%POWERDAT 50%POWERDAT 100%POWERCLK 0% (D=0)POWERCLK 0% (D=1)POWERCLK 33%POWERCLK 50%POWERCLK 100%PDP (gnd)PDP (vdd)3.22E+023.22E+023.22E+023.22E+023.22E+02

TGLM3.22E+022.05E+012.05E+012.47E+013.61E+016.50E+017.66E+011.12E+022.02E+025.60E+018.40E+011.66E+021.03E-031.20E-024.80E+007.19E+001.44E+012.03E+012.04E+011.05E+011.04E+012.04E+016.60E+006.59E+002.68E+022.68E+022.68E+022.68E+022.68E+02

C2MOS2.68E+026.09E+016.35E+013.47E+014.35E+017.00E+011.29E+021.62E+022.61E+029.50E+011.25E+022.15E+025.53E-033.45E-035.40E+008.10E+001.62E+012.76E+012.87E+012.89E+012.90E+012.93E+011.63E+011.70E+0110fJ/500MHz20fJ/500MHz30fJ/500MHz40fJ/500MHz50fJ/500MHz

3.74E+023.74E+023.74E+023.74E+023.74E+021.50E+021.00E-111.50E-101.00E-142.00E-143.00E-144.00E-145.00E-146.67E+011.33E+022.00E+022.67E+023.33E+02

TGFF3.74E+024.18E+014.46E+013.75E+014.81E+017.84E+011.00E+021.28E+022.09E+028.29E+011.07E+021.75E+021.21E-011.50E-018.84E+001.33E+012.60E+018.03E+008.55E+008.36E+008.28E+008.16E+001.56E+011.67E+013.25E+023.25E+023.25E+023.25E+023.25E+021.60E+021.00E-111.60E-101.00E-142.00E-143.00E-144.00E-145.00E-146.25E+011.25E+021.88E+022.50E+023.13E+02

TSPC3.25E+024.74E+016.70E+013.64E+014.64E+017.19E+011.12E+021.43E+022.23E+028.74E+011.16E+021.92E+021.77E-032.21E-033.45E+005.18E+001.03E+011.95E+012.06E+012.08E+012.12E+012.10E+011.54E+012.18E+011.70E+021.00E-111.70E-101.00E-142.00E-143.00E-144.00E-145.00E-145.88E+011.18E+021.76E+022.35E+022.94E+02

2.23E+022.23E+022.23E+022.23E+022.23E+021.80E+021.00E-111.80E-101.00E-142.00E-143.00E-144.00E-145.00E-145.56E+011.11E+021.67E+022.22E+022.78E+02

DETACPFF2.23E+027.18E+017.50E+012.96E+013.61E+015.57E+011.33E+021.62E+022.49E+021.09E+021.36E+022.17E+024.92E-042.62E-033.76E+005.63E+001.13E+011.93E+012.02E+012.04E+012.06E+012.10E+011.60E+011.67E+012.17E+022.17E+022.17E+022.17E+022.17E+021.90E+021.00E-111.90E-101.00E-142.00E-143.00E-144.00E-145.00E-145.26E+011.05E+021.58E+022.11E+022.63E+02

DETCPFF2.17E+027.30E+017.62E+012.96E+013.54E+015.46E+011.34E+021.63E+022.50E+021.09E+021.36E+022.16E+025.60E-042.78E-034.03E+006.06E+001.21E+011.93E+012.02E+012.07E+012.10E+012.18E+011.59E+011.65E+012.36E+022.36E+022.36E+022.36E+022.36E+022.00E+021.00E-112.00E-101.00E-142.00E-143.00E-144.00E-145.00E-145.00E+011.00E+021.50E+022.00E+022.50E+02

DETDTFF2.36E+024.07E+011.30E+022.43E+013.16E+015.31E+011.03E+021.34E+021.84E+029.01E+011.20E+021.67E+024.06E-046.73E-021.55E+002.33E+004.64E+001.11E+011.16E+011.17E+011.17E+011.17E+019.60E+003.06E+012.10E+021.00E-112.10E-101.00E-142.00E-143.00E-144.00E-145.00E-144.76E+019.52E+011.43E+021.90E+022.38E+02

2.20E+021.00E-112.20E-101.00E-142.00E-143.00E-144.00E-145.00E-144.55E+019.09E+011.36E+021.82E+022.27E+02

2.30E+021.00E-112.30E-101.00E-142.00E-143.00E-144.00E-145.00E-144.35E+018.70E+011.30E+021.74E+022.17E+02

2.40E+021.00E-112.40E-101.00E-142.00E-143.00E-144.00E-145.00E-144.17E+018.33E+011.25E+021.67E+022.08E+02

2.50E+021.00E-112.50E-101.00E-142.00E-143.00E-144.00E-145.00E-144.00E+018.00E+011.20E+021.60E+022.00E+02

6.60E+036.59E+032.60E+021.00E-112.60E-101.00E-142.00E-143.00E-144.00E-145.00E-143.85E+017.69E+011.15E+021.54E+021.92E+02


2.80E+021.00E-112.80E-101.00E-142.00E-143.00E-144.00E-145.00E-143.57E+017.14E+011.07E+021.43E+021.79E+02



3.10E+021.00E-113.10E-101.00E-142.00E-143.00E-144.00E-145.00E-143.23E+016.45E+019.68E+011.29E+021.61E+02




3.50E+021.00E-113.50E-101.00E-142.00E-143.00E-144.00E-145.00E-142.86E+015.71E+018.57E+011.14E+021.43E+02

3.60E+021.00E-113.60E-101.00E-142.00E-143.00E-144.00E-145.00E-142.78E+015.56E+018.33E+011.11E+021.39E+02

3.70E+021.00E-113.70E-101.00E-142.00E-143.00E-144.00E-145.00E-142.70E+015.41E+018.11E+011.08E+021.35E+02

3.80E+021.00E-113.80E-101.00E-142.00E-143.00E-144.00E-145.00E-142.63E+015.26E+017.89E+011.05E+021.32E+02

3.90E+021.00E-113.90E-101.00E-142.00E-143.00E-144.00E-145.00E-142.56E+015.13E+017.69E+011.03E+021.28E+02

4.00E+021.00E-114.00E-101.00E-142.00E-143.00E-144.00E-145.00E-142.50E+015.00E+017.50E+011.00E+021.25E+02

4.10E+021.00E-114.10E-101.00E-142.00E-143.00E-144.00E-145.00E-142.44E+014.88E+017.32E+019.76E+011.22E+02

4.20E+021.00E-114.20E-101.00E-142.00E-143.00E-144.00E-145.00E-142.38E+014.76E+017.14E+019.52E+011.19E+02

4.30E+021.00E-114.30E-101.00E-142.00E-143.00E-144.00E-145.00E-142.33E+014.65E+016.98E+019.30E+011.16E+02

4.40E+021.00E-114.40E-101.00E-142.00E-143.00E-144.00E-145.00E-142.27E+014.55E+016.82E+019.09E+011.14E+02

4.50E+021.00E-114.50E-101.00E-142.00E-143.00E-144.00E-145.00E-142.22E+014.44E+016.67E+018.89E+011.11E+02

4.60E+021.00E-114.60E-101.00E-142.00E-143.00E-144.00E-145.00E-142.17E+014.35E+016.52E+018.70E+011.09E+02

4.70E+021.00E-114.70E-101.00E-142.00E-143.00E-144.00E-145.00E-142.13E+014.26E+016.38E+018.51E+011.06E+02

4.80E+021.00E-114.80E-101.00E-142.00E-143.00E-144.00E-145.00E-142.08E+014.17E+016.25E+018.33E+011.04E+02

4.90E+021.00E-114.90E-101.00E-142.00E-143.00E-144.00E-145.00E-142.04E+014.08E+016.12E+018.16E+011.02E+02

5.00E+021.00E-115.00E-101.00E-142.00E-143.00E-144.00E-145.00E-142.00E+014.00E+016.00E+018.00E+011.00E+02

Sheet1

000

000

000

000

000

000

000

000

000

000

000

000

000

000

000

33% act. PDP

50% act. PDP

100% act. PDP

EDP [fJ/500MHz]

EDP vs. Activity rate

Sheet2

0

0

0

0

0

0

0

0

0

Latch-Mux

Pulsed Latch

Our designs

Delay [ps]

Dual-Edge Triggered Flip-Flops Delay

Sheet3

0

0

0

0

0

0

0

0

0

Latch-Mux

Pulsed Latch

Our designs

EDP [fJ/250MHz]

Dual-Edge Triggered Flip-Flops EDP (50% activity)

000

000

000

000

000

000

000

000

000

Latch-Mux

Pulsed Latch

Our designs

Internal

Clock

Data

Power [uW]

DET Flip-Flops Power Break-Up (50% activity)

00000

00000

00000

00000

00000

00000

00000

00000

00000

Latch-Mux

Pulsed Latch

Our designs

0% (gnd)

0% (vdd)

33%

50%

100%

Total Power [uW]

DET Flip-Flops Power vs. Activity

00000

00000

00000

00000

00000

00000

00000

00000

00000

Latch-Mux

Pulsed Latch

Our designs

0% (gnd)

0% (vdd)

33%

50%

100%

Total EDP [fJ/250MHz]

DET Flip-Flops EDP vs. Activity

000000000000

000000000000

000000000000

000000000000

000000000000

00000

00000

00000

00000

00000

00000

00000

00000

00000

00000

00000

00000

00000

00000

00000

00000

00000

00000

Our designs

50fJ/250MHz

40fJ/250MHz

30fJ/250MHz

20fJ/250MHz

10fJ/250MHz

TGLM

C2MOS

TGCPFF

TSPC

DETACPFF

DETCPFF

DETDTFF

10fJ/250MHz

20fJ/250MHz

30fJ/250MHz

40fJ/250MHz

50fJ/250MHz

Delay [ps]

Total Power [uW]

DET Flip-Flops Power vs. Delay

Symmetric Pulse Generator Flip-Flop (SPG-FF) Nedovic, Oklobdzija, Walker, ESSCIRC 2002


0.28

0.28

0.28

0.28

0.9

0.5

In

Op

C1

Mn3

Mn4

Mp3

Mp2

2nd STAGE

1st STAGE: X

1st STAGE: Y

Mn1

Mn2

CLK

D

CLK3

CLK

CLK1

D

CLK4

CLK1

X

Y

Inv1

Inv2

Inv3

Inv4

CLK

CLK1

CLK2

CLK3

CLK4

CL

Q

I1

Q

Mp1

Mn7

Mn8

Mp6

Mn5

Mn6

Mp4

Mp5

Mp8

Mp7

Mn9

Mn10

I2

I3

ConclusionClocking is the next challenge. Current clocking techniques may hold up to 10 GHz. Afterwards the pipeline boundaries start to vanish while more exotic clocking techniques will find their use. Synchronous design will be possible only in limited domains on the chip. A mix of Synchronous and Asynchronous design may emerge even in digital logic. Synchronous Design:Has not exhausted all the tricksAsynchronous Design:Has not solved all the problemsWe need solutions from both for a successful SoC Design


Figure presenting typical clock-to-output and data-to-output characteristics is shown.. In stable region, clock-to-output characteristic is constant. As setup requirement of the device starts to be violated, clock-to-output curve rises, ending in failure at some point. Data-to-output characteristic, being simple sum of clock-to-output and data-to-clock time, falls with the slope of 45 in stable region. In metastable region, the slope starts to decrease as a function of increased clock-to-output characteristic. Minimum of data-to-output curve occurs at 45 slope of clock-to-output curve. Data-to-clock time that corresponds to this point is termed optimal setup time.

issues in system on the chip clocking november 6th, 2003 soc design conference, seoul, korea

Documents

university of californiaref

university of californiamulti

soc design conference

asynchronous synchronousprof

ps of clock uncertainties

fo4clock uncertainty

clocking problemsfewer

chip clocking