lect10 clocking short

7/29/2019 Lect10 Clocking Short

1/21

ECE465 Lecture Notes # 11

Clocking Methodologies

Shantanu Dutt

UIC

Acknowledgement: (1) Most slides prepared by Huan Ren from Prof. Dutts Lecture

Notes (some modifications made by Prof. Dutt); (2) Some slides extracted fromProf. David Pans (UT Austin) slides as indicated


2/21

Me

mory

Timing Methodologies

Synchronous Sequential Circuits

Comb.

Logic

Clk

External I/P External O/P

Features Required for Correct

Operation 1) All State Transitions take place

only with respect to a particular

event in the clock (e.g., positive

or negative edge, etc. )

A

C11/0

B

11/0

00,11/0 01/1

00,01,10/0

01/0

10,00/1

Transition occurs only on

positive edge of Clk

TOPP,Logic

T

NS

P,Logic

(critical path delay

In the o/p logic part)

(critical path delay

In the NS logic part)


3/21

Timing Methodologies (contd)

Features Required for Correct Operation

2) Only one state transition should take place in one clock period. 3) All inputs to all FFs/latches should be correctly available with

appropriate setup time (Tsetup or Tsu) and hold time (Thold or Th)

around the triggering edge of the clock.

ith state

transition

(i+1)th state

transition

(i+2)th state

transition

(i+3)th state

transition

Tperiod=TClk

[could be to

the same state]

Tsetup Thold

Input

Clock


4/21

Clock Routing A path from the clock source to clock sinks (FFs)

Different FFs are at different distances from the clock source

Clock Source

FF FF FF FF FFFF FF FFFF FF

From: David Pan, UT Austin

This leads to the clock ariving at different FFs at slightly different time.

This difference in clock arrival times is called clock skew


5/21

Timing Methodologies: Clock Skew Problem

Real-world problems that can cause the three requirements to be violated

A) Clock Skew: Max(arrival time difference of the same clock edge betw allFF pairs).

01

D1 FF1

D Q Logic

FF2

D QIN

Q1

0 1D2 Q2

0

Clk Clk1 Clk2

00 10

Current

state

Correct

transition

11

Incorrect

transition

New value of D2

overwrites old valuebefore Q2 changes

This causes an incorrect

Q2 change when +ve

edge arrives at Clk2

Clk1

Clk2

D1

D2

Q1

Q2

Tskew

Safe: Ifblue horse wins race & wins it by a margin of at least Th2

1Unsafe: Ifbrown horse wins race

2

1

Values before

the clock +ve

edge


6/21

Safe Value of Tskew

Clk1

Clk2

D1

D2

Q1

TsuTh

Typical ormin TPLH

min TP,Logic

Tskew Th

01

D1 FF1D Q Logic

FF2D Q

IN

Q1

0

D2Q2

0

Clk Clk1 Clk2

Safe if: min (TPLH of FF)+min (TP,Logic

between Q1 & Q2)>Tskew+Th

i.e. if: Tskew


7/21

Determining Clock Period: EdgeTriggered System

Comb.Logic

FF1

FF2

Clk

Clk1

Clk2

Clk

Level sens.latch

Positive

edge trigg.

Clk

negative

edge trigg.

Memory of FF bankwith delay TP,FF

TOPP,Logic

Clk1

Clk2

TP,FFTsu

TP,Logic Tskew

TClk

TClk

-Tskew

> max(TP,FF

)+ max(TNSP,Logic

)+Tsetup

= TP,FF+ TNS

P,Logic+Tsetup

i.e., we will use the normal convention of using TP,FFto mean max(TP,FF) TNSP,Logicto mean max(T

NSP,Logic)

Also, TClk-Tskew > TP,FF+ TOP

P,Logic, where TOPP,Logic

is the output logic portion of combinational logic.

Max(typical TPHLand typical TPL

TNSP,Logic


8/21

Determining the Clock Period (Contd.)

If with skew TClk> Tskew+ TP,FF+ T

NSP,Logic +Tsetup AND

TClk> Tskew+ TP,FF+ TOP

P,Logic

Thus TClk> max(Tskew+ TP,FF+ TNS

P,Logic +Tsetup, Tskew+ TP,FF+ TOP

P,Logic)

Use 10% buffer for safety

TClk=1.1max(Tskew+ TP,FF+ TNSP,Logic +Tsetup, Tskew+ TP,FF+ TOPP,Logic)

Tskew= max (|difference between clock pulses (rising edges) of clock inputs

of any two FFs in the system|)

Clk1

TP,FF + TNS

P,Logic + Tsetup, AND

TP,FF+ TOPP,Logic

TClk


9/21

Clock Skew Clock skew is the maximum difference in the arrival time of a clock

signal at two different components.

Clock skew forces designers to use a large time period between

clock pulses. This makes the system slower.

So, in addition to other objectives, clock skew should be

minimized during clock routing.



10/21

Clock Design Problem What are the main concerns for clock design?

Skew No. 1 concern for clock networks For increased clock frequency, skew may

contribute over 10% of the system cycle time

Power

very important, as clock is a major powerconsumer! It switches at every clock cycle!

Noise Clock is often a very strong aggressor

May need shielding Delay

Not really important But slew rate is important (sharp transition)



11/21

The Clock Routing Problem

Given a source and n sinks (FFs).

Connect all sinks to the source by an

interconnect tree so as to minimize: Clock Skew = maxi,j |ti- tj|

Delay = maxiti

Total wirelength

Noise and coupling effect



12/21

H-Tree Clock Routing

4 Points 16 Points

Tapping Point



13/21

Method of Means and Medians (MMM)

Applicable when the clock terminals are arbitrarily

arranged.

Follows a strategy very similar to H-Tree.

Recursively partition the terminals into two sets of

equal size (median). Then, connect the center ofmass of the whole circuit to the centers of mass of

the two sub-circuits (mean).

Clock skew is only minimized heuristically. The

resulting tree may not have zero-skew.



14/21

An Example of MMM

centers of mass



15/21

Another Problem: Race ConditionReason 1

A race condition occurs when a FF/latch output changes more than

once in a clock cycle (cc). This happens when after the O/P of a latch changes, it feeds back to its

input via some logic when the latch is still enabled in the same cc. This

cause the O/P to change again.

Clk

D

Q

Tsu

2 changes of state in Q in 1 cc

Clk

D latch

Comb.

Logic

Other I/Ps

DQ


16/21

Race Condition: Reason 1 (contd) Race condition is generally a problem with level sensitive latches.

Can be solved using:

a) Edge-triggered FFs.Clk

D

Q

D FF

Comb.

Logic

Other I/Ps

Clk

DQ

b) Narrow-width clocking.

Only 1 O/P change per cc.

TClk

Tw

TClk> Tskew+ TP,FF+ TP,Logic+Tsetup

Tw


17/21

Correct State Transition Using Level-Sensitive

Latches

00

100/0

0/1

01

1/1

111/1

1/01/0

0/0

Comb.

Logic

0

1

0

1

0

1

Transition for the darkened arrow:

Clk

Comb.Logic

0

1

0

0

1

1

Clk

Comb.

Logic

0

0

1

0

1

1

Clk

0/1

2 level

sens.

latches

CS NS

R C diti R 2


18/21

Race Condition: Reason 2(Unequal logic delay for different NS bits)

Incorrect State Transition Using Level-Sensitive Latches

Required transition for the darkened

arrow becomes incorrect transition

corresponding to the dashed arrow

Comb.

Logic

0

1

0

1

0

1

Clk

Comb.

Logic

0

1

0

1

1

1

Clk

Comb.

Logic

0

1

1

1

1

1

Clk

Comb.

Logic

1

1

1

0

0

1

ClkComb.

Logic

1

0

0

0

0

1

Clk2 level-sens. latches

fast

slow

1/0

00

100/0

0/1

01

1/1

11

1/1

1/0

0/00/1


19/21

No Race Condition Using Edge-Triggered FFs

00

100/0

0/1

01

1/1

11

1/1

1/01/0

0/0

Correct transition for the darkened

arrow irrespective of the relative speed

of different excitation (next state) outputs

Comb.

Logic

0

1

0

1

0

1

Clk

Comb.

Logic

0

1

0

1

1

1

Clk

Comb.

Logic

0

1

0

1

1

1

Clk

0/1

Comb.

Logic

0

1

0

0

1

1

ClkComb.

Logic

0

0

1

0

1

1

Clk2 M-S or edge-triggered FFs

fast

slow

Period Between StateTransitions (also clock period)

N R C diti U i 2 h l ki d


20/21

Comb.

Logic

0

1

0 1

1

1

Clk2 Clk1

No Race Condition Using 2-phase clocking and

MS level sensitive latches

00

100/0

0/1

01

11

1/1

1/01/0

0/0

Generally, Cost(master-slave (MS) LS latches)< Cost(edge-trigg. FF)

Correct transition for the darkened arrowirrespective of the relative speed of differentexcitation (next state) outputs

Comb.

Logic

0

1

0 0

1

1

Clk2 Clk1

fast

slowComb.Logic

0

0

0 1

1

1

Clk2 Clk1

Comb.Logic

0

0

1 1

0

1

Clk2 Clk1Clk2

Clk1

fast

slow

T2-1TgapT1-2


21/21

Two-phase clock period determination

Clk2

Clk1 T2-1 Tgap1 T1-2

Tgap1>Tskew(to avoid overlap and thus a race condition)

T2-1+aT1-2(assuming 0 Tgap1, 0< a TP,FF+TP,Logic+Tsu(Note: Introducing a Tgap1 of at least Tskew also takes care of the

reqmt to allow for Tskewin the above sum of the 3 delay components)

T1-2 = T2-1 (for symmetry requirements)(1- a)T1-2 + Tgap2> TP,FF + Tsu+ TskewTgap1 = Tgap2 (for symmetry requirements)Tclk = 1.1(T2-1 + T1-2 + Tgap1 + Tgap2 ) =

1.1(2TP,FF+TP,Logic+2Tsu+2Tskew) [w/ 10% safety gap]

Comb.Logic

O/PsI/Ps

Clk2 Clk1TClk

CS NS

Tgap2

aT1-2

(1-a)T1-2

lect10 clocking short

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