05 timing clocking p6

8/6/2019 05 Timing Clocking p6

1/11

ECE152B TC 1

Issues on Timing and Clocking

Combinational

Logic

X Z

D

ECE152B TC 2

FF

FF

. . .

FF

clock

clock periodclock

Latch and Flip-Flop

D

Q

Q

L

D Q

QCK

ECE152B TC 3

CK

L1

D Q

QCK

L2

D Q

QCK

CK

D1Q1 Q2

Clocking

FF

Combinational

Logic

X Z

Q D

For correct operation of asynchronous circuit:

The clock period must belonger than the delay ofthe lon est ath in the

ECE152B TC 4

clock

clock period

FF

FF

. . .

FF

clock

combinational logic.

The width of the clockpulse must be long enoughto allow the flip-flops tochange state.

Flip-Flop Setup and Hold Times

50%Input

date50%

D Q

Flip-flop setup time Tsu: the required time the datainput signal value must be held stable prior to thearrival of clock pulse.

ECE152B TC 5

50%

Setup time Hold time

Inputclk

Q

Flip-flop hold time Th: the required time the datainput signal value must be held stable after thearrival of clock pulse.

Flip-flip Timing Parameters

D

Clk

Q

ECE152B TC 6

D

Q

Clk

tc-q

thold

tsu

Delays can be different for rising and falling data transitions


2/11

Example: For the circuit shown below, assume thedelay through the register (tpd) is 0.6 and the delaythrough each logic block is indicated inside the box.Assume that the registers, which are positive edge-triggered, have a set-up time T

suof 0.4. What is the

minimum clock period?

logic

ECE152B TC 7

Clock

tpd=

logictpd=2

logictpd=2

logictpd=3

logictpd=5

register register

t t

A Simple RC Model for Logic Gates

A BA B

equivalentcircuit

G

G

Rout

ECE152B TC 8

a buffer/gate input

Interconnect Models

driver

C1C2

C3

ECE152B TC 9

1. Ignoring interconnects

2. Lumped capacitance model

3. RC tree model

4. RLC tree model

5.

Transmission line models (RC, LC, RLC)6. RC / RLC Network model

Interconnect Models as a Capacitor

1. Ignoring Interconnects: 2. Lumped Capacitance model:

Rd

CoutputCinput C1+ C2+ C3

Vout Rd

CoutputCinput C1+ C2+ C3+ Cwir

Vout

ECE152B TC 10

1.0 x VDDVOUT

T 2T time

0.5 x VDD

Vout(t) = VDD (1 et/T) T = Rd (Coutput+ C1+ C2+ C3) orT = Rd (Coutput+ C1+ C2+ C3 + Cwire)

Vout-1(0.5VDD) = (ln 2) T = 0.693 TVout(T) = 0.632 VDD

Analysis of Simple RC Circuit

)())((

)(

)()()(

tdv

C

tCvd

ti

tvtvtiRT

==

=+ v(t)CR

vT(t)

i(t)

ECE152B TC 11

)()()(

tvtvdt

tdvRC

T=+ first-order linear

differential equationwith constantcoefficients

statevariable

Inputwaveform

Analysis of Simple RC Circuit

0)()(

=+ tvdt

tdvRCZero-input response:

(natural response)

Step-input response:

RCt

N Ke(t)vRCdt

dv(t)

v(t)

==

11

)()()(

0 tuvtv

dt

tdvRC =+

t

ECE152B TC 12

match initial state:

output response for step-input:v0 v0u(t)

v0(1-e-t/RC)u(t)

)()()()( 00 tuvKetvtuvtvRC

F +==

)()1()( 0 tuevtvRC

t=

0)(0)0( 0 =+= tuvKv

You can get the same result by Laplace Transform


3/11

Delays of Simple RC Circuit

v(t) = v0(1 - e-t/RC) -- waveform under step input v0u(t)v(t)=0.5v0 t = 0.7RC

i.e., delay = 0.7RC (50% delay)

v(t)=0.1v0 t = 0.1RC= =

ECE152B TC 13

. 0 .

i.e., rise time = 2.2RC

Rise time (Fall time): time for a waveform to rise from10% to 90%(90% to 10%) of its steady state valueVOL

VOH

Rise time

VOLVOH

Fall time

Interconnect Models as a Tree

3. RC tree model

4. RLC tree model

5. Transmission line models (RC, LC, RLC)

C2

ECE152B TC 14

driver C3

L-type -type T-type

ortransmissionline

Determining Which Model to Use

Some Rule-of-Thumbs:

Need to consider C: if interconnect C is comparable to C of gates

driven

ECE152B TC 15

Need to consider R: if interconnect R is comparable to R of

driver

Need to consider L: if L is comparable to R of interconnect

Model Interconnects as RC Trees

Each wire maybesegmented into severaledges

ECE152B TC 16

-type or L-type circuit

rE = unit res. length(E) cE = unit cap. length(E)

Interconnect Delay: Putting All Models Together

Rout

Rin

+

-

G1 G2

CLCinG1 G2

R= Rout+RintV

in

ECE152B TC 17

Vin Vout

C=Cin+CL

v0(1-e-t/RC) Vout

timeRise/fall time 2.2 RC => Delay is proportional to the loading capacitance CL

Driving more gates result in longer rise/fall time

Longer interconnects (larger Rint and Cin) also result in longer rise/fall time

Clock Tree

If the # of flip-flops driven by the clock line is large, theclock rise time (also called slew rate) will beunacceptably long.

Solution: Using clock power-up tree (adding buffers intothe clock tree)

CLK

ECE152B TC 18

FF FF

... ... ...

......


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Limiting the number of fanouts of each buffer to N

Create a buffer tree to drive all flip-flops while satisfying

the constraint of fanout count

The load seen by the clock source is significantly reduced

Solution: Adding Buffers and LimitingNumber of Their Fanouts

ECE152B TC 19

The same idea can be used to reduce the delay of logicsignals which drive a large number of gates and are ontiming-critical paths

An Example

Assume 64 flip-flips to be driven by a single clock source

Buffer delay (with zero load): 0.2 ns

Interconnect delay: 0.2 ns with a single fanout (either to a flip-flop or to a buffer)

Addition 0.1ns delay for each additional fanout

ECE152B TC 20

Total delay from clock source to clock ports of flip-flops: 6.9 ns

0.2ns + 0.2ns + (0.2ns + 63 x 0.1ns) = 6.9ns

FF FF... ... ...

Clk source

Example Clock Tree

Assume each buffer has four fanoutsClk Source

......

ECE152B TC 21

... ... ...FF FF

Total delay from clock source to clock ports of flip-flops: 2.3ns0.2ns {0th-level wire delay} + 0.2ns {1st-level buffer delay} +

(0.2ns + 3 x 0.1ns) {1th-level wire delay} + 0.2ns {2nd-level buffer delay} +

(0.2ns + 3 x 0.1ns) {2nd-level wire delay} + 0.2ns {3rd-level buffer delay} +

(0.2ns + 3 x 0.1ns) {3rd-level wire delay}

Techniques for Improving Speed

1. Keep the logic gate depth shallow between flip-flops.

2. Avoid circuit designs that have highly loaded gates inthe critical path.

A gate delay will increase as the capacitive load isincreased on the output of the gate.

ECE152B TC 22

e pr mary sources o oa capac ance are rou ngcapacitance and the input capacitance of the drivengates.

3. Duplicate logic to reduce fanouts (similar idea to clocktree buffering).

4. Avoid long interconnects

5. Gate sizing

Gate Sizing: Making The Driving GateLarger (or Smaller)

Rout

Rin

+

G1 G2

Larger the driving gate => Greater the driving current (sosharper Vin), but larger Cinput too (which slows down thesignal coming into G1)

BD

A B D

Vin

ECE152B TC 23

-

CLin

v0v0(1-e-t/RC)

timeA B

G1

CinputRout

TimingSpecs

REPORTS

Static Timing Analysis 101

ECE152B TC 24

(courtesy P. Joshi, IBM)


5/11

PO1

PO2

PO3

PI1

PI2

PI3

131

4644

665

574

Netlist with delay foreach gate

Static Timing Analysis

ECE152B TC 25

PO1

PO2

PO3

PI1

PI2

PI3

131

4644

665

574

Arrival times000

1

31

79

77

13

1514

182218

PO1

PO2

PO3

PI1

PI2

PI3

1

31

4

644

6

65

5

74

arrival time/required time

0/4

0/0

0/8

1/5

3/3

1/9

7/9

9/9

7/157/13

13/15

15/15

14/18

18/22

22/22

18/22

Static Timing Analysis

ECE152B TC 26

PO1

PO2

PO3

PI1

PI2

PI3

131

4644

665

574

slack = required time -

arrival time

408

4

08

20

86

2

04

404

Timing Analysis with Interconnect Delay

5 5 5LA

LA

3 2 1 12222

11

ECE152B TC 27

4 4 4

CH

CH

2 1 3 2

Clock Non-idealities

Clock skew

Spatial variation in temporally equivalent clockedges; deterministic + random, tSK

Clock itter

ECE152B TC 28

Temporal variations in consecutive edges of theclock signal; modulation + random noise

Cycle-to-cycle (short-term) tJS Long term tJL

Variation of the pulse width

Important for level sensitive clocking

Clock Skew

The delays from the clock source to the clock inputsof different flip-flops are different

ACLOCK

DRIVER

ECE152B TC 29

B

Clock Skew and Jitter

Clk

Clk

tSK

tJS

ECE152B TC 30

Both skew and jitter affect the effective cycle time

Only skew affects the race margin


6/11

Clock Uncertainties Sources of Skewand Jitter

2

4

3

Power Supply

Interconnect

5 Temperature

6 Capacitive Load

7 Coupling to Adjacent Lines

Devices

ECE152B TC 31

1 Clock Generation

Sources of clock uncertainty

The clock skew problem: the race problem

FF1 FF2

0ns2ns

1ns

D1 D2Q1 Q2

ECE152B TC 32

Correct operation: D1 -> Q1 , D2 -> Q2Due to clock skew: D1 -> Q2 (error!!)

Minimizing clock skew:

Distribute the clock signal in such a way that the

interconnections from the clock source to the FFs

clock inputs are of equal length.

ECE152B TC 33 ECE152B TC 34

Positive and Negative Skew

R1In Combinational

LogicD Q

tCLK1CLK

delay

tCLK2

R2

D QCombinational

Logic

tCLK3

R3

D Q

delay

ECE152B TC 35

(a) Positive skew

R1In

(b) Negative skew

CombinationalLogic

D Q

tCLK1

delay

tCLK2

R2

D QCombinational

Logic

tCLK3

R3

D Q

delay CLK

Positive Skew

R1In

a Positive skew

CombinationalLogic

D Q

tCLK1CLK

delay

tCLK2

R2

D QCombinational

Logic

tCLK3

R3

D Q

delay

ECE152B TC 36

Launching edge arrives before the receiving edge

R1In

(b) Negative skew

CombinationalLogic

D Q

tCLK1

delay

tCLK2

R2

D QCombinational

Logic

tCLK3

R3

D Q

delay CLK

CLK1

CLK2

TCLK

TCLK+

+ th

2

1

4

3


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Clock Period: T

Longest delay from Reg. A to Reg. B: LD AB

Shortest delay from Reg. A to Reg. B: SD AB FF propagation delay, setup time, hold time: tcq, tsu, thold

1. T + (tcq + LDAB + tsu)

Summary

ECE152B TC 43

2. (tcq + SDAB - thold)

Where=(t -t)

Requirement (1) have to be satisfied for datapath between any pairof registers where would be either positive or negative

Requirement (2) have to be satisfied for datapath between any pairof registers with a positive clock skew

logictpd=5

logic

tpd=2

logic

tpd=2

logictpd=3

logictpd=5

register register

t t

Example: Assume tcq is 0.6, tsu is 0.4 and thold is0.5.

ECE152B TC 44

Clock

(a) Determine the minimum clock period assuming a positive clock skew: = (t -t) = 1.(b) Repeat part(a), factoring in a positive clock skew: = 3.(c) Repeat part(a), factoring in a negative clock skew: = -2.(d) Derive the maximum positive clock skew (i.e. t > t) that can be tolerated before the

circuit fails.

(e) Derive the maximum negative clock skew (i.e. t < t) that can be tolerated before thecircuit fails.

Impact of Jitter

CLK

-tjitter

TC LK

tjitter1

2

3 4

5

6

ECE152B TC 45

CLK

InCombinational

Logic

tc-q

, t c-q, cd

tlogic

tlogic, cd

tsu,

thold

REGS

tjitter

Be Very Careful About Gated Clock

ControllerFF

D QA

clk B

ECE152B TC 46

An undesirable glitch or

spike will result & cause an

additional trigger of the clock.

clk

A

B

An alternative design:

Controller

FFD

Q

0

1

Controller

FF

DQ

A

B

ECE152B TC 47

This design causes less timing problem but consumemore power.

clk clk

Clock Gating

Typically 40-50% of active power isin the IC clock trees

Clock gating allows some of this

power eliminated in active modes

ECE152B TC 48

Root and branch clock gating can besignificant

Resumption of clocking is very fast

So clock-gated modules can returnto run mode without loss ofservices


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05 timing clocking p6

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