JESD204B/C Clocking TI Precision Labs – Clocks and Timing

Presented by Timothy Toroni

Prepared by Timothy Toroni and Liam Keese

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Traditional clocking vs. JESD204B clocking

JESD204B clocking and data interface Traditional clocking with

parallel data interface

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FrameClock

Transport

Layer

Data

LayerADC

: : :LMFC Frame

Clock

Transport

Layer

Data

Layer

Application

Layer

:::LMFC

Device Clock A Device Clock B

JESD204B/C

Clocking

Device

SYSREF A SYSREF B

ADC (Tx) FPGA/ASIC (Rx)

SYNC~

SampleClock

LogicClock

ADC

Sample Clock

Logic Clock

Traditional

Clocking

Device

ADC (Tx) FPGA/ASIC (Rx)

Application

Layer

What is JESD204?

• JESD204 is a definition for data converters to allow synchronization of

data between data converters and logic devices.

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Function JESD204 JESD204A JESD204B JESD204C

JEDEC specification release 2006 2008 2011 2017

Maximum lane rate (Gbps) 3.125 3.125 12.5 32

Support for multiple lanes? No Yes Yes Yes

Support for lane synchronization? No Yes Yes Yes

Support for multi-device synchronization? No Yes Yes Yes

Support for deterministic latency? No No Yes Yes

Support for harmonic clocking? No No Yes Yes

JESD204B subclasses

• Subclass 0 – No support for deterministic latency (backward compatible with JESD204A)

• Subclass 2 – Deterministic latency achieved using “~SYNC‟ as timing signal

• Subclass 1 – Deterministic latency achieved using an external “SYSREF” as timing signal

.

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DeviceClock

SYSREF

Types of SYSREF signals

• Continuous SYSREF

• One-shot SYSREF

– Single (or multiple) pulses

only when requested

– Reduces radiated spurious

noise

• Gapped Periodic SYSREF

– Reduces radiated spurious

noise

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Device Clock

SYSREF One-Shot

SYSREF Continuous

SYSREF Gapped-Periodic

LMFC

LMFC

LMFC

Benefits of JESD204B – Reduced PCB complexity

ADC

DAC

Many low speed parallel lanes with length matching

Clocking Device

ADC

DAC

Logic

Device

(ASIC/

FPGA)

Logic

Device

(ASIC/

FPGA)

Clocking Device

Single or few serialized high speed lanes without the need for length matching

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JESD204B clocking and data interface

Traditional clocking with parallel data interface

Example of non-JESD204B vs. JESD204B layout

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Non-JESD204B DAC (LVDS) JESD204B DAC (JESD204B)

DAC

DAC

32 lanes, 750 MSPS 8 lanes, 1250 MSPS

Lots of length

matched traces

Fewer direct

routed traces

Benefits of JESD204B – Reduced clock frequencies

ADC

DAC

Different clock frequencies for each device

Clocking Device

ADC

DAC

Logic

Device

(ASIC/

FPGA)

Logic

Device

(ASIC/

FPGA)

Clocking Device

1 GHz

2 GHz 250 MHz

2 GHz

2 GHz

SYSREF

SYSREF

/2

/1

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JESD204B clocking and data interface

Traditional clocking with parallel data interface

Single clock frequency for each device

Single clock frequency for each device, with exception

SYSREF 2 GHz 250 MHz

/1 /8

JESD204B subclass 1: determinism with SYSREF

• Deterministic timing/data

transfer achieved by

repeatable “marking” of

device clocks across

system elements.

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1000 MHz

Device Clock

3000 MHz

VCO

SYSREF

(Based on

10 MHz Clock)

1000 MHz

Device Clock

3000 MHz

VCO

SYSREF

SYSREF valid

windowMinimum setup time

Maximum setup timeSetup time

Minimum hold time

JESD204B

Clocking

Device

Device

Clock

SYSREF

Converter

Logic Device

SYSREF

Device

Clock

Data

What if timing is missed?

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Holdx ps

Setupy ps

Setupy ps

± 0 cycles +1 cycle-1 cycle-2 cycles

Holdx ps

Setupy ps

SYSREF valid

window for +/- 0 error1 device

clock edge

Holdx ps

Device Clock Period

SYSREF valid window for +/- 13 device clock edges

Device clock and SYSREF timing adjustment

• Device clock

– Adjusted to minimize skew between

device clocks

• SYSREF

– Adjusted to optimize timing to

SYSREF valid window.

• Delay adjustment types:

– Digital delay

– Analog delay

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Device Clock

SYSREF Clock

SYSREF adjustment

Device clock

adjustmentSYSREF valid window

SYSREF example 1: SYSREF valid window greater than three times delay step

• 3000 MHz VCO frequency

• 1500 MHz device clock,

666.7 ps period

• 50 ps setup/hold time

• Valid window = 566.7 ps

Device Clock Period

666.7 ps

SYSREF valid window

566.7 ps

1500 MHz

Device Clock

SYSREF 166.7 ps 166.7 ps 166.7 ps 166.7 ps

1 2 3

Delay Step Size

Valid window = device clock period – setup time – hold time

𝑀𝑎𝑟𝑔𝑖𝑛 = 𝑚𝑖𝑛(𝐷𝑒𝑙𝑎𝑦 𝑆𝑡𝑒𝑝 𝑆𝑖𝑧𝑒); 𝑖𝑓 3 ∗ max 𝐷𝑒𝑙𝑎𝑦 𝑆𝑡𝑒𝑝 𝑆𝑖𝑧𝑒 < 𝑆𝑌𝑆𝑅𝐸𝐹 𝑣𝑎𝑙𝑖𝑑 𝑤𝑖𝑛𝑑𝑜𝑤

Equations:

Min and max delay step size is to account for possible non-uniform step sizes.

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Hold

Time

50 ps

Setup

Time

50 ps

200 ps

SYSREF example 2: SYSREF valid window less than three times delay step

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Device Clock Period

400 ps

Hold

Time

50 ps

Setup

Time

50 ps

SYSREF valid window

300 ps

200 ps

2500 MHz

Device Clock

SYSREF

Equations:

𝑀𝑎𝑟𝑔𝑖𝑛 =𝑉𝑎𝑙𝑖𝑑 𝑊𝑖𝑛𝑑𝑜𝑤 − 𝑚𝑎𝑥(𝐷𝑒𝑙𝑎𝑦 𝑆𝑡𝑒𝑝 𝑆𝑖𝑧𝑒)

2

200 ps

1 2

Delay Step Size

• 2500 MHz VCO

• 2500 MHz device clock,

400 ps period

• 50 ps setup/hold time

• Valid window = 300 ps

Valid window = device clock period – setup time – hold time

Min and max delay step size is to account for possible non-uniform step sizes.

Interface between clock and target

50 Ω trace

50 Ω trace

Rs

Rs

Rb

LVPECL Clock

Input

Rb

RL

Re

LVPECL Clock

Input

Re

RL

50 Ω trace

C

C

50 Ω trace

LVDS Clock

InputRL

50 Ω trace

50 Ω trace

AC Coupled Clock DC Coupled Clock

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