clocking in digital systems

8/2/2019 Clocking in Digital Systems

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Clocking in digital systems

By

Bhanu prasad nimmagaddaRoll no 3


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All sequential circuits have one property in commona well-defined ordering of theswitching events must be imposed if the circuit is to operate correctly. If this were not thecase, wrong data might be written into the memory elements, resulting in a functional fail-ure. The synchronous system ap proach, in which all memory elements in the system aresimultaneously updated using a globally distributed periodic synchronization signal (thatsignals and their distribution to the memory elements distributed over the chip; non-com-

pliance often leads to malfunction.

At the other end of the design spectrum is an approach calledasynchronous design which avoids the problem of clock uncertainty all-together by eliminating the need for globally-distributed clocks. Afterdiscussing the basics of asynchronous design approach


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Synchronous Interconnect

CombinationalLogic

R1 R2Cin Cout Out

In

CLK


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Mesochronous interconnect


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Plesiochronous Interconnect


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Asynchronous Interconnect


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Latch parametes

D

Clk

Q

Qtc-q

thold

PWmtsu

td-q

T


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Clock skew

The spatial variation in arrival time of aclock transition on an integrated circuit iscommonly referred to as clock skew


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Positive and Negative Skew

R1In

(a) Positive skew

CombinationalLogic

D Q

tCLK1CLK

delay

tCLK2

R2

D QCombinational

Logic

tCLK3

R3

D Q

delay

R1In

(b) Negative skew

CombinationalLogic

D Q

tCLK1

delay

tCLK2

R2

D QCombinational

Logic

tCLK3

R3

D Q

delay CLK


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Positive Skew

CLK1

CLK2

TCLK

d

TCLK+ d

+ th

2

1

4

3

Launching edge arrives before the receiving edge


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Negative Skew

CLK1

CLK2

TCLK

d

TCLK+ d

2

1

4

3

Receiving edge arrives before the launching edge


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Clock Jitter

Clock jitterrefers to the temporal variation of the clock period at agiven point that is the clock period can reduce or expand on acycle-by-cycle basis. It is strictly a temporal uncertainty measureand is often specified at a given point on the chip.

CLK

-tjitte r

TC LK

tj itter

CLK

InCombinational

Logic

tc-q, tc-q, cdt log ict log ic, cd

tsu,thold

REGS

tjit te r


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Impact of Skew and Jitter on

Performance


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Sources of Skew and Jitter

2

4

3

Power Supply

Interconnect

5 Temperature

6 Capacitive Load

7 Coupling to Adjacent Lines

1 Clock Generation

Devices


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Clock-Distribution Technique

CLK

Clock is distributed in a tree-like fashion


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The Grid System

Driver

Driver

Dr

iver

Driver

GCLK GCLK

GCLK

GCLK

No re-matchingLarge power


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A Simple Synchronizer

CLK

int

I2

I1

D Q

CLK

Data sampled on rising edge of the clockLatch will eventually resolve the signal value,but ... this might take infinite time!


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Arbiters

Req1

Req2

Req1

Req2

Ack1

Ack2Arbiter

Ack1

Ack2

(a) Schematic symbol

(b) Implementation

A

B

Req1

Req2

A

B

Ack1t

(c) Timing diagramVTgap

metastable


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PLL Block Diagram

Phasedetector

Chargepump

Divide byN

Loopfilter

VCO

Referenceclock

Localclock

SystemClock

Up

Down

vcont


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Mesochronous pipelining scheme


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clocking in digital systems

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