12/4/2002 clocking – lecture 2 and 3 purpose – clocking design topics read chapter 12

12/4/2002

Clocking – Lecture 2 and 3

Purpose – Clocking Design TopicsRead Chapter 12

12/4/2002Introduction

2

Optional Additional Reading

http://www.uoguelph.ca/~antoon/gadgets/pll/pll.html © by Tony van Roon

http://www.cwc.nus.edu.sg/news/seminar/arch/PLL_seminar.pdf


3

Agenda

Clock Signal Requirements Intro to Phase Lock Loop – Baby

StepsClock Circuit Examples


4

In a system design, clocks may be generated by external chips

The idea assumption is that the clock edge are synchronized at each device

A digital clock signal is ideally a 50% duty cycle square wave

A “clock domain” is comprised of the a set of signals that are referenced to the same idea clock signal.

CPUs RAM Memory & I/O control

clock


5

Clock Signal Requirements Monotonic edges

Avoid double clocking and meta-stable behavior. Controlled with distribution topology

Fast edges Reduce uncertainty from slew rate Controlled by length

Low SkewControlled by topology, loading, and receiver sensitivity.

Low JitterMostly a clock generation issue.

High fan-out - TopologyIncludes cpu’s, i/o chips, expansion connectors, memory chips, control chips


6

Non-monotonic series terminated effects

Threshold limits

Wave is reflected at the load and turns around here

Wave is re-reflected at the source due to imperfect termination and transmitted back to load.

This “bump” move up and down depending on relation to Zl, Zs, rterm, and Zo.So we can see how more than just time delay effects the clock skew


7

Fast Edge Reduce Skew – but…

Fast edges can reduce the time uncertainty through the thresholds

However stub and packages can make fast edges more susceptible to ringing which can cause double clocking of the data


8

Issues with single ended threshold sensitivity

The wave is referenced to either Vcc or Vss. Consequently the effective DC value of the wave will be tied to one of these rails.

The wave is attenuated around the effective DC component of the waveform, but the reference does not change accordingly. Hence the clock trigger point between various clock load points is very sensitive to distortion and attenuation.

Vss

Vss

Vss

Rx1

Rx2

Tx

Vref

Vref

Vref


9

Differential Clocking vs Single Ended Clocking

Greater detail will be covered in in the next course. For a Single ended (SE) clock, the buffer drives

the clock signal on one trace. For a Differential (Diff) clock, the buffer drives

two traces in equal but in opposite directions. The signal are received at the load end with a differential amplifier. This means that the qualifying “clock” waveform is the difference of the signals on the two traces.

Single ended signaling requires a threshold reference voltage.

This voltage is generated either on or off of the die.The problem with single ended clocking is that is sensitive to more to attenuation and edge distortion.

Differential signaling reference threshold is normally at 0 volts. We will explore differential clocking later.


10

Low Skew

Clock path arrival mis-match

Clock buffer Tco pin to pin skew

Receiver loading

Skew Factors

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Data Bus

Clock Buffer

PhaseLockedLoop

Clock

Tree


11

Review of Clock Skew

Clock Skew: pin-to-pin variation in the timing of input clock at each agent (source & destination, in our example) on a bus.

The net effect of clock skew is that it can reduce the total delay that signals are allowed to have for a given frequency target.require larger minimum signal delays in order to avoid logic errors. (We’ll cover this in more detail shortly.)

Transmit clock at device a

Receive clock at device b


12

Clock path arrival mismatch considerations (Skew)

Clock distribution design decisions include:

Choice of TopologyEnumeration is in following slides

Routed trace length rules If all bus devices are identical,

matching is just making equal length routes from the clock buffer.

This is usually not the case


13Serpentine Routing is used to adjust for lengths

Space between serpentine traces should be minimum of 3x the dielectric height for stripline and 5x the dielectric height for microstrip.

We can estimate the effect using the coupling coefficient from a 2 D field solvers.

Buffer

L1

L2

L1=L2


14

Changing layers in a clock treeMaintain the same length on the

same layer similar segments.Dielectric constant and impedance

can vary up to 10% between layers.Changing layers is subject to return

path effectsChanging layers is normally not

desirable but may be unavoidable.Simulation of parametric variation is use to determine skew impact.


15Jitter

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Data Bus

Clock Buffer

PhaseLockedLoop

Reference oscillator PLL jitter – many typesBuffer jitter

Mostly caused power disturbance and SSO

On Chip clock distribution

Normally part of timing specHowever, subject to cascaded loop jitter.


16

Clock Source

The traceable reference for most clocks sources is a crystal oscillator.

A phase locked loop (PLL) regenerates clocks for distribution.

The primary purpose of a phase lock loop is to synchronize signal edges.PLLs may be the main clock domain sourcePLLs may be used within each chip to synchronizes internal nodes and external clock references.

PLLs are feedback amplifiers and subject to stability criteria. This especially true when PLLs cascaded.


17

Clock in

00

0

VCO

Distribution Route“Same electrical

length as feedbackclock”

Feedback ClockRoute

Phase detector

Phase Locked Loop – Simple Circuit

When this point is 0 V the distribution clocks are in phase with the “clock in”


18

Review Clock Jitter

Cycle to cycle variation of clock Reduces the time it take for data to get from

transmitter to receiver Jitter + Skew is clock budget for setup Skew is clock budget for hold

Hold uses same cycle of clock In many cases we can ignore certain types of jitter

There are other types of jitter – more advanced topic

Idea clock

Bar graph of each cycle time

Clock with Cycle to Cycle Jitter

Pulse Width(Ideal) Pulse Width

(Actual)


19

PLL Refer to the racing game

analogy in the text The angle of travel is

analogous to frequency control.

The transfer function is tracking gain vs. frequency of phase error.

Low frequencies are tracked well i.e. the gain is 1.

High frequencies are filtered. PLL’s are cascaded the

response is product. Results response > 1 can cause loop stability issues.

Freq.

Tracking Gain

4

3

2

1

Well Damped

Severe Resonance

TrackingRange

FilterRange


20

Other Types of Synchronizers

Delay Locked Loop (DLL) – Adjust to sub-clock phases. Synchronizing to quadrate is an example.

Phase Interpolator The difference function only increments a count. The phase stabilizes to the median of edge crossings.Adjustment is not proportional to amount of phase errorIs use to pull a clock out of data signals

Input

90 degree phase shift


21

Phase Interpolator is a Voting Circuit

Refclock

Interpolator

Counter

DLL (edge position)

Data Bit

Countup

Countdown

Lead/Lag Detect

Q

QSET

CLR

D

Clock out


22

Jitter Response measurement

In all but simplest of cases jitter measurement can be difficult.

Power ripple can introduce jitter

This suggest that PLL power should be filtered

Some data generations can introduce edge to edge jitter.

PLLAC

Power Rail


23

Clock Topologies – 2nd half of lecture

We will go over additions to what is in the text

We will go over the clock simulation project.

You will need sweep parameters and may need use Monte Carlo analysis that was presented last semester.

This is similar to an actual signal integrity design task.


24

Source Series Termination

Q

QSET

CLR

DRterm

L2aL1a

Q

QSET

CLR

DRterm

L2bL1b

Q

QSET

CLR

DRterm

L2a

Q

QSET

CLR

DRterm

L2b

Little or no re-reflection at source.

No additional components required at loads.

Loads may be 1000+ pin BGAs with limited component placement roomEasier to get termination close to source.Clock buffers are relatively small compared to computer and chip set chipsCan support multiple loads on one line with some restrictions

Low DC power. Low impedance buffers can

be used. L1a and L1b need to be

short lengths


25

Ganged Source Termination

Q

QSET

CLR

DRterm

Rterm

Rterm

Rterm

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Buffer Chip

Layout Example

Via

L1a

L1b

L1c

L1d

L2aL2b

L2c

L2d

L3a

L3b

L3c

L3d

L1a,b,c,d and L2a,b,c,d and L3a,b,c,d are matched. L1’s and L2’s are short.

Many drivers have issues ganging outputs. Buffer delays between legs is eliminated. As the number of ganging goes up the via node

tends toward 0 ohms


26

Double (multiple) loaded lines

Q

QSET

CLR

DRterm

Q

QSET

CLR

D

L1 L2

L3

Q

QSET

CLR

D

Rterm

Q

QSET

CLR

D

L1 L2L3

L3

Electrically this appears unattractive at first glance

May be required if clock buffers are scarce.

Simulation can determine if the edges are monotonic and if skew is acceptable.

In general: This is OK for clock with slow edges

There is a design task to determine L3.L3 is usually short.


27

Case Study and Project – testckt_clk.sp

•Buffer: 100 MHz, Rn=10 ohm, Rp=70 ohm, Tr=700ps

•Rterm=40 ohm, all inductors 1nH, All caps=1pf,•Ln1=.5”, Ln2=10”, Ln3=9”, Ln5=LN4=1”•Transmission line: r=4.1 Z0=68ohms•Receiver threshold = 1.5V +/- 0.1V

Q

QSET

CLR

DRtermLn1 Ln2

RtermLn1 Ln3Ln4

Ln5

L3

L1 L2

Q

QSET

CLR

DL4

C2

C4

Q

QSET

CLR

DL5

C5

C1

C3


28

Main program

Use level 1 behavioral model for MYBUF Create new board, package, and receiver

subcircuits


29

Level 1 Behavioral Model

Pass capacitor load in as parameter10 ohms up and 70 ohms down (Rp and Rn)Slew is controlled by input pulse


30

Packages are just series inductors

Receiver package has the inductance value passed in.

No coupling in buffer package and the inductance is set to 1 nH


31

The topology is captured in the brd subcircuit

The length and terminators are not parameterized here.

For our project you will need to parameterize them.


32

Transmission line model

We will parameterize L0 and C0 in terms of Z0 and r.

This means we can change Z0 and r and get a realistic transmission line. Notice the equations above in the first line.

This is quick way to parameterize a lossy transmission line. For 100MHz, the loss parameter are less significant that for 1GHz+. It will suffice for our example


33

Simple receiver model

In our test case, rload is 10K and cload is 1 pF


34

Results

Blue is the single line Red is the end of the forked line

Potential for glitch on negative edge

Potential oxide wear out problem


35

Effect of impedance sweep from 40 to 90

Skew measurements are done for the steady state solution for clocks

i.e. take measurements on the 3rd edge.MEAS TRAN skew1 TRIG V(clk1_pad) VAL=vil +RISE=3 TD=0ns TARG V(clk2a_pad) VAL=vih RISE=3 TD=0ns


36

Example of dependencies

skew

0

200

400

600

800

1000

1200

1400

1600

1800

0 20 40 60 80 100

impedance

ps skew

When the impedance Z0 is below 50 ohms the skew increases rapidly

This is only one case of other simulation parameters Your project need to evaluate all cases


37

Clock Design Project

You are to define board design parameters target Z0, Ln1, Ln3, Ln4, Ln5

Each segment can have a separate Z0 but may not be necessary and is will add cost to the design.

The skew goal is 900 ps (not +/-) The undershoot safe limit is -600 mV

You can exceed -600 mV to -1V but only for 1 ns It may not be possible to meet all requirements.

If so, determine the best design and the weak corners. Hand in 10-15 minutes of Power Point proving

your design Use HSPICE with a combination of Monte Carlo

and sweeping to acquire supporting data. You will need to further parameterize

testckt_clk.sp


38

Transmission Lines All lines are on the same layer They can be different impedances but if

one varies by 10 %, they all will see the same variation.

L2 is given to be exactly 10 inches L1 at least 1 inch Er is constant at 4.1 You need to choose the impedance target

for each of the segments The chosen target impedance will vary +/-

10% across all products Use Model on slide 27

“Case Study and Project – testckt_clk.sp”


39

Buffer Clock frequency is 100 MHz Rise fall time varies between 4Volts/ns and 0.75

V/ns when driving a 1K ohms load to ground and measured between 1.3 and 1.7 volts.

You will have to adjust pulse “tr” time to compensate. Both buffers Rn and Rp move together. Rn and Rp vary by 20% and move together. Rp target is 10 ohms Rn target is 70 ohms Vcc target is 3.3 volts +/- 10 %

You may determine this regulation may need to improve. If so, you will need to report the acceptable percentage.

The capacitance buffer load (bload) is 1pF


40

Packages

Inductance of buffer ranges between 1nH and 2nH.

Inductance of load (receiver) packages ranges between 1nH and 2nH and vary independently.


41

Load (Receiver)

Receiver threshold is between 1.4 and 1.6 volts.

Capacitance load of single load circuit is between 1pF and 2pF.

Capacitance loads of dual load circuit (fork) is between 1pF and 3pF and varies independently.

DC load of all receivers is 10K to ground.


42

Suggestion on how to start

List all parametersList rangesDetermine sensitivity

12/4/2002 clocking – lecture 2 and 3 purpose – clocking design topics read chapter 12

Documents

clock skew slide

clock edge

clock domain

idea clock signal

digital clock signal

differential diff clock

single ended se clock

qualifying clock waveform