memory innovation made possible by...
TRANSCRIPT
External Use
Memory Innovation Made Possible by Suppliers Er-Xuan Ping Managing Director, Applied Materials
September 9, 2016
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Current e-NVM Status and Challenges
STT-MRAM, ReRAM, PCRAM as New e-NVM
Applied Materials New e-NVM Development Out
line
Conclusions
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Current e-NVM Status and Challenges
STT-MRAM, ReRAM, PCRAM as New e-NVM
Applied Materials New e-NVM Development Out
line
Conclusions
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e-NVM in Microcontroller (MCU)
Access Speed Endurance
Retention (non- volatility) Density
Infineon TC1784, 90nm (180 MHz, 2.5 MByte Flash)
CPU/ Register Cache - SRAM
Memory – SRAM
Code Storage - eFlash (NOR)
Volatile & Non Volatile Memory on the Same Chip
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Markets and Applications
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Technology Status CMOS vs. e-Flash
Flash Summit 2013, Spansion
Do Dormans et al, NVSMW 2003
Flash Summit 2013, Spansion
4 Year/Gen
Renesas Announced 28nm Technology (with MONOS cell)
Source: Yole, 2015
14nm
SST, 32th European SSDVC 2002
3rd Generation Super Flash
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MCU Scaling Issues
Cost
Performance Power Consumption
Reliability High Temp Retention
F2
A. Kotov, Leti Innovation Days – Memory Workshop 2013
R. Strenz, IEDM 2011
Y. Thachev, and A. Kotov, Proc. ESSDERC, 2006
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Current e-NVM Status and Challenges
STT-MRAM, ReRAM, PCRAM as New e-NVM
Applied Materials New e-NVM Development Out
line
Conclusions
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New NVM Entrants
PCRAM – NOR NVM ReRAM – e-NVM
High Density Fast NVM
Toshiba/SanDisk, ISSCC 2013
Micron/Sony, ISSCC 2014
STT-MRAM DDR
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New Memory Attributes
Faster Than Flash Source: Kosuke Suzuki, Steven Swanson, University of California, San Diego technical report CS2015-1011, May 2015.
NVM Read Latency NVM Write Latency
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Cost Advantage of New e-NVM in MCU
Source Drain Gate
SRAM, Logic FETs NOR Flash
Source Drain
Current MCU Chip
STT-MRAM MCU Chip
10+ Mask Adder
3 Mask Adders
FEOL
BEOL
FEOL
Memory (STT MRAM)
Logic FET
Source: Macronix, Applied Physics A, 2011
One Mask
IBM, ECS Trans. 2015
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PCRAM Integration
As PCRAM cell pitch reduces and architecture changes to 3D XPoint, HAR processes needed.
CMOS
H.Horii et al, Symp on VLSI Tech 2003
Process Flow Pa
ssiv
atio
n Oxide Polish
Oxide Fill
PECVD/PEALD Liner
Treatment
Patte
rnin
g
Inspection
Post Etch Clean
Cell Material Etch
HM Open
Lithography
High Selective HM Dep
Cel
l Sta
ck Top Electrode Dep
Phase Change Material Dep
Polish
Bottom Electrode
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ReRAM Integration
Current ReRAM faces variability, endurance issues. Forming circuit is
extremely important.
Panasonic/IMEC, VLSI 2015
CMOS
Process Flow Pa
ssiv
atio
n Oxide Polish
Oxide Fill
PECVD/PEALD Liner
Treatment
Patte
rnin
g
Inspection
Post Etch Clean
Cell Material Etch
HM Open
Lithography
High Selective HM Dep
Cel
l Sta
ck Top Electrode Dep
ReRAM Stack Dep
Polish
Bottom Electrode
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Current e-NVM Status and Challenges
STT-MRAM, ReRAM, PCRAM as New e-NVM
Applied Materials New e-NVM Development Out
line
Conclusions
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Low Temperature High Quality Dielectrics For BEOL Integration
Flowable CVD Dielectrics (Surface chemical reaction leads to good film quality)
Source: Applied Materials Experimental Data
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ALD Dielectrics and Metals For HAR Structure Integration
Mean Thickness = 24.2Å WtW Uniformity = 0.53%, 1σ WiW Uniformity = 0.71%, 1σ TPT = 11.25 WPH
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24
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28
30
0 2,000 4,000 6,000 8,000 10,000 Wafer Count
Mea
n St
ack
Film
Thi
ckne
ss (A
)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
WiW
Uniform
ity (%)
Thickness
WiW Uniformity
Mean Thickness = 24.2Å WtW Uniformity = 0.53%, 1σ WiW Uniformity = 0.71%, 1σ HfO
25 30 35 40 45 50 55 60 65 70 75 80 852Theta (°)
0
200
400
600
Inte
nsity
(cou
nts)
TiN
Source: Applied Materials Experimental Data
TiN
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Endura PVD Technology For STT-MRAM Film Stack Precision Magnetic Film and MgO Dielectric
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Material Engineering – TaOx By O Implant In Ta Metal
Source: Applied Materials Experimental Data
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Cell ETCH and PEALD Dielectric For Novel Material Integration Solution
Typical Requirements – Flat HM – No visible metal re-dep – Minimize damage – >85˚ side wall – In-situ Encapsulation
Hard Mask Open
Critical Material ETCH Reactive Ion Etch Dual Ribbon Beam
PEALD Liner (Low Temp < 250˚C)
Dry Clean
Source: Panasonic/IMEC, VLSI 2015
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1
0
Byprod. Conc. (a.u.)
Sym3™ Etch – Control Byproducts
Pump
Sym3 Chamber High conductance Designed for efficient byproduct removal
Cathode
Simulation result
+
+
+
+
+ + + +
Plasma
+
+
+
+
+ + + +
Plasma
Low conductance leads to accumulation and resulting etch variation
High conductance produces uniform etch
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Minimizing Within-Die Variation: Loading Control
Tunable Radical / Ion flux Ratio with Pulsing and High Conductance Required for Micro and Depth Loading Control
20nm
Sym3 Performance Multiple Patterning Induced CD Variation
Loading Challenge
Source: Applied Materials Experimental Data
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Centura STT-MRAM Etch System For Non-Volatile Magnetic Material Etch Solution
Source: Applied Materials Experimental Data
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Current e-NVM Status and Challenges
STT-MRAM, ReRAM, PCRAM as New e-NVM
Applied Materials New e-NVM Development Out
line
Conclusions
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Summary Flash based e-NVM scaling faces scaling challenges
CMOS scaling outpaced e-NVM cell scaling. Transition to new cell technology is needed to align with advanced CMOS technology
Non-charged based STT-MRAM, PCRAM, ReRAM memory cells are compatible with advanced high K/MG CMOS and they are suitable for e-NVM scaling.
Implementation of new cell technology depends on e-NVM product requirements for the market and manufacturing cost
Applied Materials is very actively working in the STT-MRAM, PCRAM and ReRAM technologies
