fine line panel level fan-out -...

P - 1Copyright © 2017 Powertech Technology Inc. All Rights Reserved

Fine Line Panel Level Fan-Out

David FangCTO, Vice President of Powertech Technology Inc.


Outline

1. Brief Introduction of PTI

2. Moore’s Law Challenges & Solutions

• Moore’s Law Challenges

• Highly Integration SiP Solutions

3. Fine Line Panel Level Fan Out Technology

• Wafer Level v.s. Panel Level

• Panel Level Fan Out Challenges and Solutions

• Panel Level Fan Out Diversification

4. Summary


PTI Company Overview

Founded in 1997

Major Services:

Chip Probing, Bumping, WLP, Panel FO,

Packaging, Final Test, & Module Assembly

Revenue: $1.5B USD (2016)

Employees: ~16,000

15 plants worldwide

TaiwanHeadquarters (3D)

Hukou (3A)

Hukou (2A & 2B)

Hukou (3C)

HSP (P8 & P11)

WenHua (P9)

Hsinpu (P1)

Greatek


PTI Package Technology In Brief

CHIEFS® CLIP® PiFO®

Fan Out

50um Pitch CPB FC32D Stacking NAND

25um chip

Debut in 2007

SiP WLCSP

2008 2008 2011

2009 2010

CIS CSP

2013

3DIC Memory Cube 3DIC Memory on Logic

4D

memory

logic

2010

2.5D IC

2.5D/3DIC

chip1chip2

chip3

Interposer

TSV

Chip

Bump

BF2O®


Outline









4. Summary


Today’s accomplishments were yesterday’s impossibilities!

Electronics Industry Evolution

1960s1950s1940s 1970s ~

IBM 360 U. of Manchester

Vacuum tube Transistor

Integrated circuit

LSI~VLSI

18,000 vacuum tubes

John Ambrose Fleming, 1904John Bardeen, Walter Brattain,

and William Shockley, 1947

Jack Kilby, 1958

Pennsylvania State U.


Moore’s Law Challenges

Source: The Economist


SoC Challenges

SoC in FCBGA Chip Split & Re-constitution in SiP


Challenges of Conventional SiP

Challenges for conventional SiP

1. Performance degradation (long interconnection).

2. Power consuming (high transmission resistance).

3. Large form factor (substrate routing constraint).

Need solutions to allocate chips as close as possible.

SoC in FCBGA Conventional SiP


3DIC and 2.5DIC for SiP

Difficult TSV connection design

(different chip size).

Heat dissipation & data retention issue.

Thicker package than conventional SiP.

Additional interposer design and

manufacturing.

Interposer cost.

Extra tests to ensure known good

interposer.

3DIC SiP

2.5DIC SiP

Take time to coordinate different

chip suppliers and TSV designs.

High chips cost (same size

chips).

Interposer

Substrate

Chips


Fan Out SiP

Wide L/S fan out (> 10/10um) doesn’t have better performance than

FC SiP because long interconnection.

We need fine L/S fan out to place chips closer for better performance,

lower power consumption, and higher I/O density.

FC SiP

L/S>10/10um L/S 2/2~10/10um

FO SiP


Flip Chip 3DIC 2.5DIC Fine line

Fan Out

I/O density (#/mm2) 1x102 ~ 6x102 1x103 ~ 1x104 1x103 ~ 1x104 1x102 ~ 1x103

L/S (um) 9/12 < 2/2 < 2/2 2/2

Chip partition ◎ △ ◎◎ ◎◎

Bandwidth ◎ ◎◎◎ ◎◎ ◎◎

Total power

Thickness M M+ M L

Cost $$ $$$ $$$ $$-

Highly Integration SiP Solutions

Fine line Fan Out for highly integration has reasonable cost with

good performance.

Solution

Items


FO : Advantages & Applications

<5/5um L/S

Low insertion loss ,

Coplanar waveguide

>3 GHz CPU , GPU

Short path

Low J

PMIC , Power

Fine pitch pillar

High I/Os

High BW PoP Side-by-side

Short transmission

& High I/O interconnection

Logic + Memory

Thin RDL & PI

Low Z-height

Mobile AP


Fan-Out for Heterogeneous Integration

SoC

AP 14nm

BB 14nm

SoC on FCCSP

High wafer cost

Low wafer gross die

High NRE (mask)

FO (side-by-side)

Low wafer cost

Low NRE (mask)

Flexible to dynamic product mix

Quick time-to-market

AP

14nm

BB

28nm

AP

14nm

BB

28nm

RF

PMIC

IPD

FO SiP

Low COO

Easy to use / design-in

Small form factor


Fan-Out for Homo/Heterogeneous Integration (Chip Partition)

7 nm

Wafer Yield : ~30% Wafer Yield : ~70%

FCCSP Fan-Out

Chip Combo

Performance boosted

Value added by FO+ <

N-lane SerDes N-lane SerDes 2N-lane SerDes Chip Combo

1X dollars 1X dollars >2X dollars


Outline









4. Summary


Wafer Level or Panel Level

Package quantity ratio (per panel)

Package size

(mm2)

Wafer

level

Panel

level

15 x 15 1 3.6

20 x 20 1 3.9

30 x 30 1 4.0

40 x 40 1 4.5

300mm

wafer

3~5X

Package for “More than Moore” is

usually larger than 10x10mm. Panel

level provides 3~5X efficiency than

wafer level.

Suitable Player for Panel

Level Fan Out Setup

Wafer

foundryLCD PCB OSAT

IC package △ N N ○

Large panel △ ○ ○ ○-

Fine line ○ ○ △ ○

Warpage

control△ △ △ ○

Industry

Expertise

1. OSAT is in a good position to setup panel

level Fan Out.

2. Initial investment per module is 30~40%

higher than Fan In WLP.


Panel Level Fan Out Challenges

1. No worldwide standards

- 300 mm wafer has SEMI standards

- LCD and IC substrate has different panel size. What standard

should panel level follow ?

2. Tool and accessory readiness

- Lack of whole set of fine pitch panel tools

- Process cassette, loader / unloader, transportation

3. Product & Process Difficulty

- Panel warpage, chip shift, fine line patterning

Gen. Size (mm)

1 300x400

2 370x470

3 600x720

4 680x800

5 1100x1300

6 1500x1850

LCD panel

Type Size (mm)

A 400x500

B 500x500

C 500x600

D 600x600

PCB (IC substrate) panel


Tool Readiness for Panel Level Fan Out

Wafer foundry

(WLP, bumping)LCD PCB Picked

Tool

Coating A B C B

Exposure A B C B

Development A B C B

Deposition A B CPVD: B

ECD: A (E’)

Back-end A - - Expanded version

Accessory

Cassette

New design Transportation

Load Port

Industry

Process

Panel Level Fan Out leverages a mixed infrastructure.

We referred accessory of different industries to design suitable ones for panel

level Fan Out.

FOUP

OHT

Load Lock Open Env. Open Env.

Cassette Tray

TrollyAGV/MGV


Chip Preparation Die Embedding Patterning Backend

Cu post

BSG

Chip singulation

Molding

Mold grinding

Dielectric litho

PVD

RDL litho

Singulation

Major Panel Level Fan Out Process Flow (Chip First)

RDL ECD

Strip & etch

Marking

Ball mount

Debond

Chip mount


Warpage Challenge for Panel Level Fan Out

1. Structure, materials, and process optimization helps reducing warpage.

2. Special chuck, conveyor, and cassette designs also help to tolerate panel warpage.

A B C D E F G H I J K L M

Process steps

After

Acceptable warpage

Pan

el

warp

ag

e BeforeBig warpage

Small warpage

Panel

• Conveyor with guide rollers • Robot clamps with vacuum chuck


Chip Shift Challenge for Panel Level Fan Out

Chip mount accuracy

Mold parameters optimization

Lithography compensation

Add chip shift design tolerance

CTE matched design

Chip mount offset compensationGood alignment

Aligned

PI open to pad

mis-alignment

Chip

PadPI open Not aligned

Chip shift after mold cure

Original chip mount locationChip mount shift

intentionally

Chip move to correct position

after mold cure

Offset chip mount position intentionally to compensate chip shift after mold cure.

Pa

ne

l


CCD read die shift

AOI feedback chip shift to stepper.

Chuck will move to fit chip shift

Chip Shift Compensation

Θ

X

YCCD

Mask

Mask-to-Chip alignment

LDI creates patterns aligned with

shifted chip locations.

LDI

CCD detect chip

shift location

CCD

Laser Direct Imaging (LDI)


PTI Panel Level Fan Out Solutions

CHIEFS® :Chips Integration Embedded Fanout Solution

CLIP® : Chip Last Integration Package

ePLP® (embedded Panel Level Package)

ePLB® (embedded Panel Level BGA)

PiFO® : Pillars In FanOut

CHIEFS®

(Chip First)

CLIP®

(Chip Last)

PiFO®

(Chip Middle)

- Cheaper than CLIP ®

- AP, BB, ASIC, Memory

- Known Good RDL

- Passive available

- CPU, GPU, FPGA,

Thermal sensitive devices

- Pillars connect top and

bottom RDLs

- Passive available

- RF module, Sensor,

AP (PoPb), SiP, 3D stacking

- PMIC, Audio,

RF transceiver

BF2O®

(Bump Free)

BF2O® : Bump Free FanOut

RDL L/S : 8/8um qualified, 5/5um developed, 2/2um capability


Homogeneous Integration Fan Out

Chip A Chip A

3P2M+UBM

8/8 um

M1

M2


Heterogeneous Integration Fan Out

Chip BChip A

4P3M+UBM

M1

M2

M3

5/5 um


PiFO® (Pillar in FO)

controllerCu Pillar

Underfill

EMC

Top RDL 3P2M

Bottom RDL 3P3M+UBM

Bottom RDL first

100um

200um

55um

33um

M3M2

M1


Panel Level Fan Out Diversification

FO Sensor

FO SiP

FO AoP

FO compartment

EMI shield

FO stack

CHIEFS®

(Chip First)

CLIP®

(Chip Last)

PiFO®

(Chip Middle)

FO in package

FO_PoP w/ stacked chips FO_PoP w/ FI

embedded SBT

BF2O®

(Bump Free)

Homo/Heterogeneous Integration Specific Function


Outline









4. Summary


Summary

1. Panel level Fan-Out has advantages of small form factor,

high bandwidth, and good production efficiency for

highly integrated packages.

2. PTI setup the first fine line panel level Fan Out in

2H/2016 to extend Moore’s Law with homo /

heterogeneous integration.

3. We expect fine line Fan-Out would be adopted in a wide

range of applications. It is encouraged that more players

to join and make it prosperous.


Powertech Technology Inc.

No. 10, Datong Rd., Hsinchu Industrial Park, Hukou, Hsinchu, Taiwan. TEL: (886) 3 5980300

Powertech Technology (Suzhou) Ltd.

No. 33, Xinghai Street, Suzhou Industrial Park, Suzhou, China. TEL: (86) 0512 62523333

Powertech Technology (Singapore) Pte.Ltd.

12 Ang Mo Kio Street 65 Singapore 569060. TEL: (65) 6412 8181

Powertech Semiconductor (Xian) Co., Ltd.

Part B, Shaanxi Xi'an Export Processing Zone, No. 28, Xinxi Avenue, Xi'an, Shaanxi 710119 China.

TEL: (86) 29 81022888

Greatek Electronics Inc.

No. 136, Gung-Yi Rd., Chunan Town, Miaoli, Taiwan. TEL: (886) 37 638568

Tera Probe Inc.

KAKiYA Bldg., 2-7-17 Shin-Yokohama, Kohoku-ku, Yokohama City, Kanagawa. TEL: (81) 45 4761011

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