machine instructions

1Alberto Romano Schiesari – www.profars.com Prev.Page

Machine Instructions

MACHINE INSTRUCTIONS


Machine Instructions – Hints and Tips

Hints and Tips


Machine Instructions – Hints and Tips 1

1 - STORE = FROM register TO storage2 - LOAD = FROM storage TO register

3 - xxxxR = RR instruction, operands are both registers Example: AR,SR, LR, MR, DR, LTR4 - xxxxI = SI instruction, 1 operand is an immediate operand; it is the 2nd byte of the instruction, and is specified via an self-defining term (1 byte length) Example: MVI, SI, NI, OI, XI, etc5 - xxxxP = SS instruction, decimal packed operands, 2 lengths specification Example: AP, SP, MP, DP, ZAP6 - xxxxH = RX instruction, operands are 1 register and 1 halfword storage field Example: LH, SH, AH



7 - Nxxxx = boolean instruction AND Example: NI, NC, N, NR 8 - Oxxxx = boolean instruction OR Example: OI, OC, O, OR 9 - Xxxxx = boolean instruction Exclusive OR Example: XI, XC, X, XR

10 - Most instructions (except CVD and the STORE ones STC, ST, STH, STCM, STM):symbol instruction receiver_operand,emitter_operand

11 - STORE and CVD instructions: symbol instruction emitter_operand,receiver_operand



12 - SS-L instructions (only one length) are: MVN, MVC, MVZ, NC, CLC, OC, XC, TR, TRT, ED, EDMK, MVCINMaximum length of each operand is 256 bytes. 13 - SS-L1/L2 instructions (2 lengths) are: MVO, PACK, UNPK, ZAP, CP, AP, SP, MP, DPMaximum length for each operand is 16 bytes. 14 – SRP instruction is an exception in the SS group: it has a reference to a length (1st half of the 2nd byte), and a round (in the other half of the 2nd byte)



15 – Use of Boolean instructions:

OR = To force bits to 1 (turn ON bits)

This can be used to (for instance) : (a) Set program flags to ON(b) Transform lowercase leters into uppercase letters (mask 0100 0000 : note in an EBCDIC table that the difference between lowercase and uppercase letters is always x’40’ (b’0100 0000’); turning the 2nd bit ON one can transform a lowercase letter into an uppercase letter. (c) Transform a binary number into the nearest high odd number (turning rightmost bit ON) Example: 1111 1110 is decimal 254. Turning rightmost bit ON: 1111 1111 it becomes decimal 255




AND = Force bits to 0 (turn bits OFF)

This can be used to (for instance) : (a) Set program flags to OFF (b) Transform uppercase leters into lowercase letters (mask 1011 1111 : note in an EBCDIC table that the difference between uppercase and lowercase letters is always x’40’ (b’0100 0000’); turning the 2nd bit OFF one can transform an uppercase letter into a lowercase letter. (c) Transform a binary number into the nearest low even number (turning rightmost bit OFF) Example: 1111 1111 is decimal 255. Turning rightmost bit OFF: 1111 1110 it becomes decimal 254




XOR (ou exclusivo) = To invert bit setting (turns OFF if it is on, turns ON if it is OFF)

This can be used to (for instance) : (a) Inverte program flags (toggle flags)(b) Transform lowercase into uppercase letter and vice-versa (mask 0100 0000) :

letter x1xx xxxx becomes x0xx xxxxletter x0xx xxxx becomes x1xx xxxx

(c) Transform binary even numbers into odd numbers and vice-versa: (mask 0000 0001) : rightmost bit is inverted(d) Exchange the contents of 2 area without a 3rd auxiliary area :

XOR A,B + XOR B,A + XOR A,B(e) “Clear” (move binary zeros) an area :

XOR A,A



16 – Arithmetic and bit shift operations (algebraic / logic operations):

Unless othewise stated, these operations are done algebraically.This is always true for decimal packed fields.

For binary fixed point numbers (in storage and/or registers) some operations that work algebraically and other operations work logically.

Algebraic operations uses: 15-bit binary numbers + 1 bit sign for 2 byte numbers31-bit binary numbers + 1 bit sign for 4 byte numbers63-bit binary numbers + 1 bit sign for 8 byte numbers

Logical operations assume numbers are always positive and uses: 16-bit binary numbers for 2 byte numbers 32-bit binary numbers for 4 byte numbers 64-bit binary numbers for 8 byte numbers



Machine instructions (alphabetically)

A

AH

AL

ALR

AP

AR

BAL

BALR

BAS

BASR

BASSM

BC

BCR

BCT

BCTR

BSM

BXH

BXLE

C

CDS

CH

CL

CLC

CLCL

CLI

CLM

CLR

CP

CR

CS

CVB

CVD

D

DP

DR

ED

EDMK

EX

IC

ICM

IPM

L

LA

LCR

LH

LM

LNR

LPR

LR

LTR

M

MC

MH

MP

MR

MVC

MVCIN

MVCL

MVI

MVN

MVO

MVZ

N

NC

NI

NR

O

OC

OI

OR

PACK

S

SH

SL

SLA

SLDA

SLDL

SLL

SLR

SP

SPM

SR

SRA

SRDA

SRDL

SRL

SRP

ST

STC

STCK

STCM

STH

STM

SVC

TM

TR

TRT

TS

UNPK

X

XC

XI

XR

ZAP



(Some) Machine instructions (by group)- Storage to Storage move : MVC, MVZ, MVN, MVI, MVO, ZAP, MVCL, PACK, UNPK, MVCIN

- Register to Storage move : ST, STH, STM, STC, STCM, CVD

- Storage to Register move : L, LH, LM, IC, ICM, CVB

- Register to Register move : LR, LPR, LNR, LCR, LTR

- Arithmetic with Storage fields in the packed format : AP, SP, MP, DP, SRP

- Arithmetic with Registers (fixed point binary) : AR, SR, MR, DR, ALR, SLR

- Arithmetic with Register and Storage (fixed point binary) : A, S, M, D, AH, SH, MH, AL, SL

- Compare : CP, CLC, CLI, CLCL, C, CH, CL, CLM, CR, CLR

- Branch : BC, BCR

- Loop Control : BCT, BCTR, BXH, BXLE

- Edition : ED, EDMK

- Byte Translation and test: TR, TRT

- Register Shift : SLL, SRL, SLDL, SRDL, SLA, SRA, SLDA, SRDA

- Boolean Algebra : N, O, X, NR, OR, XR, NI, OI, XI, NC, OC, XC

- Load and branch : BALR, BAL, BAS, BASR, BASSM, BSM

- Misc : LA, TM, EX, SVC, MC, SPM, IPM, STCK, TS, CS, CDS



Hints: what instruction do I have to use to move data from a place to another?

Origin Destination Instruction

Storage Storage MVC

Register Register LR

Storage (zoned) Storage (packed) PACK

Storage (packed) Storage (zoned) UNPK (maybe, additionally, MVZ / OI)

Register Storage ST

Storage (binary) Register L

Storage (packed) Register (binary) CVB

Register (binary) Storage (packed) CVD

(address) Register LA [ or L reg,=A(address) ]

(address) Storage (contents=address) LA + ST [ or L + ST ]


Machine Instructions - A

A (ADD)

Instruction A adds algebraically the binary number in the 1st operand and the bynary number in a storage field (2nd operand – a full-word). Result is loaded into 1st operand register. Examples:Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after A 5,=F'259' 00.00.BF.D2 00.00.01.03 00.00.C0.D5 00.00.01.03 A 7,FULL 00.00.00.0D 00.00.01.03 00.00.01.10 00.00.01.03 A 7,4(2,8) 07.FF.FF.FE 00.00.00.01 07.FF.FF.FF 00.00.00.01 A 7,4(2) 07.FF.FF.FF FF.FF.FF.FF 07.FF.FF.FE FF.FF.FF.FF A 7,4(,8) 00.00.00.00 FF.FF.FF.FF FF.FF.FF.FF FF.FF.FF.FF

Machine Instruction Code

5A (RX Instruction)

Condition code 00 Result = 001 Result < 010 Result > 011 Overflow

Possible Interruptions 0005,0008

Mach.Inst.Summary


Machine Instructions - AH

AH (Add Halfword)Machine Instruction Code

4A (RX Instruction)



This instruction adds algebraically two binary numbers. One of them is in the register specified as 1st operand, and the other is a storage half-word specified as 2nd operand.Before the operation is executed, the half-word is internally expanded to 32 bits by repeating (to the left) the leftmost bit (sign bit). Result is loaded into 1st operand register. Examples:Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after AH 5,=H'259' 00.00.2B.C4 01.03 00.00.2C.C7 01.03 AH 5,HALF 00.00.00.0D 01.0D 00.00.01.1A 01.0D AH 5,4(2,8) 11.11.11.11 (decimal 286331153) 88.88 (decimal –30584) 11.10.99.99 (decimal 286300569) 88.88 AH 5,4(2) 11.11.11.11 (decimal 286331153) 78.88 (decimal +30856) 11.11.89.99 (decimal 286362009) 78.88

Mach.Inst.Summary


Machine Instructions - AL

AL (Add Logical)Machine Instruction Code

5E (RX Instruction)

Condition code 00 Result = 0, sign not lost01 Result <> 0, sign not lost10 Result = 0, sign lost11 Result <> 0, sign lost

Possible Interruptions 0005

This instruction adds logically two binary numbers. One of them is in the register specified as 1st operand, and the other is a storage full-word specified as 2nd operand. Both numbers are considered as positive 32-bit numbers. Result is loaded into 1st operand register. Examples:Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after AL 5,=F'259' 00.00.00.00 00.00.01.03 00.00.01.03 00.00.01.03 AL 5,FULL 00.B0.C4.E2 00.00.00.01 00.B0.C4.E3 00.00.00.01 AL 5,4(2,8) 7F.FF.FF.FF 00.00.00.01 80.00.00.00 00.00.00.01 AL 5,4(2) FF.FF.FF.FF 00.00.00.01 00.00.00.00 00.00.00.01 AL 5,4(,8) 80.00.00.00 00.00.00.01 80.00.00.01 00.00.00.01

Mach.Inst.Summary


Machine Instructions - ALR

ALR (Add Logical Register)Machine Instruction Code

1E (RR Instruction)

Condition code 00 Result = 0, sign not lost01 Result <> 0, sign not lost10 Result = 0, sign lost11 Result <> 0, sign lost

Possible Interruptions No interruptions occur

This instruction adds logically the contents of two binary numbers, both located in registers.Both numbers are considered as positive 32-bit numbers.Result is loaded into 1st operand register. Examples:Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after ALR 7,12 00.B0.C4.E2 00.00.00.01 00.B0.C4.E3 00.00.00.01 ALR 8,8 7F.FF.FF.FF 00.00.00.01 80.00.00.00 00.00.00.01 ALR 10,10 FF.FF.FF.FF 00.00.00.01 00.00.00.00 00.00.00.01 ALR 10,10 80.00.00.00 80.00.00.00 00.00.00.00 80.00.00.00

Mach.Inst.Summary


Machine Instructions - AP

AP (Add Packed)Machine Instruction Code

FA (SS Instruction – L1 e L2)


Possible Interruptions 0001,0004,0005,0007,000A

This instruction adds the contents of two packed numbers, both located in storage fields.Both numbers must be in the decimal packed format. Result is stored into 1st operand field. Examples: AP FLDA,FLDB before after FLDB 12.3C 12.3CFLDA 12.34.5C 12.46.8C

AP FLDA,FLDA before after FLDA 45.2C 90.4C

See more examples following:

Mach.Inst.Summary


Machine Instructions - AP

AP (Add Packed)Machine Instruction Code

FA (SS Instruction – L1 e L2)



Suppose the operands with the length and values shown in the “before” line 1st operand before 2nd operand before 1st operand after 2nd operand after AP HOWMANY,=P'1' 00.00.5F 1C 00.00.6C 1C AP ARL+2(5),ARL+7(2) 01.23.40.00.0C 98.7C 01.23.40.98.7C 98.7C AP TOTAL,2(3,7) 55.66.77.78.8C 11.11.1D 55.66.66.67.7C 11.11.1D AP 4(3,8),WALFA 01.99.9F 02.0C 02.01.9C 02.0C AP 7(07,8),14(2,3) 00.00.00.00.01.23.4C 00.5C 00.00.00.00.01.23.9C 00.5C AP GRANDTOT,SMALLTOT 00.00.00.0C 00.10.1C 00.00.10.1C

Mach.Inst.Summary


Machine Instructions - AR

AR (Add Register)Machine Instruction Code

1A (RR Instruction)



This instruction adds the contents of two binary numbers, both located in registers.The value of the register 2nd operand is added to the value of the register 1st operand.Result is stored into register 1st operand. Examples:

Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after AR 7,8 00.00.FF.FF 00.00.00.01 00.01.00.00 00.00.00.01 AR 2,2 00.00.FF.FF 00.00.FF.FF 00.01.FF.FE 00.01.FF.FE

Mach.Inst.Summary


Machine Instructions – BAL

BAL (Branch And Link)Machine Instruction Code

45 (RX Instruction)

Condition code Remains unchanged


BAL instruction is similar to the BALR instruction; the difference is that the address where the branch is to be made to (specified by the 2nd operand) is the instruction address in the base+displacement format (rather than the address in the register as in the BALR instruction). Note that to load the next instruction address (generally used as the return address when branching to execute a routine) BAL loads the last 4 bytes of PSW into 1st operand register. Examples:

Mach.Inst.Summary

BAL 9,ROUTINE BAL 14,WRTHDR BAL 7,2(5) BAL 7.2(,8) BAL 7,2(5,8)

...

... BAL 9,ROUTINERETINS EQU * continuation......ROUTINE ST 9,SAVEREG9........ L 9,SAVEREG9 BR 9

BAL loads the address of instruction labeled

RETINS into register 9

Save register 9 (return address) into SAVEREG9

Restore return address

Goback (to RETINS)


Machine Instructions - BALR

BALR (Branch And Link Register)Machine Instruction Code

05 (RR Instruction)



BALR instruction is similar to the BAL instruction; the difference is that the address where branch is to be made to (specified by the 2nd operand) is the value of the register 2nd operand (rather than the address in the base+displacement format as in the BAL instruction). Important: if the second operand is register zero, branch won’t be executed. Note that to load the next instruction address (generally the return address) BALR loads the last 4 bytes of PSW. Examples:

Mach.Inst.Summary

BALR 3,0 BALR 14,15

... LA 15,ROUTINE BALR 14,15RETINS EQU * continuation......ROUTINE ST 14,SAVEREG........ L 14,SAVEREG BR 14

BALR loads the address of instruction labeled

RETINS into register 14

Save register 14 (return address) into SAVEREG


Goback (to RETINS)

LA loads the address of instruction labeled

ROUTINE into register 15


Machine Instructions - BAS

BAS (Branch And Save)Machine Instruction Code

4D (RX Instruction)



The address of the next instruction (following BAS) is loaded in the register 1st operand: - Bytes 5, 6 and 7 (last 3 bytes of PSW) are loaded into bytes 1, 2 and 3 of the register - Leftmost byte of register 1st operand is set to zero (this is the difference between BAS and BAL)After loading the address, there’s a branch (jump) to the instruction specified in the 2nd operand. Example: BAS 14,ROUTINE

Mach.Inst.Summary

...

... BAS 9,ROUTINERETINS EQU * continuation......ROUTINE ST 9,SAVEREG........ L 9,SAVEREG BR 9

BAS loads the address of instruction labeled RETINS into register 9 bytes 1,2,3 and sets byte 0 with zero



Goback (to RETINS)


Machine Instructions - BASR

BASR (Branch And Save Register)Machine Instruction Code

0D (RR Instruction)



The address of the next instruction (following BASR) is loaded in the register 1st operand: - Bytes 5, 6 and 7 (last 3 bytes of PSW) are loaded into bytes 1, 2 and 3 of the register - Leftmost byte of register 1st operand is set to zero (this is the difference between BASR and BALR)After loading the address, there’s a branch (jump) to the instruction specified in the 2nd operand. Example: BASR 14,15

Mach.Inst.Summary

... LA 15,ROUTINE BASR 14,15RETINS EQU * continuation......ROUTINE ST 14,SAVEREG........ L 14,SAVEREG BR 14

BASR sets register 14 byte 0 with zero and loads the address of

instruction labeled RETINS into bytes 1,2,3 of register 14



Goback (to RETINS)




Machine Instructions - BASSM

BASSM (Branch And Save and Set Mode)Machine Instruction Code

0C (RR Instruction)



The address of the next instruction (following BASSM) is loaded in the register 1st operand: - Bytes 4, 5, 6 and 7 (last 4 bytes of PSW) are loaded into bytes 0, 1, 2, 3 of the register 1st operand - The value of register 2nd operand is loaded into bytes 4-7 of PSW; it includes leftmost bit (addressing mode) and (next) instruction address. Due to this, the addressing mode is (re)set and a branch is provided. Example: BASSM 14,15

Mach.Inst.Summary

LA 15,ROUTINE ICM 15,8,AMODE BASSM 14,15RETINS EQU * continuation......ROUTINE ST 14,SAVEREG........ L 14,SAVEREG BR 14

BASSM :- Sets register 14 with the address of instruction labeled RETINS into register 14 (taken from PSW)- Loads contents of register 15 into PSW bytes 4-7(Addressing mode is set [from reg. 15 into PSW] ) and (Branch to ROUTINE is executed)



Goback (to RETINS)



ICM sets addressability mode into register 15 bits


Machine Instructions - BC

BC (Branch on Condition)

There are 2 branch instructions: BC (RX Instruction) and BCR (RR Instruction).But they have many auxiliary mnemonic codes, named extended mnemonic codes. The branch instruction execution is based upon the status of Condition Code (remember? Those 2 bits of PSW) and the mask provided in the instruction (in the left half of its 2nd byte).The 4 different status Condition Code can be are: 00, 01, 10 and 11.For each one of them there is a corresponding code:

STATUS CODE

00 8

01 4

10 2

11 1

The MASK occupies half byte and indicates the condition in which branch MUST be done. It can vary from X'0' to X'F' (decimal 0 up to 15).MASK 8, CC B'00‘ = Branch executedMASK 4, CC B'01‘ = Branch executedMASK 2, CC B'10“ = Branch executedMASK 1, CC B’11’ = Branch executed

Mach.Inst.Summary



BC (Branch on Condition)

One can do a combination of the masks, by adding their value. For instance, if mask is X'C', it means that branch must occur if Condition Code is in the 8 or 4 status (8 + 4 = 12). If mask is zero, no branch will be done (NOP/NOPR = no operation). If mask is 15 (X'F') branch will be done no matter waht is the Condition Code setting, because 15 = all codes added (8+4+2+1); it is an unconditional branch. Branch instructions with masks from 1 to 14 are conditional branches: the branch will only be done if Condition Code is apropriately set. See in the following slide the list of mnemonic codes, the valid masks and the extended mnemonic codes.

Mach.Inst.Summary



BC (Branch on Condition)-------------------------------------------------------------------------- USE MNEMONIC MEANING BC/BCR EQUIVALENCE -------------------------------------------------------------------------- General B or BR Allways branches BC 15 or BCR 15 NOP or NOPR Never branches BC 0 or BCR 0-------------------------------------------------------------------------- After BH or BHR Branch if A > B BC 2 or BCR 2 Compare BL or BLR Branch if A < B BC 4 or BCR 4 BE or BER Branch if A = B BC 8 or BCR 8 BNH or BNHR Branch if A < or = B BC 13 or BCR 13 BNL or BNLR Branch if A > or = B BC 11 or BCR 11 BNE or BNER Branch if A not = B BC 7 or BCR 7-------------------------------------------------------------------------- After BO or BOR Branch if overflow BC 1 or BCR 1 Arithmetic BP or BPR Branch if R > 0 BC 2 or BCR 2 Instructions BM or BMR Branch if R < 0 BC 4 or BCR 4 BZ or BZR Branch if R = 0 BC 8 or BCR 8 BNP or BNPR Branch if R < or = 0 BC 13 or BCR 13 BNM or BNMR Branch if R > or = 0 BC 11 or BCR 11 BNZ or BNZR Branch if R not = 0 BC 7 or BCR 7--------------------------------------------------------------------------After TM BO or BOR Branch if all bits 1 BC 1 or BCR 1 BM or BMR Branch if mixed BC 4 or BCR 4 BZ or BZR Branch if all bits 0 BC 8 or BCR 8 BNO or BNOR Branch if some are 1 BC 14 or BCR 14--------------------------------------------------------------------------Notes: A = 1st operand ; B = 2nd operand ; R = 1st operand after compute

Mach.Inst.Summary



BC (Branch on Condition)The extended menmonic codes are: B = BranchNOP = No Operation BH = Branch High BL = Branch Low BE = Branch Equal BNH = Branch Not High BNL = Branch Not Low BNE = Branch Not Equal BO = Branch If Overflow BP = Branch If Plus BM = Branch If Minus BZ = Branch If Zero BNP = Branch If Not Plus BNM = Branch If Not Minus BNZ = Branch If Not Zero BO = Branch If Ones BM = Branch If Mixed BZ = Branch If Zeros BNO = Branch If Not Ones

Mach.Inst.Summary



BC (Branch on Condition)BC (Branch on Condition) Machine Instruction Code

47 (RX Instruction)



This instruction branches (or not) to another instruction. The format is:1st byte = operation code = 472nd byte – 1st half = mask2nd byte – 2nd half = index register for 2nd operand (branch instruction address)3rd and 4th byte = 2 bytes with base+displacement of 2nd operand (branch instruction address)1st operand is the mask; it indicates the condition branch must be done (or not).2nd operand address is the address to branch to. If condition indicated by the mask is not satisfied, branch is not done, the execution resumes on the next intruction (instruction following BC).If condition indicated by the mask is satisfied, branch is done, the execution resumes on the intruction addressed by the 2nd operand.

Mach.Inst.Summary




47 (RX Instruction)



If one uses the mnemonic code, only one “operand” must be specified: the address to branch to; in this case the mask is implicit in the mnemonic. Example: BC 8,AGAIN is the same as BE AGAIN BE is the same as BC 8.In this case, the branch will be done when condition code is 00. Other examples: B READ same as BC 15,READ BH AGAIN same as BC 2,AGAIN BL COMPARE same as BC 4,COMPARE BE 0(2) same as BC 8,0(2) BE 0(,4) same as BC 8,0(,4) BE 0(2,4) same as BC 8,0(2,4) NOP TOGGLE1 same as BC 0,TOGGLE1

Mach.Inst.Summary




47 (RX Instruction)



Other examples: B READ same as BC 15,READ BNH LOOP1 same as BC 13,AGAIN BNL LOOP2 same as BC 11,COMPARE BNE 0(2) same as BC 7,0(2) BZ 0(,4) same as BC 8,0(,4) BNZ 0(2,4) same as BC 7,0(2,4) BM BTAB(15) same as BC 4,BTAB(15)

Mach.Inst.Summary


Machine Instructions - BCR

BCR (Branch on Condition Register)BCR (Branch on Condition Register)

Machine Instruction Code 07 (RX Instruction)



BCR instruction is similar to BC instruction. SEE BC INSTRUCTION.The format is:1st byte = operation code = x’07’2nd byte – 1st half = mask (1st operand)2nd byte – 2nd half = register 2nd operand containing the branch instruction address1st operand is the mask; it indicates the condition branch must be done (or not).2nd operand register must contain the address to branch to. If condition indicated by the mask is not satisfied, branch is not done, the execution resumes on the next intruction (instruction following BCR).If condition indicated by the mask is satisfied, branch is done, the execution resumes on the intruction addressed by the 2nd operand.If one uses the mnemonic code, only the register 2nd operand must be specified.

See examples following:Mach.Inst.Summary


Machine Instructions - BCR

BCR (Branch on Condition Register)BCR (Branch on Condition Register)

Machine Instruction Code 07 (RX Instruction)



BCR 8,15 is the same as BER 15 BER is the same as BCR 8.In this case, the branch will be done when condition code is 00. Other examples:

BCR 2,10 same as BHR 10 BR 7 same as BCR 15,R7 BNER 10 same as BCR 7,R10 BLR 15 same as BCR 4,R15

Mach.Inst.Summary


Machine Instructions - BCT

BCT (Branch on CounT)Machine Instruction Code

46 (RX Instruction)



This instruction has 2 operands: the first one is a register, and the second is an instruction address.BCT subtracts 1 from the register 1st operand and after it compares the resulting number with zero. If result not equal to zero, it will provide a branch to the instruction referred in the 2nd operand If result is zero the branch won’t be done, processing will resume at the next instruction after BCT. Examples:

Mach.Inst.Summary

BCT 5,AGAIN BCT 2,0(4,7) BCT 2,0(4) BCT 2,0(,7)

... L 11,=F’200’AGAIN CLC 0(3,5),CODE BE FOUND...... BCT 11,AGAINNOTFND EQU * ........FOUND EQU *...

L loads into register 11 number of times loop

must be repeated

At the end of the set of loop instructions, BCT subtracts 1 from register 11. If zero not reached, branchs to AGAIN.If zero, resumes execution at

NOTFND


Machine Instructions - BCTR

BCTR (Branch on CounT Register)Machine Instruction Code

06 (RX Instruction)



BCTR instruction has 2 operands, both in registers.BCTR subtracts 1 from the register 1st operand and after it compares the resulting number with zero. If result not = zero, a branch is provided to the instruction whose address is in the register 2nd operand If result is zero the branch won’t be done, processing will resume at the next instruction after BCTR.

IMPORTANT: If 2nd operand is register zero, branch won’t be done; this is often used just to subtract 1 from a register, rather than, for instance, the S or SH instructions. Examples:

Mach.Inst.Summary

BCTR 2,7 BCTR 4,0

LA 15,AGAIN L 11,=F’200’AGAIN CLC 0(3,5),CODE BE FOUND...... BCTR 11,15NOTFND EQU * ........FOUND EQU *...

L loads into register 11 number of times loop

must be repeated

At the end of the set of loop instructions, BCTR subtracts 1 from register 11. If zero not reached, branchs to AGAIN.If zero, resumes execution at

NOTFND

LA loads into register 15 the address of AGAIN

instruction


Machine Instructions - BSM

BSM (Branch and Set Mode)Machine Instruction Code

0B (RR Instruction)



(a) The PSW’s addressing mode (bit 32) is loaded into bit 0 of the register 1st operand; bits 1-31 remain unchanged , and after that

(b) PSW’s Bytes 4-7 is loaded with contents of register 2nd operand (including addressing mode bit and next instruction address)

Thus a addressing mode setting is done followed by a branch.If 2nd operand is register zero, branch is not executed.Example:

BSM 14,15

Mach.Inst.Summary


Machine Instructions - BXH

BXH (Branch on indeX High)Machine Instruction Code

86 (RX Instruction)



1st and 2nd operands are registers.3rd operand is an instruction address.(a) The contents of register 2nd operand is added to the contents of register 1st operand, the result set into register 1st operand. (b) Result is compared with: Contents of register 2nd operand (if it is an odd register) or Contents of register following register 2nd operand (if it is an even register)If the compare result is Greater than it will be executed a branch to the instruction addressed by 3rd operand Less than or equal to the branch will not be executed; processing resumes at the instruction following BXH

Mach.Inst.Summary




86 (RX Instruction)



Examples:

BXH 7,8,AGAIN R7 = R8 + R7; If R7 > R9 Branch to AGAIN; * If R7 <= R9 next instruction

BXH 7,9,AGAIN R7 = R9 + R7; If R7 > R9 Branch to AGAIN;* If R7 <= R9 next instruction

BXH 7,9,8(4) R7 = R9 + R7; If R7 > R9 Branch to instruction * whose address is [ (contents R4) + x’008’ ]* If R7 <= R9 next instruction

Mach.Inst.Summary




86 (RX Instruction)



BXH 7,8,NOTFOUND R7 = R8 + R7; * If R7 > R9 all table already read; end search * If R7 <= R9 table not exhausted; continue search

Example: Use in a search loop:

R7 = begins with table address; incremented by element table length via R8R8 = Table element lengthR9 = Last element addressNOTFOUND : all table read, desired item not found.

L R7,=A(TABADRS) L R8,=A(20) L R9,=A(TABADRS+(HOWMANY-1)*LENGTH)NEXTITEM pointed item vs desired one if found, process it and go to TABLSEEN if not, point to next item BXH R7,R8,NOTFOUND B NEXTITEMTABLSEEN ...

Mach.Inst.Summary


Machine Instructions - BXLE

BXLE (Branch on indeX Less or Equal)Machine Instruction Code

87 (RS Instruction)



BXLE is similar to BXH instruction; the difference is that the branch is done if the result of the compare is Less or Equal. 1st and 2nd operands are registers.3rd operand is an instruction address.(a) The contents of register 2nd operand is added to the contents of register 1st operand, the result set into register 1st operand. (b) Result is compared with: Contents of register 2nd operand (if it is an odd register) or Contents of register following register 2nd operand (if it is an even register)If the compare result is Less or Equal to : it will be executed a branch to the instruction addressed by 3rd operand Greater than : the branch will not be executed; processing resumes at the instruction following BXLE

Mach.Inst.Summary




87 (RS Instruction)



Examples:

BXLE 7,8,AGAIN R7 = R8 + R7; If R7 <= R9 Branch to AGAIN; * If R7 > R9 next instruction

BXLE 7,9,AGAIN R7 = R9 + R7; If R7 <= R9 Branch to AGAIN;* If R7 > R9 next instruction

BXLE 7,9,8(4) R7 = R9 + R7; If R7 <= R9 Branch to instruction * Whose address is [ (contents R4) + x’008’ ]* If R7 > R9 next instruction

Mach.Inst.Summary




87 (RS Instruction)



BXLE 7,8,NOTFOUND R7 = R8 + R7; * If R7 <= R9 table not exhausted; continue search* If R7 > R9 all table already read; end search

Example: Use in a search loop:

R7 = begins with table address; incremented by element table length via R8R8 = Table element lengthR9 = Last element addressNOTFOUND : all table read, desired item not found

L R7,=A(TABADRS) L R8,=A(20) L R9,=A(TABADRS+(HOWMANY-1)*LENGTH)NEXTITEM compare pointed item vs desired one if found, process it and go to TABLSEEN if not, point to next item BXLE R7,R8,NEXTITEMNOTFOUND ...TABLSEEN ...

Mach.Inst.Summary


Machine Instructions - C

C (Compare)Machine Instruction Code

59 (RX Instruction)

Condition code 00 1st operand = 2nd operand01 1st operand < 2nd operand10 1st operand > 2nd operand 11 Condition code is not set as 11 after C


C performs an algebraic compare between a binary number in a register (1st operand) and a binary number in a storage field (a full-word, the 2nd operand). Example: C 9,CPO C 8,=F'0' C 13,=A(TABLE+430) C 1,2(4) C 1,2(,4) C 1,2(7,4)

Mach.Inst.Summary


Machine Instructions - CDS

CDS (Compare Double and Swap)Machine Instruction Code

BB (RS Instruction)

Condition code 00 1st operand equal to 2nd operand, 3rd operand moved to 2nd operand01 1st operand not equal to 2nd operand, 2nd operand moved to 1st operand 10 Condition code is not set as 11 after CDS 11 Condition code is not set as 11 after CDSPossible Interruptions 0004,0005,0006

1st and 3rd operands are even registers. They are considered an indication of: 1st operand: double-word composed by R1 and R1+13rd operand: double-word composed by R3 and R3+12nd operand is an storage field (double-word).Contents of 1st operand (R1 and R1+1) is compared with the contents of the double-word 2nd operand.If they are equal, the contents of the 3rd operand (R3 and R3+1) is stored into the 2nd operand double-word.If they are not equal, the contents of the double-word 2nd operand is loaded into the 1st operand (R1 and R1+1). See the following examples:

Mach.Inst.Summary


Machine Instructions - CDS

CDS (Compare Double and Swap)Machine Instruction Code

BB (RS Instruction)

Condition code 00 1st operand equal to 2nd operand, 3rd operand moved to 2nd operand01 1st operand not equal to 2nd operand, 2nd operand moved to 1st operand 10 Condition code is not set as 11 after CDS 11 Condition code is not set as 11 after CDS

Possible Interruptions 0004,0005,0006

CDS 4,8,DW Before: R4/R5 00.BF.C4.20.50.CC.A0.00 R8/R9 7D.48.C0.00.00.00.00.02 DW 00.BF.C4.20.50.CC.A0.00 After: R4/R5 00.BF.C4.20.50.CC.A0.00 R8/R9 7D.48.C0.00.00.00.00.02 DW 7D.48.C0.00.00.00.00.02

CDS 4,8,DW Before: R4/R5 00.CC.DD.EE.FF.FF.FF.FF R8/R9 7D.48.C0.00.00.00.00.02 DW 00.BF.C4.20.50.CC.A0.00 After: R4/R5 00.BF.C4.20.50.CC.A0.00 R8/R9 7D.48.C0.00.00.00.00.02 DW 00.BF.C4.20.50.CC.A0.00

Mach.Inst.Summary


Machine Instructions - CH

CH (Compare Halfword)Machine Instruction Code

49 (RX Instruction)

Condition code 00 1st operand = 2nd operand01 1st operand < 2nd operand10 1st operand > 2nd operand 11 Condition code is not set as 11 after CH


CH performs an algebraic compare between a binary number in a register (1st operand) and a binary number in a storage field (a half-word, the 2nd operand). To do that, the 2nd operand is expanded (internally in the CPU) to 4 bytes, by repeating (to the left) 16 times the leftmost bit of the half-word.Example: CH 9,FLD 1st operand = R9; 2nd operand = FLD field CH 8,=H'0' 1st operand = R8; 2nd operand = half-word with zeros CH 13,=Y(TAB+430) 1st operand = R13; 2nd operand = half-word with address of TAB+430 CH 1,2(4) 1st operand = R1; 2nd operand = storage half-word which * address = value of index register R4 +0[base register omitted] + x’2’ CH 1,2(,4) 1st operand = R1; 2nd operand = storage half-word which * address = value of base register R4 +0[index register omitted] + x’2’ CH 1,2(7,4) 1st operand = R1; 2nd operand = storage half-word which* address = value of base register R4 +R7[index register] + x’2’

Mach.Inst.Summary


Machine Instructions - CL

CL (Compare Logical)Machine Instruction Code

55 (RX Instruction)

Condition code 00 1st operand = 2nd operand01 1st operand < 2nd operand10 1st operand > 2nd operand 11 Condition code is not set as 11 after CL


The CL instruction compares logically the contents of register 1st operand and the contents of a storage full-word (2nd operand). Logical compare is done left to right, one bit at a time; the first couple of unequal bits finish the operation.. Examples: CL 9,CPO 32 bits of register 9 compared with 32 bits of 4-byte CPO CL 8,=F'0' 32 bits of register 8 compared with 32-bit of 4-byte full-word with zero CL 1,2(4) 32 bits of register 1 compared with 4-byte storage field * ( 2nd operand address = contents of index reg. 4 + displacement X’2’ [base reg. omitted = zero = not considered] ) CL 1,2(,4) 32 bits of register 1 compared with 4-byte storage field* ( 2nd operand address = [ index reg. Omitted = zero = not considered] + displacement X’2’ + base reg.4 ) CL 1,2(7,4) 32 bits of register 1 compared with 4-byte field* ( 2nd operand address = contents of index reg. 7 + displacement X’2’ + contents of base reg. 4 )

Mach.Inst.Summary


Machine Instructions - CLC

CLC (Compare Logical Character)Machine Instruction Code

D5 (SS Instruction – L)

Condition code 00 1st operand = 2nd operand01 1st operand < 2nd operand10 1st operand > 2nd operand 11 Condition code is not set as 11 after CLC


This instruction compares logically (left to right, one bit at a time) two storage fields. The first not equal couple of bits finish the compare. Examples: CLC CPOA,CPOB Only one length used = length of CPOA (e.g. 100 bytes) CLC AE+78(2),=C'*1' 2-byte (AE+78 and AE+79) storage field is compared with * 2-byte storage field referenced via literal (contents = X’5CF1’) CLC 4(2,7),2(9) 2 bytes field (address = base register 7 + displacement X’4’) * is compared with storage field ( address = base register 9 + displacement X’2’ ) CLC ID,2(7) n-byte storage field ID is compared with n-byte storage field * (address = base register 7 + displacement X’2’ ) CLC 194(5,11),AE+3 5-byte storage field (address = base register 11 + displacement X’C2’) * is compared with 5-byte storage field ( address = AE+3 )

Mach.Inst.Summary


Machine Instructions- CLCL

CLCL (Compare Logical Character Long)Machine Instruction Code

0F (RR Instruction)

Condition code 00 1st operand = 2nd operand or both operands have zero length.01 1st operand < 2nd operand10 1st operand > 2nd operand11 Condition code is not set as 11 after CLCL


This instruction compares two storage fields, in a similar way the CLC does.Both 1st and 2nd operands must be even registers. They indicate (each one of them) a pair of even-odd registers. We’ll call them: 1st pair = R1st and R1st+1; 2nd pair = R2nd and R2nd+1The 1st operand (receiver field) address must be in the last 3 bytes (righmost) of R1st.The 2nd operand (sender field) address must be in the last 3 bytes (righmost) of R2nd.The 1st operand length must be in the last 3 bytes (rightmost) of R1st+1.The 2nd operand length must be in the last 3 bytes (rightmost) of R2nd+1. The leftmost byte of R2nd+1 must have the padding character.The leftmost byte of R1st, the leftmost byte of R2nd and the leftmost byte of R1st+1 are not considered in the operation. Example: CLCL 2,8R2=1st operand register (dubbed as R1st above); note that R1st+1 = register 3R8=2nd operand register (dubbed as R2nd above); note that R2nd+1 = register 9

Mach.Inst.Summary




0F (RR Instruction)

Condition code 00 1st operand = 2nd operand or both operands are zero length.01 1st operand < 2nd operand10 1st operand > 2nd operand11 Condition code is not set as 11 after CLCLPossible Interruptions 0005,0006

Compare is done one bit at a time, from left to right. When not 2 bits unequal are found OR when length of greater operand is exhausted compare is finished. If the operands have no equal kengths, the smaller one is extended with the padding character (internally, without any change in the field).If compare is finished due to 2 bits unequal encountered:- From the value in the rightmost 3 bytes of R1st+1 and R2nd+1 is subtracted the amount of equal bytes; if the difference was found with the padding character the rightmost 3 bytes of R1st OR R2nd+1 are zeroed (the ones who have the smallest length).- To the value of the rightmost 3 bytes of R1st and R2nd is added the amount of equal bytes.If both operands are equal (including the padding character, if needed):- The 3 rightmost bytes of R1st+1 AND R2nd+1 are zeroed.- To the 3 rightmost bytes of R1st AND R2nd is added the amount of equal bytes. In both cases : the leftmost byte of R1 and the leftmost byte of R2 are zeroed, and the leftmost byte of R1st+1 and R2nd+1 remain unchanged.

Mach.Inst.Summary




0F (RR Instruction)

Condition code 00 1st operand = 2nd operand or both operands are zero length.01 1st operand < 2nd operand10 1st operand > 2nd operand11 Condition code is not set as 11 after CLCLPossible Interruptions 0005,0006

Mach.Inst.Summary

Example: LA 2,BUFEROUT LA 3,12000 LA 8,BUFERIN LA 9,20000 ICM 9,B'1000',C' ' AGAIN CLCL 8,9 BE EQUALSDIFFS EQU *...... ......EQUALS EQU *...

LA loads into register 2 the BUFEROUT address

CLCL executes the compare between a 12000-byte field (BUFEROUT) and a 20000-

byte field (BUFERIN)

LA loads into register 3 the BUFEROUT length

LA loads into register 8 the BUFERIN address

LA loads into register 9 the BUFERIN length ICM inserts padding

character into leftmost byte of register 9


Machine Instructions - CLI

CLI (Compare Logical Immediate)Machine Instruction Code

95 (SI Instruction)

Condition code 00 1st operand = 2nd operand01 1st operand < 2nd operand10 1st operand > 2nd operand 11 Condition code is not set as 11 after CLI


This instruction compares logically (left to right, one bit at a time) two storage fields. The first operand is a “normal” storage field with its address expressed with a base+displacement address.The second operand is also a storage field, but it is located IN the instruction: it is the instruction’s 2nd byte. It’s not necessary to specify its address, only its contents.Examples (note that b1d1d1d1 is the address of the 1st operand, in the base+displacement format):

CLI AE+79,C'*' Machine code = 95.5C.b1d1.d1d1 Compare with asterisk

CLI 2(5),X'00' Machine code = 95.00.50.02 Compare with binary zeros

CLI BYTE,B'11110000' Machine code = 95.F0.b1d1.d1d1 Compare with character zero

CLI NOP+1,240 Machine code = 95.F0.b1d1.d1d1 Compare with character zero

Mach.Inst.Summary


Machine Instructions - CLM

CLM (Compare Logical under Mask)Machine Instruction Code

BD (RS Instruction)

Condition code 00 Selected bytes are equal, or mask is zero01 Selected field of the 1st operand is less than 2nd operand10 Selected field of the 1st operand is greater than 2nd operand11 Condition code is not set as 11 after CLMPossible Interruptions 0005

The contents of register 1st operand is logically compared (left to right, one bit at a time) with the contents of the 2nd operand, based on the control of the mask 3rd operand. The result is reflected in the setting of the condition code.It’s a RS instruction, with the following format:Byte 1= x’BD’ (operation code); Byte 2 = left half = R1 = register 1st operand; right half = M3 =(mask)Bytes 3 and 4 = 2nd operand address (base+displacement)The 4-bit mask, left to right, are related to the 4 bytes of the register 1st operand. The register bytes whose bits in the mask are ON are considered as a contiguous field, and compared with the storage field specified in the 2nd operand (the 2nd operand must have a length equal to the number of bits ON in the mask.The register bytes whose bits in the mask are OFF are not considered in the operation. Example: CLM 5,B'1011',ARCOMPThe “field” composed by 1st , 3rd and 4th bytes of register 5 is compared with the 3-byte field named ARCOMP.

Mach.Inst.Summary


Machine Instructions - CLR

CLR (Compare Logical Register)Machine Instruction Code

15 (RR Instruction)

Condition code 00 1st operand = 2nd operand01 1st operand < 2nd operand10 1st operand > 2nd operand11 Condition code is not set as 11 after CLR


The CLR instruction compares logically the contents of the 2 registers (1st operand and 2nd operand). Logical compare is done left to right, one bit at a time; the first couple of unequal bits found finish the operation. Examples:

CLR 4,5 32-bit “string” of register 4 compared with 32 bit “string” of register 5

CLR 8,13 32-bit “string” of register 8 compared with 32-bit “string” of rregister 13

Mach.Inst.Summary


Machine Instructions - CP

CP (Compare Packed)Machine Instruction Code

F9 (SS Instruction – L1 e L2)

Condition code 00 1st operand = 2nd operand01 1st operand < 2nd operand10 1st operand > 2nd operand 11 Condition code is not set as 11 after CP


The CP instruction compares the contents of 2 storage fields ( 1st and 2nd operands). Both must be in the decimal packed format, and remain unchanged. The lengths can be different: the values are compared, not the sizes. Examples: CP FLDA,FLDB If FLDA = X’00000009999C’ and FLDB = X’10000C’* Result is : 1st operand less than 2nd operand

CP COUNTLIN,=P'1' If COUNTLIN = X’999999D’ compared with X’1C’* Result is : 1st operand less than 2nd operand

CP 0(5,9),=P'0' Compares contents of 5-byte field at address * (base register 9 + X’0’) with zero

CP TOTAL,2(7,9) Compares contents of TOTAL with 7-byte field address (base register 9 + displacement X’2’)

Mach.Inst.Summary


Machine Instructions - CR

CR (Compare Register)Machine Instruction Code

19 (RR Instruction)

Condition code 00 1st operand = 2nd operand01 1st operand < 2nd operand10 1st operand > 2nd operand11 Condition code is not set as 11 after CR


The CR instruction compares 2 binary numbers within 2 registers (1st and 2nd operands). Both remain unchanged. Examples:

CR 4,5 31-bit binary number in register 4 compared with 31-bit binary number in register 5

CR 8,13 31-bit binary number in register 8 compared with 31-bit binary number in register 13

Mach.Inst.Summary


Machine Instructions - CS

CS (Compare and Swap)Machine Instruction Code

BA (RS Instruction)

Condition code 00 1st operand equal to 2nd operand, 3rd operand moved to 2nd operand01 1st operand not equal to 2nd operand, 2nd operand moved to 1st operand10 Condition code is not set as 10 after CS 11 Condition code is not set as 11 after CSPossible Interruptions 0004,0005,0006

1st and 3rd operands are registers.2nd operand is a storage field (full-word).The contents of the register 1st operand is compared with the 2nd operand full-word. If they are equal, the contents of register 3rd operand is stored in the 2nd operand full-word.If they are unequal the contents of the 2nd operand full-word is loaded into register 1st operand. Examples: CS 5,8,FWBefore: R5 00.BF.C4.20 R8 7D.48.C0.00 FW 00.BF.C4.20After: R5 00.BF.C4.20 R8 7D.48.C0.00 FW 7D.48.C0.00

CS 5,8,FWBefore: R5 00.BF.C4.20 R8 7D.48.C0.00 FW 00.FF.EE.DDAfter: R5 00.FF.EE.DD R8 7D.48.C0.00 FW 00.FF.EE.DD

Mach.Inst.Summary


Machine Instructions - CVB

CVB (ConVert to Binary)Machine Instruction Code

4F (RX Instruction)


Possible Interruptions 0005, 0007, 0009

The decimal packed number within the 8-byte field 2nd operand (normally a double-word – it remains unchanged), is converted to binary and loaded into 1st operand register. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after CVB 8,DOUBLE 12.BC.4F.CA 00.00.00.00.00.01.02.4D FF.FF.FC.00 00.00.00.00.00.01.02.4D* 2nd operand = DOUBLE CVB 8,0(5,9) FF.FF.FF.FF 00.00.00.00.00.01.02.5C 00.00.04.01 00.00.00.00.00.01.02.5C* 2nd operand address = index register 5 + base register 9 + X’0’ CVB 8,0(,9) FF.FF.FF.FF 00.00.00.00.00.01.02.3F 00.00.03.FF 00.00.00.00.00.01.02.3F* 2nd operand address = index register 0 + base register 9 + X’0’ CVB 8,0(5) FF.FF.FF.FF 00.00.00.00.00.01.02.3C 00.00.03.FF 00.00.00.00.00.01.02.3C* 2nd operand address = index register 5 + base register 0 + X’0’

Mach.Inst.Summary


Machine Instructions - CVD

CVD (ConVert to Decimal [packed])Machine Instruction Code

4E (RX Instruction)



The binary number within the register 1st operand is converted to decimal packed format and stored into the 8-byte field 2nd operand (normally a double-word).For positive numbers or zero, sign is ‘C’. For negative numbers sign is ‘D’.Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after CVD 8,DOUBLE 00.00.10.00 00.00.00.00.00.00.00.70 00.00.10.00 00.00.00.00.00.04.09.6C* 2nd operand = DOUBLE CVD 8,0(5,9) FF.FF.FF.FF 00.00.FB.EC.44.CC.F0.F1 FF.FF.FF.FF 00.00.00.00.00.00.00.1D* 2nd operand address = index register 5 + base register 9 + X’0’ CVD 8,0(,9) 00.00.99.99 98.BA.76.FE.54.DC.32.B9 00.00.99.99 00.00.00.00.00.39.32.1C* 2nd operand address = index register 0 + base register 9 + X’0’ CVD 8,0(5) 00.00.AA.AA 00.00.00.00.00.00.00.0C 00.00.AA.AA 00.00.00.00.00.43.69.0C* 2nd operand address = index register 5 + base register 0 + X’0’

Mach.Inst.Summary


Machine Instructions - D

D (Divide)Machine Instruction Code

5D (RX Instruction)



This instruction executes a division between 2 binary numbers. 1st operand indicate an even register; it is the the first of a couple registers (even+odd); together they must have a fixed-point number, whose format is: 1 sign bit + 63 binary-digit bits.The number within this couple of registers is the dividend.The divisor is the number within the 2nd operand storage field (full-word). After division:-The remainder is stored into the even register from the even-odd couple.- The quotient is stored in the odd register from the even-odd couple.Examples: L 6,=F'0' Dividend: Registers 6-7 together; L 7,=F'257' They have the number 257 D 6,=F'4' Divisor: (literal) with number 4; Quotient: Register 7 = 64; Remainder: Register 6 = 1* L 10,=F'0' Dividend: Registers 10-11 together; L 11,=F'17' They have the number 17 D 10,=F'3' Divisor: (literal) with number 3; Quotient: Register 11 = 5; Remainder: Register 10 = 2*

Mach.Inst.Summary


Machine Instructions - DP

DP (Divide Packed)Machine Instruction Code

FD (SS Instruction – L1 e L2)


Possible Interruptions 0004,0005,0006,0007,000B

The DP instruction executes a division between 2 storage fields, both in packed decimal format. 1st operand is the dividend, and 2nd operand is the divisor. After division the quotient and the remainder are stored in the 1st operand storage field.2nd operand remains unchanged.About the 2nd operand divisor (a) it remains unchanged after division (b) it cannot exceed 8 bytes (c) its length cannot be greater than or equal to the 1st operand length (d) if condition b or c occurs, program will interrupt with code 0006.The remainder is stored in the rightmost bytes of the 1st operand, with divisor’s length.Code 000B interruption occurs when: Quotient’s length is greater than the length available to it in the 1st operand Dividend has not at least 1 leftmost zero algarism. Divisor is zero.

See the following examples:

Mach.Inst.Summary


Machine Instructions - DP

DP (Divide Packed)Machine Instruction Code

FD (SS Instruction – L1 e L2)


Possible Interruptions 0004,0005,0006,0007,000B

Suppose the operands with the length and values shown in the “before” line

1st operand before 2nd operand before 1st operand after 2nd operand after DP FLDA,FLDB 00.00.45.67.8C 00.2C 22.83.9C.00.0C 00.2C DP FLDA,FLDB 00.00.00.11.1C 00.2C 00.05.5C.00.1C 00.2C DP VALUE,=P'5' 00.00.00.00.00.12.7C 5C 00.00.00.00.02.5C.2C 5C


Machine Instructions - DR

DR (Divide Register)Machine Instruction Code

1D (RR Instruction)



This instruction executes a division between 2 binary numbers, both in registers. 1st operand must indicate an even register; it is the the first of a couple registers (even+odd); together they must have a fixed-point number, whose format is: 1 sign bit + 63 binary-digit bits.The number within this couple of registers is the dividend. 2nd operand is the divisor.After division:- The quotient is stored into the odd register- The remainder is stored into the even register- If the remainder and/or quotient are = 0, their sign will be 0; remainder’s sign is the same as dividend’s sign Examples: L 12,=F'2' Divisor: Register 12 with number 2 L 4,=F'0' Dividend: Registers 4-5 together; L 5,=F'257' They have the number 257 DR 4,12 Quotient: Register 5 = 128; Remainder: Register 4 = 1* L 9,=F'12' Divisor: Register 9 with number 12 L 6,=F'0' Dividend: Registers 6-7 together; L 7,=F'148' They have the number 148 DR 6,9 Quotient: Register 7 = 12; Remainder: Register 6 = 4

Mach.Inst.Summary


Machine Instructions - ED

ED (Edit)Machine Instruction Code

DE (SS Instruction – L)

Condition code 00 Last field = 001 Last field < 010 Last field > 011 Condition code is not set as 11 after ED


Syntax: [symbol] ED receiving_field,sending_field The 1st operand must have been prepared, prior to the edition, with the edition mask (e.g. move the edition mask to the 1st operand of edit instruction). The sending field (2nd operand) is converted from packed decimal to zoned decimal, and stored into the receiving field (1st operand), ovelaying therefore the mask in the 1st operand.Edition means the control and inclusion, if needed, of sign, visual characters (e.g. decimal point, 3-digit separators), and supression of non-significant zeros.One may edit many packed fields in just one execution of ED instruction.The (only) length specified is applied just to the 1st operand.The 2nd operand must be in the decimal packed format. If any byte of the 2nd operand have in his left half the configurations A, B, C, D , E or F, it will occur a program interruption (code 0007).Edit is done left to right.

Mach.Inst.Summary







The bytes of mask may have: X'20‘ = digit selector; X’21’ = significance trigger, X’22’ ) = field separator , or any other contents (in this last case, it’s just a character to be inserted for visual pirposes)During edition, each character of the receiving field (mask – 1st operand) may have go into one of the 3 ways:Remain unchangedSubstituted by an algarism of the sending field (converted to zoned format)Substituted by the leftmost character of the 1st operand mask (FILLING character).To make the opetion from the 3 alternatives, CPU must analyse the mask, and consider the algarism being edited (is it zero or not?).The process is as follows:

Mach.Inst.Summary







The mask’s leftmost byte is analysed; if it is X’20’ or X’21’ it’s assigned as padding character and the edition starts with it.Each one of the following bytes can have one of the following configurations:Digit selector (X'20') or S-Trigger (X'21') or Field separator (X'22') or Any otherIn the edition, when is detected a X’20’ or X’21’ in the 1st operand, instruction v erifies:The S-Trigger : significance indicator; it is a CPU flag; it can be ON or OFF. The digit carresponding at the 2nd operand.As a result of the verification, the configuration in the mask in the 1st operand will be substituted by the corresponding digit in the 2nd operand converted to zoned (if digit in the 1st operand is X’20’ or X’21’), or by the padding character (if not X’20’ nor X’21’).

Mach.Inst.Summary







About the S-trigger: It is turned OFF (a) at the beginning of the ED execution or (b) after a X’22’ is found in the mask or (c) when a X’A’ or X’C’ or ‘E’ or ‘F’ is found in the right phalf of any byte of the 2nd operand (the packed field being edited) It is turned ON (a) after a X’21’ is detected in the mask or (b) when a ‘X20’ is detected in the mask WITH its corresponding digit in the sending field being NOT zero. For these 2 cases the right half of the byte in the sending field doesn’t have X’A’ or X’C’ or ‘E’ or ‘F’.

About Field separator (X'22') : it identifies fields in a multi-field edition. It is always substituted by the padding character

Examples:

Mach.Inst.Summary







Note that lowercase b means a (blank) space. MVC WPAREA+5(10),MASK ED WPAREA+5(10),TOTAL.MASK DC X'4020204B202126B2020' Before: TOTAL 00.12.34.5C WPAREA+5(10) 40.20.20.4B.20.21.20.6B.20.20.20 b b b b 1 2 3 , 4 5After: TOTAL 00.12.34.5C WPAREA+5(10) 40.40.40.40.F1.F2.F3.6B.F4.F5 b b b b 1 2 3 , 4 5

Other examples: ED 0(5,7),CPO ED ARIMP+17(8),ISDRT ED 4(12,9),2(10)

Mach.Inst.Summary


Machine Instructions - EDMK

EDMK (Edit and Mark)Machine Instruction Code

DF (SS Instruction – L)

Condition code 00 Last field = 001 Last field < 010 Last field > 011 Condition code is not set as 11 after EDMK


This instruction is analog to the ED instruction.It loads into register 1 (bits 8-31; bits 0-7 remain unchanged) the address of the byte in the 1st operand who received the 1st non-zero digit. Note that the address is not loaded when significance is forced (using X'21').Example: EDMK ARIMP+5(10),TOTAL

Mach.Inst.Summary


Machine Instructions - EX

EX (Execute)Machine Instruction Code

44 (RX Instruction)

Condition code The setting (or not) depends on the executed instruction


The 2nd operand specifies an instruction address.The instruction it refers to is temporarily (internally in theCPU) modified according to the value of the register specified as 1st operand. With this tomporary change, it is executed.The temporary changing is made applying a boolean OR (mask = rightmost byte of 1st operand register; object = 2nd byte of instruction addressed by 2nd operand).Note that both EX operands remain unchanged. If 1st operand is register 0, OR won’t be done, the instruction will be executed as it is in storage, with no change in the 2nd byte.Example: L 5,=F'22' EX 5,MVC . . MVC MVC 0,(0,12),=CL256' '

Move will be executed with length 23

Mach.Inst.Summary


Machine Instructions - IC

IC (Insert Character)Machine Instruction Code

43 (RX Instruction)



The contents of the byte specified in the 2nd operand is inserted into the rightmost byte of the register 1st operand; leftmost 3 bytes remain unchanged. Example:Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register1st operand after 2nd operand after IC 4,BYTE 00.00.45.67.8C 6B 00.00.45.67.6B 6B IC 8,=C'K' 00.00.00.11.1C D2 00.00.00.11.D2 D2 IC 11,=HL1'125' 00.00.00.00.00.12.7C 7D 00.00.00.00.02.5C.2C 7D

Mach.Inst.Summary


Machine Instructions - ICM

ICM (Insert Character under Mask)Machine Instruction Code

BF (RS Instruction)

Condition code 00 All inserted bits are 0, or mask is zero.01 1st bit of inserted field is 1.10 1st bit of inserted field is 0, and not all inserted bits are zero. 11 Condition code is not set as 11 after ICM.Possible Interruptions 0005

The format of this instruction is:1st byte: X’BF’ (operation code); 2nd byte, left half : 1st operand register ; 2nd byte, right half : 3rd operand (mask); 3rd and 4th bytes : 2nd operand address, base+displacement format. The 4 bits in the mask correspond to the 4 bytes of the 1st operand register.The storage field specified in the 2nd operand must have as many bytes as the ON bits in the mask. The storage bytes are inserted left to right into the bytes of 1st operand byteswhose bits in the mask are ON.The remaining bytes of the register remain unchanged. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register1st operand after 2nd operand after ICM 5,B'1010',TWOBYTES 00.00.45.67 9A.BC 9A.00.BC.67 9A.BC 1st byte from TWOBYTES is inserted into 1st byte of register 5 and 2nd byte from TWOBYTES is inserted into the 3rd byte of register 5.

Mach.Inst.Summary


Machine Instructions - IPM

IPM (Insert Program Mask)Machine Instruction Code

B222 (RR InstructionE)



Bits 16-23 (3rd byte) and 28-31 (4th byte right) of the instruction are ignored.Condition code and program mask (from PSW) are copied into bits 2-3 (condition code) and bits 4-7 (program mask) into the corresponding bits of 1st operand register.Bits 0-1 of the register are zeroed, and bits 8-31 remain unchanged.Example:Suppose PSW with condition code ’01’ and program mask ‘1100’ register 8 before register 8 after IPM 8 C4.56.78.9A 1C.56.78.9A

Mach.Inst.Summary


Machine Instructions - L

L (Load)Machine Instruction Code

58 (RX Instruction)



The contents of the field specified as 2nd operand (remains unchanged and) is loaded into the register 1st operand. Examples:Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register1st operand after 2nd operand after L 7,FULL FE.DC.BA.98 00.01.00.00 00.01.00.00 00.01.00.00 L 14,SALVA 00.00.00.11 FF.FF.FF.FD FF.FF.FF.FD FF.FF.FF.FD L 11,=F'125' 00.00.00.00 00.00.00.7D 00.00.00.7D 00.00.00.7D Other examples: L 8,0(10) L 8,0(,11) L 8,0(10,11) L 5,=F'200'

Mach.Inst.Summary


Machine Instructions - LA

LA (Load Address)Machine Instruction Code

41 (RX Instruction)



The instruction computes the 2nd operand address and loads it into the 3 rightmost bytes of register 1st operand. The leftmost byte of register is set ro zero. Example:Suppose the registers with the values shown bellow (for symbol references register 3 is supposed to be the base register for the referenced fileds, and the displacements are just for example purposes; ) register 1st operand before machine instruction register 3 before register 9 before register1st operand after register 3 after register 9 after LA 5,TABLE 01.12.34.56 41.50.3A.C2 00.0B.88.40 not used 00.0B.93.02 00.0B.88.40 not used LA 5,FLD+17 01.12.34.56 41.50.3F.03 00.A0.00.00 not used 00.A0.0F.03 00.A0.00.00 not used LA 5,FLD+17(9) 01.12.34.56 41.59.3F.03 00.A0.00.00 00.00.00.14 00.A0.0F.17 00.A0.00.00 00.00.00.14 LA 5,2(9,3) 01.12.34.56 41.59.30.02 00.A0.00.00 00.00.00.14 00.A0.00.16 00.A0.00.00 00.00.00.14 LA 5,200 01.23.45.67 41.50.00.C8 not used not used 00.00.00.C8 not used not used

Mach.Inst.Summary


Machine Instructions - LA

LA (Load Address)Machine Instruction Code

41 (RX Instruction)



The instruction computes the 2nd operand address and loads it into the 3 rightmost bytes of register 1st operand. The leftmost byte of register is set ro zero. Example:

Suppose the registers with the values shown bellow register 1st operand before machine instruction register 3 before register 9 before register1st operand after register 3 after register 9 after LA 5,4095 01.23.45.67 41.50.0F.FF not used not used 00.00.0F.FF not used not used LA 5,4095(3) 01.23.45.67 41.53.0F.FF 00.0A.80.00 not used 00.0A.8F.FF 00.0A.80.00 not used LA 5,4095(3,9) 01.23.45.67 41.53.9F.FF 00.0A.00.00 00.00.00.01 00.0A.10.00 00.0A.80.00 00.00.00.01

Mach.Inst.Summary


Machine Instructions - LCR

LCR (Load Complement Register)Machine Instruction Code

13 (RR Instruction)



The binary number in the register 2nd operand is complemented and stored into the register 1st operand.If the number is positive, it becomes negative; if it is negative it becomes positive.Example:Suppose the operands with the length and values shown in the “before” line register 1st operand before register 2nd operand before register1st operand after register 2nd operand after LCR 4,5 00.00.00.00 FF.FF.FF.FC 00.00.00.04 FF.FF.FF.FC LCR 4,4 00.00.00.02 00.00.00.02 FF.FF.FF.FE 00.00.00.02

Mach.Inst.Summary


Machine Instructions - LH

LH (Load Halfword)Machine Instruction Code

48 (RX Instruction)



The 2-byte field specified as 2nd operand (remains unchanged and) is loaded into the rightmost 2 bytes of the register 1st operand. The leftmost bit of the storage field is used to fill the leftmost 2 bytes of the register 1st operand: it is expanded / copied to all bits of the first 2 bytes of the register.Example:Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register1st operand after 2nd operand after LH 5,FLD 00.00.00.00 8A.B4 FF.FF.8A.B4 8A.B4 LH 8,HWORD FF.FF.FF.FF 7A.B4 00.00.7A.B4 7A.B4 More examples: LH 7,HALF LH 8,0(10) LH 8,0(,11) LH 8,0(10,11) LH 8,=H'200'

Mach.Inst.Summary


Machine Instructions - LM

LM (Load Multiple)

This instruction works with 3 operands: 1st and 3rd are registers, and 2nd is a storage field. It loads the contents of the storage field 2nd perand into the registers specified as a range by the 1st and 3rd operands. The length of the field depends on how many registers must be loaded. To load 2 registers, the area must have 8 bytes; to load 3 registers, the area must have 12 bytes, and so on.Example: LM 14,1,SAVEAREA

Reg. 14 Reg.15 Reg.0 Reg.1<----------><---------><----------><----------> |------- SAVEAREA ----------------------------|SAVEAREA = 16 bytes (bytes 0-3 = contents loaded into register 14; bytes 4-7 = contents loaded into register 15; bytes 8-11 = contents loaded into register 0; bytes 12-15 = contents loaded into register 1) Another example: LM 1,7,2(10)


98 (RX Instruction)



Mach.Inst.Summary


Machine Instructions - LNR

LNR (Load Negative Register)Machine Instruction Code

11 (RR Instruction)

Condition code 00 Result = 001 Result < 010 Condition code is not set as 10 after LNR11 Condition code is not set as 11 after LNR


The binary number of the 2nd operand is converted to negative and loaded into the register 1st operand. Negative numbers and zero remain unchanged.Example:Suppose the operands with the length and values shown in the “before” line register 1st operand before register 2nd operand before register1st operand after register 2nd operand after LNR 4,5 00.00.00.00 FF.FF.FF.FC FF.FF.FF.FE FF.FF.FF.FC LNR 4,5 00.00.00.02 00.00.00.02 FF.FF.FF.FE 00.00.00.02 LNR 4,8 00.00.00.02 00.00.00.00 00.00.00.00 00.00.00.00

Mach.Inst.Summary


Machine Instructions - LPR

LPR (Load Positive Register)Machine Instruction Code

10 (RR Instruction)

Condition code 00 Result = 001 Condition code is not set as 1 after LPR.10 Result > 011 Overflow


The binary number of the 2nd operand converted to positive and loaded into the register 1st operand. Positive numbers and zero remain unchanged.The overflow occurs when the maximum negative value is converted to positive; in this case, the number remains unchanged. Examples:Suppose the operands with the length and values shown in the “before” line register 1st operand before register 2nd operand before register1st operand after register 2nd operand after LPR 4,5 00.00.00.00 FF.FF.FF.FC 00.00.00.04 FF.FF.FF.FC LPR 4,5 00.00.00.02 00.00.00.02 00.00.00.02 00.00.00.02 LPR 4,8 00.00.00.FF 00.00.00.00 00.00.00.00 00.00.00.00

Mach.Inst.Summary


Machine Instructions - LR

LR (Load Register)Machine Instruction Code

18 (RR Instruction)



The contents of the register 2nd operand is loaded into the register 1st operand. Example:Suppose the operands with the length and values shown in the “before” line register 1st operand before register 2nd operand before register1st operand after register 2nd operand after LR 4,5 00.00.00.00 FF.FF.FF.FC FF.FF.FF.FC FF.FF.FF.FC LR 4,5 00.00.12.34 00.00.00.02 00.00.00.02 00.00.00.02 LR 4,8 00.00.00.02 00.00.00.00 00.00.00.00 00.00.00.00

Mach.Inst.Summary


Machine Instructions - LTR

LTR (Load and Test Register)Machine Instruction Code

12 (RR Instruction)

Condition code 00 Result = 001 Result < 010 Result > 011 Condition code is not set as 11 after LTR


The contents of register 2nd operand is loaded into the register 1st operand; the condition code is set according to the number loaded. Example:Suppose the operands with the length and values shown in the “before” line register 1st operand before register 2nd operand before register1st operand after register 2nd operand after LTR 4,5 00.00.00.00 FF.FF.FF.FC FF.FF.FF.FC FF.FF.FF.FC LTR 4,5 00.00.12.34 00.00.00.02 00.00.00.02 00.00.00.02 LTR 4,8 00.00.00.02 00.00.00.00 00.00.00.00 00.00.00.00

Mach.Inst.Summary


Machine Instructions - M

M (Multiply)Machine Instruction Code

5C (RX Instruction)



This instruction multiplies two binary numbers. Register 1st operand must be an even register. The odd register following it must contain the multiplicand.The 2nd operand storage field must contain the multiplier.The result is a 64-bit fixed-point binary number stored into the pair of even-odd registers (specified by the 1st operand). Examples: Register 6 before Register 7 before 2nd operand before Register 6 after Register 7 after 2nd operand after M 6,FLDA [ Multiplicand: Register 7; Multiplier: FLDA; Result: Registers 6 and 7 together ] 00.00.00.00 00.00.00.0A 00.00.00.02 00.00.00.00 00.00.00.14 00.00.00.02 M 6,=F'256' Multiplicand: Register 7; Multiplier: 256; Result: Registers 6 and 7 together 00.00.00.00 00.00.04.00 00.00.00.FF 00.00.00.00 00.03.FC.00 00.00.00.FF M 6,4(2,8) Multiplicand: Register 7; Multiplier address: Index reg 2 + Base reg 8 + X’4’;

Result: Registers 6 and 7 together 00.00.00.00 00.00.04.00 00.00.01.0A 00.00.00.00 00.04.28.00 00.00.01.0A

Mach.Inst.Summary


More examples:

Register 6 before Register 7 before 2nd operand before Register 6 after Register 7 after 2nd operand after M 6,4(2) Multiplicand: Register 7; Multiplier address: Reg index 2 [ + Reg base 0 ] + X’4’;

Result: Registers 6 and 7 together 00.00.00.00 00.00.00.0C 00.00.00.02 00.00.00.00 00.00.00.18 00.00.00.02 M 6,FLD+4(1) Multiplicand: Reg 7; Multiplier address: Reg index 1 + Base register of FLD+4

+ Displacement of FLD+4 + X’4’; Result: Registers 6 and 7 together 00.00.00.00 00.00.AA.AA 00.11.22.33 00.00.00.0B 6C.16.93.DE 00.11.22.33

Machine Instructions - M

M (Multiply)Machine Instruction Code

5C (RX Instruction)



Mach.Inst.Summary


Machine Instructions - MC

MC (Monitor Call)Machine Instruction Code

AF (SI Instruction)



This instruction causes a program interruption if the bit that controls this event is ON in the control register.The control register mask bits are the bits 16-31, end they correspond to the classes 0-15 respectively.The leftmost 4 bits of 2nd operand (immediate) must be zero.The rightmost 4 bits of 2nd operand specify abinary number indicating the desired interruption class.If the corresponding bit in the control register 8is ON, interruption will occur.The 2nd operand address is not a storage address; it is a code to be stored at the storage address X'000156'.If the mask referred to the desired interruption is OFF in the control register 8, instruction processes as a NOP (no operation).

Example: MC MONITCOD,7

Mach.Inst.Summary


Machine Instructions - MH

MH (Multiply Halfword)Machine Instruction Code

4C (RX Instruction)



This instruction multiplies two binary numbers. Register 1st operand must have the multiplicand. The 2nd operand 2-byte storage field must contain the multiplier.The result is a 32-bit fixed-point binary number stored into the register 1st operand. Example:Note that if an overflow occurs (this event is NOT indicated in the condition code) the result sign may not be correct. If result = zero, sign is same as positive number. Examples: Register 1st operand before 2nd operand before Register 1st operand after 2nd operand after MH 5,=H'4' [ Multiplicand: Register 5; Multiplier: literal 4; Result: Register 5 ] 00.00.00.0A 00.04 00.00.00.28 00.04 MH 5,=F'2' Multiplicand: Register 5; Multiplier: 0 [ left half of the fullword is taken as the

halfword 2nd operand] ; Result: Register 5 00.00.04.00 00.00 [TAKE CARE! right half with 00.02 not taken! ] 00.00.00.00 00.00

Mach.Inst.Summary


Machine Instructions - MP

MP (Multiply Packed)Machine Instruction Code

FC (SS Instruction – L1 e L2)


Possible Interruptions 0001,0004,0005,0006,0007

This instruction multiplies two decimal packed numbers, both in storage fields. The result is stored in the 1st operand.2nd operand can be up to 8 bytes.2nd operand length must be less than the length of the 1st operand.If 2nd operand length is greater than or equal to the length of the 1st operand, an interruption will occur (code 0006).1st operand must have as many zero leftmost digits as many digits the 2nd operand has. If it doesn’t happen, interruption 0007 will occur. Example: MP FLDA,FLDB 1st operand before 2nd operand before 1st operand after 2nd operand after 00.09.99.9C 99.9C 99.89.00.1C 99.9C

00.19.99.9C 99.9C 00.19.99.9C 99.9C (Error! FLDA must have at least 3 leftmost digits with zero)

Mach.Inst.Summary


Machine Instructions - MR

MR (Multiply Register)Machine Instruction Code

1C (RR Instruction)



This instruction multiplies two binary numbers, both in registers. Register 1st operand must be an even register (its contents is not considered in the operation, unless it is [also] the multiplier). The odd register following it must contain the multiplicand.The 2nd operand register must contain the multiplier.The result is a 64-bit fixed-point binary number stored into the pair of even-odd registers (specified by the 1st operand). Example:

Register 6 before Register 7 before Register 9 before Register 6 after Register 7 after Register 9 after MR 6,9 [ Multiplicand: Register 7; Multiplier: register 9; Result: Registers 6 and 7 together ] 00.00.00.00 00.00.00.0A 00.00.00.02 00.00.00.00 00.00.00.14 00.00.00.02 MR 6,9 [ Multiplicand: Register 7; Multiplier: register 9; Result: Registers 6 and 7 together ] 00.00.00.00 99.AA.BB.CC 00.FF.FF.FF 00.99.AA.BB 32.55.44.34 00.FF.FF.FF

Mach.Inst.Summary


Machine Instructions - MVC

MVC (MoVe Character)Machine Instruction Code

D2 (SS Instruction - L)



This instruction moves (copies) the contents of stotage field to another storage field.The move is done left to right, each byte at a time. Example: MVC FLDA,FLDB before afterFLDB C1.C2.C3 C1.C2.C3FLDA C4.C5.C6 C1.C2.C3The sending field is the 2nd operand and remains unchanged (unless part of it is at the same time the receiving field = overlapping). The receiving field is the 1st operand. The quantity of bytes moved is determined by the 1st operand length, and both operands are treated with this same length. Examples:Suppose the operands with the length and values shown in the “before” line 1st operand before 2nd operand before 1st operand after 2nd operand after MVC WA+5(3),WR+2 40.40.40 E5.C1.D3 E5.C1.D3 E5.C1.D3 MVC WOUT,WIN 00.00.00.00.00 00.00.00.00.1C 00.00.00.00.1C 00.00.00.00.1C MVC NICKNAM,=C'SMAIL' C3.D9.E8.40.40 E2.D4.C1.C9.D3 E2.D4.C1.C9.D3 E2.D4.C1.C9.D3

Mach.Inst.Summary







Mach.Inst.Summary

More examples:

Move spaces using an auxiliary 5-byte field (a 5-byte literal) :Suppose the operands with the length and values shown in the “before” line 1st operand before 2nd operand before 1st operand after 2nd operand after MVC WA(5),=CL5' ' 5C.5C.5C.5C.5C 40.40.40.40.40 40.40.40.40.40 40.40.40.40.40

Alternatively, one may propagate spaces using na auxiliary 1-byte area (the literal) ! - The first MVC moves space to the leftmost byte of WA.- The second one moves 4 bytes; remember that MVC operates one byte at a time.- Follow the 4-byte move, one at a time: The 1st byte is moved to the 2nd; The 2nd to the 3rd; The 3rd byte to the 4th; The 4th byte to the 5th.

Initial MVC for the leftmost byte: MVC WA(1),=C' ' 5C.??.??.??.?? 40 before 40.??.??.??.?? 40 after







Mach.Inst.Summary

Propagation from 1st to 2nd, from 2nd to 3rd, from 3rd to 4th and from 4th to 5th MVC WA+1(4),WA Follow MVC one byte at a time :

1st byte move: 40.??.??.??.?? 40.??.??.??.?? 40.40.??.??.?? 40.40.??.??.??

2nd byte move : 40.40.??.??.?? 40.40.??.??.?? 40.40.40.??.?? 40.40.40.??.??

3rd byte move : 40.40.40.??.?? 40.40.40.??.?? 40.40.40.40.?? 40.40.40.40.??

4th byte move : 40.40.40.40.?? 40.40.40.40.?? 40.40.40.40.40 40.40.40.40.40

Or, better yet:

1st move: 40.??.??.??.?? Before

40.40.??.??.?? After

2nd move: 40.40.??.??.?? Before

40.40.40.??.?? After

3rd move: 40.40.40.??.?? Before

40.40.40.40.?? After

4th move: 40.40.40.40.?? Before

40.40.40.40.40 After


Machine Instructions - MVCIN

MVCIN (MoVe Character Inverted)Machine Instruction Code

E8 (SS Instruction – L)



This instruction moves (copies) the contents of the 2nd operand to the 1st operand (both are storage fields) in an inverted sequence.Note that the 1st operand address is its leftmost byte, and the 2nd operand address is its rightmost byte.Move is done each byte at a time.From the sending field’s view its from right to left.From the receiving field’s view its from left to right.If occurs any overlay (superposition), results are unpredictable.Example:Suppose the operands with the length and values shown in the “before” line 1st operand before 2nd operand before 1st operand after 2nd operand after MVCIN A(3),B+2 C4.C5.C6 C1.C2.C3 C3.C2.C1 C1.C2.C3 MVCIN A(5),BETA C4.C5.C6.C7.C8 C1.C2.C3.C4.C5 C5.C4.C3.C2.C1 C1.C2.C3.C4.C5

Mach.Inst.Summary


Machine Instructions - MVCL

MVCL (MoVe Character Long)Machine Instruction Code

0E (RR Instruction)

Condition code 00 Length of 1st operand is equal to length of 2nd operand01 Length of 1st operand is less than length of 2nd operand10 Length of 1st operand is greater than length of 2nd operand11 Move not executed


Both 1st and 2nd operands must be even registers. They indicate a couple of (even-odd) registers, herein dubbed R1st, R1st+1, R2nd and R2nd+1 This instruction move a storage field (sending field) to another storage field (receiving field), each byte at a time, left to right.Receiving field address must be in the 3 rightmost bytes of R1st.Sending field address must be in the 3 rightmost bytes of R2nd.Receiving field length must be in the 3 rightmost bytes of R1st+1.Sending field length must be in the 3 rightmost bytes of R2nd+1.The leftmost byte of R2nd+1 must contain the padding character.The leftmost byte of R1st is ignored. Same happens with leftmost byte of R1st+1 and leftmost byte of R2nd.Example: MVCL 2,8See details on following slide.

Mach.Inst.Summary




0E (RR Instruction)



L 2,=A(RECEIVE) L 3,=A(L’RECEIVE) L 8,=A(SENDING) L 9,=A(L’SENDING) ICM 9,B'1000',=C'*' MVCL 2,8If sending field wraps from byte 16.777.215 to byte 0 (or not), move is executed this way:· The move is executed while the receiving field’s leftmost byte is the same or it’s at the left of the leftmost byte of the sending field OR the move is executed while the receiving field’s leftmost byte is at the right of the rightmost byte of the sending field.· The move is executed while the receiving field’s leftmost byte is the same or is at the left of the leftmost byte of the sending field AND the receiving field’s leftmost byte is at the right of the rightmost byte of the sending field.

The (address of the) rightmost byte of the sending field is computed using the length of the receiving or sending field (the smaller).

Mach.Inst.Summary




0E (RR Instruction)



After move:- The 3 rightmost bytes of R1st+1 (previously with the receiving field length) are set to zero (in fact, at each byte moved, it’s decremented by 1; , it is the amount of remaining bytes to move; at the end of operation remaining bytes to move = zero). To the 3 rightmost bytes of R1st (previously with the receiving field address) is added the length originally specified in R1st+1 (in fact, at each byte moved, it’s incremented by 1 = next receiving byte address). From the 3 rightmost bytes of R2nd+1 (originally with the sending field length) is subtracted the amount of moved bytes (in fact at each byte move it is decremented by 1, it is the amount of remaining bytes to move; at the end remaining bytes to move = zero)- To the 3 rightmost bytes of R2nd (previously with sending field address) it is added the number of bytes moved from sending to receiving field (in fact, at each byte moved, it’s incremented by 1 = next sending byte address) Leftmost R1st byte and leftmost R2nd byte are set to zero, even if move is not done.- Leftmost R1st+1 byte and leftmost R2nd+1 byte remain unchanged.

Mach.Inst.Summary


Machine Instructions - MVI

MVI (MoVe Immediate)Machine Instruction Code

92 (SI Instruction)



This instruction moves (copies) a constant 1-byte storage field (2nd operand – immediate operand) to another storage 1-byte field.2nd operand (mmediate operand) is the sending field and 1st operand is the receiving field.Examples: MVI FLDA,C'*' or MVI FLDA,X'5C' or MVI FLDA,B'01011100' or MVI FLDA,92

FLDA before Immediate operand before FLDA after Immediate operand after 12 5C 5C 5C

Other examples: MVI WAREA+72,C'/' MVI 0(4),X'80'

Mach.Inst.Summary


Machine Instructions - MVN

MVN (MoVe Numerics)Machine Instruction Code




This instruction is similar to MVC, but it moves onle the right half of the bytes.Example:Suppose the operands with the length and values shown in the “before” line 1st operand before 2nd operand before 1st operand after 2nd operand after MVN FLDA,FLB 12.34.56 78.9A.BC 18.3A.5C 78.9A.BC MVN TOT+4(1),=X'0C' 00.12.30.00.2F 0C 00.12.30.00.2C 0C

Mach.Inst.Summary


Machine Instructions - MVO

MVO (MoVe with Offset)Machine Instruction Code




The MVO instruction moves the contents of the 2nd operand storage field to the 1st operand storage field, from righ to left, with displacement of half byte: the right half of the receveing field rightmost byte remains unchanged. The right half of the rightmost byte of sending field is sent to the left half of the rightmost byte of receiving field. And so on.If 1st operand isn’t large enough to receive all digits sent from the 1st operand, the leftmost half-bytes are truncated. If 1st operand is larger than enough to receive all digits sent from the 1st operand, the leftmost half-bytes are filled with X’0’. Examples: MVO RECFLD,SENFLD

SENFLD Before 00.00.12.00 SENFLD After 00.00.12.00

RECFLD Before 00.00.00.0C RECFLD After 00.01.20.0C

Mach.Inst.Summary


Machine Instructions - MVO

MVO (MoVe with Offset)Machine Instruction Code




MVO CPOA,CPOB Before After 1º Case CPOB 12.34.56 12.34.56 CPOA 78.9A 45.6A2º Case CPOB AB.72 AB.72 CPOA 4A.5C.B9.FC 00.0A.B7.2C Other examples: MVO ARCALC(5),ARCALC(4) MVO 0(4,7),ARCALC MVO AREA,2(5,8) MVO 2(7,13),19(5,15)

Mach.Inst.Summary


Machine Instructions - MVZ

MVZ (MoVe Zones)Machine Instruction Code




The MVZ instruction is similar to the MVC, but it moves onle the left half of the bytes. Examples:Suppose the operands with the length and values shown in the “before” line 1st operand before 2nd operand before 1st operand after 2nd operand after MVZ FLDA,FLB 12.34.56 78.9A.BC 72.94.B6 78.9A.BC MVZ TOT,=4C'0' 01.02.03.04.C5 F0.F0.F0.F0.F0 F1.F2.F3.F4.F5 F0.F0.F0.F0.F0

Mach.Inst.Summary


Machine Instructions - N

N ([boolean] aNd)Machine Instruction Code

54 (RX Instruction)

Condition code 00 Result = 001 Result <> 010 Condition code is not set as 10 after N11 Condition code is not set as 11 after N


This instruction executes a boolean AND between a register (1st operand) and a 4-byte storage field (2nd operand).Mask bit =0 then result bit = 0; mask bit = 1 then reault bit = remain unchangedExample: N 13,FIELDX Before AfterRegister 13 B4.EF.2F.A8 00.00.00.A8FIELDX 00.00.00.FF 00.00.00.FFOther examples: N 11,=F'15' N 3,0(4) N 3,0(,4) N 3,0(8,4)

Mach.Inst.Summary


Machine Instructions - NC

NC ([boolean] aNd Character)Machine Instruction Code


Condition code 00 Result = 001 Result <> 010 Condition code is not set as 10 after NC11 Condition code is not set as 11 after NC

Possible Interruptions 0004, 0005

This instruction executes a boolean AND between 2 storage fields (1st and 2nd operands). Mask bit =0 then result bit = 0; mask bit = 1 then reault bit = remain unchanged

Example:

NC FLDA,FLDB Before After FLDA EF.2F.A8 00.00.A8FLDB 00.00.FF 00.00.FF

Mach.Inst.Summary


Machine Instructions - NI

NI ([boolean] aNd [with] Immediate [operand])Machine Instruction Code

94 (SI Instruction)

Condition code 00 Result = 001 Result <> 010 Condition code is not set as 10 after NI11 Condition code is not set as 11 after NI


This instruction executes a boolean AND between 2 storage fields (1 byte each; 1st operand = field specified using its address; 2nd operand = immediate field, it’s the 2nd byte of the instruction). Mask bit =0 then result bit = 0; mask bit = 1 then reault bit = remain unchanged Example: NI BYTE,X'0F' Before AfterBYTE B4 04Immediate Op. 0F 0F

Mach.Inst.Summary


Machine Instructions - NR

NR ([boolean] aNd Register)Machine Instruction Code

14 (RR Instruction)

Condition code 00 Result = 001 Result <> 010 Condition code is not set as 10 after NR11 Condition code is not set as 11 after NR


This instruction executes a boolean AND between 2 registers.Mask bit =0 then result bit = 0; mask bit = 1 then reault bit = remain unchangedExample: NR 5,8 Before AfterRegister 5 B4.EF.2F.A8 00.00.00.A8Register 8 00.00.00.FF 00.00.00.FF

Mach.Inst.Summary


Machine Instructions - O

O ([boolean] Or)Machine Instruction Code

56 (RX Instruction)

Condition code 00 Result = 001 Result <> 010 Condition code is not set as 10 after O11 Condition code is not set as 11 after O


This instruction executes a boolean OR between a register (1st operand) and a 4-byte storage field (2nd operand).Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = 1

Example: O 13,FIELDF

Before After

Register 13 B4.EF.2F.A8 B4.EF.2F.FFFIELDF 00.00.00.FF 00.00.00.FF

Mach.Inst.Summary


Machine Instructions - OC

OC ([boolean] Or Character)Machine Instruction Code


Condition code 00 Result = 001 Result <> 010 Condition code is not set as 10 after OC11 Condition code is not set as 11 after OC


This instruction executes a boolean OR between 2 storage fields (1st and 2nd operands). Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = 1Example: OC FLDA,FLDB Before After FLDA EF.2F.A8 EF.2F.FFFLDB 00.00.FF 00.00.FF

Mach.Inst.Summary


Machine Instructions - OI

OI ([boolean] Or [with] Immediate [operand])Machine Instruction Code

96 (SI Instruction)

Condition code 00 Result = 001 Result <> 010 Condition code is not set as 10 after OI11 Condition code is not set as 11 after OI


This instruction executes a boolean OR between 2 storage fields (1 byte each; 1st operand = field specified using its address; 2nd operand = immediate field, it’s the 2nd byte of the instruction). Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = 1Example: OI BYTE,X'0F' Before After BYTE B4 BF Immediate Operand 0F 0F

Mach.Inst.Summary


Machine Instructions - OR

OR ([boolean] Or Register)Machine Instruction Code

16 (RR Instruction)

Condition code 00 Result = 001 Result <> 010 Condition code is not set as 10 after OR11 Condition code is not set as 11 after OR


This instruction executes a boolean OR between 2 registers.Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = 1Example: OR 5,8 Before After Reg. 5 B4.EF.2F.A8 B4.EF.2F.FFReg. 8 00.00.00.FF 00.00.00.FF

Mach.Inst.Summary


Machine Instructions - PACK

PACKMachine Instruction Code




The PACK instruction moves a storage zoned field to a storage packed field. The intended function is to convert a numeric field from zoned format to packed format. NO validation is done in the sending field; if its contents is not a valid decimal zoned number, the operation flows normally.1st operand is the receiving field and 2nd operand is the sending field. The operation is done from right to left.The two halves of the rightmost byte of the sending field are inverted and moved to the rightmost byte of the receiving field.After that, each right half byte of the sending field is sent to a half of the receiving field. 2nd operand remains unchanged.If the receiving field is smaller than needed to fit all digits from the sending field, the leftmost digits are truncated.If the receiving field is greater than needed to fit all digits from sending field, the remaining left digits are filled with X’0’.Example: PACK FLDA,FLDB Before After FLDB F1.F2.F3.F4 F1.F2.F3.F4 FLDA 00.B7.2A 01.23.4F

Mach.Inst.Summary


Machine Instructions - PACK

PACKMachine Instruction Code




PACK FLDA,FLDB2ºcase FLDB F1.F2.F3.F4 F1.F2.F3.F4 FLDA C9.4A 23.4F3ºcase FLDB 9A.48.F9.DB 9A.48.F9.DB FLDA 19.B7.DF 0A.89.BDNote the 3rd case. The sending field is not validated about being zoned. The receiving field may not become a valid decimal packed field. More examples: PACK VALUE,READAREA+5(9) PACK HOWMUCH+2(7),2(8,5) PACK 0(10,2),AREA PACK 2(5,7),2(3,8) PACK DOUBLE,DOUBLE PACK BYTE,BYTE

Mach.Inst.Summary


Machine Instructions - S

S (Subtract)Machine Instruction Code

5B (RX Instruction)



Instruction S subtracts algebraically the binary number in the 4-byte storage field 2nd operand from the bynary number of the register 1st operand. Result is stored into 1st operand register. Examples:Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after S 5,=F'259' 00.00.BF.D2 00.00.01.03 00.00.BE.CF 00.00.01.03 S 7,FULL 00.00.00.0D 00.00.01.03 FF.FF.FF.0A 00.00.01.03 S 7,4(2,8) 07.FF.FF.FE 00.00.00.01 07.FF.FF.FD 00.00.00.01 S 7,4(2) 07.FF.FF.FF 00.00.00.02 07.FF.FF.FD 00.00.00.02 S 7,4(,8) 00.00.00.00 FF.FF.FF.FF 00.00.00.01 FF.FF.FF.FF

Mach.Inst.Summary


Machine Instructions - SH

SH (Subtract Halfword)Machine Instruction Code

4B (RX Instruction)



Instruction SH subtracts algebraically the binary number in the 2-byte storage field 2nd operand from the bynary number of the register 1st operand. Result is stored into 1st operand register. Examples:Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after SH 5,=H'259' 00.00.2B.C4 01.03 00.00.2A.C1 01.03 SH 5,HALF 00.00.00.0D 01.0D FF.FF.FF.00 01.0D SH 5,4(2,8) 11.11.11.11 (decimal 286331153) 88.88 (decimal –30584) 11.11.88.89 (decimal 286361737) 88.88 SH 5,4(2) 11.11.11.11 (decimal 286331153) 78.88 (decimal +30856) 11.10.98.89 (decimal 286300297) 78.88

Mach.Inst.Summary


Machine Instructions - SL

SL (Subtract Logical)Machine Instruction Code

5F (RX Instruction)

Condition code 00 Condition code is not set as 00 after SL01 Result <> 0, sign not lost10 Result = 0, sign lost11 Result <> 0, sign lost


Instruction S subtracts logically the binary number in the 4-byte storage field 2nd operand from the binary number of the register 1st operand. Result is stored into 1st operand register. Examples:Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after SL 5,=F'259' 00.00.BF.D2 00.00.01.03 00.00.BE.CF 00.00.01.03 SL 7,FULL 00.00.00.0D 00.00.00.03 00.00.00.0A 00.00.00.03 SL 7,4(2,8) 07.FF.FF.FE 00.00.00.01 07.FF.FF.FD 00.00.00.01 SL 7,4(2) 07.FF.FF.FF 00.00.00.02 07.FF.FF.FD 00.00.00.02

Mach.Inst.Summary


Machine Instructions - SLA

SLA (Shift Left Algebraic)Machine Instruction Code

8B (RS Instruction)



This instruction shifts algebraically, to the left, the bits of the register 1st operand. The sign bit remains unchanged, and the other 31 bits are shifted.The “new” bits to the right are set to zero.It’s an RS instruction, and its bits 12-15 are ignored.The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 15. Example: SLA 5,3Register 5 before Shift FF.80.9A.00Register 5 after Shift FC.04.D0.00

Mach.Inst.Summary


Machine Instructions SLDA

SLDA (Shift Left Double Algebraic)Machine Instruction Code

8F (RS Instruction)



The register specified as 1st operand indicates the a pair of registers (R1st and R1st+1), taken as a number with 64-bit (1 bit = sign; 63 bits = number).This instruction shifts algebraically, to the left, the bits of the number inside the 2 registers (both treated as only onr number).The sign bit remains unchanged, and the other 63 bits are shifted.The “new” bits to the right are set to zero.It’s an RS instruction, and its bits 12-15 are ignored.The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 63. Example: SLDA 8,3Registers 8 and 9 before Shift 00.00.00.00 FF.80.9A.00Registers 8 and 9 after Shift 00.00.00.07 FC.04.D0.00

Mach.Inst.Summary


Machine Instructions - SLDL

SLDL (Shift Left Double Logical)Machine Instruction Code

8D (RS Instruction)



The register specified as 1st operand indicates a pair of registers (R1st and R1st+1), taken as a number with 64-bit.This instruction shifts logically, to the left, the bits of the number inside the 2 registers (both treated as only onr number).All 64 bits are shifted (including sign bit). The “new” bits to the right are set to zero.It’s an RS instruction, and its bits 12-15 are ignored.The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 63. Example: SLDL 8,4Registers 8 and 9 before Shift 12.FE.3D.4C 5B.6A.78.90 8 9Registers 8 and 9 after Shift 2F.E3.D4.C5 B6.A7.89.00 8 9

Mach.Inst.Summary


Machine Instructions - SLL

SLL (Shift Left Logical)Machine Instruction Code

89 (RS Instruction)



The register specified as 1st operand indicates a register, taken as a 32-bit number.This instruction shifts logically, to the left, the bits of the number inside the register.All 32 bits are shifted (including sign bit). The “new” bits to the right are set to zero.It’s an RS instruction, and its bits 12-15 are ignored.The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 32. Example: SLL 5,2

Register 5 before Shift B9.4F.FF.FF

Register 5 after Shift E5.3F.FF.FC

Mach.Inst.Summary


Machine Instructions - SLR

SLR (Subtract Logical Register)Machine Instruction Code

1F (RR Instruction)

Condition code 00 Condition code is not set as 00 after SLR01 Result <> 0, sign not lost10 Result = 0, sign lost11 Result <> 0, sign lost


Instruction SLR subtracts logically the binary number in the register 2nd operand from the binary number in the register 1st operand.Result is stored into 1st operand register. Example:Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after SLR 7,12 00.B0.C4.E2 00.00.00.01 00.B0.C4.E1 00.00.00.01 SLR 10,11 80.00.00.00 00.00.00.01 7F.FF.FF.FF 00.00.00.01

Mach.Inst.Summary


Machine Instructions - SP

SP (Subtract Packed)Machine Instruction Code

FB (SS Instruction – L1 e L2)



This instruction subtracts the contents of the 2nd operand from the contents of the 1st operand.Both must be storage fields in the decimal packed format.Result is stored into 1st operand field. Examples: SP FLDA,FLDB Before AfterFLDB 98.7C 98.7CFLDA 12.34.5C 11.35.8CMore examples: SP VALUE,VALUE SP TOTAL,=P'1' SP AE+5(8),AE+15(3) SP 0(2,7),4(1,8)

Mach.Inst.Summary


Machine Instructions - SPM

SPM (Set Program Mask)Machine Instruction Code

04 (RR Instruction)

Condition code Is set with the contents of bits 2 and 3 of register 1st operand


This is RR instruction. Its bits 12-15 are not considered.The contents of 1st operand register is used to take the values of condition code and program mask to store them into PSW.The value of bits 2-3 are set to the condition code.The value of bits 4,5,6 and 7 are set to the PSW program mask.The bits 0-1 and 8-31 are ignored.Example:

SPM 8

Mach.Inst.Summary


Machine Instructions - SR

SR (Subtract Register)Machine Instruction Code

1B (RR Instruction)



This instruction subtracts the contents of the register 2nd operand from the contents of the register 1st operand. Result is stored into register 1st operand.Then: Minuend : 1st operand ; Subtrahend : 2nd operand ; Result : 1st operandExamples:Suppose the operands with the length and values shown in the “before” line Register 1st operand before Register 2nd operand before Register 1st operand after Register 2nd operand after SR 7,8 00.00.FF.FF 00.00.00.01 00.00.FF.FE 00.00.00.01 SR 2,2 00.00.FF.FF 00.00.FF.FF 00.00.00.00 00.00.00.00

Mach.Inst.Summary


Machine Instructions - SRA

SRA (Shift Right Algebraic)Machine Instruction Code

8A (RS Instruction)

Condition code 00 Result = 001 Result < 010 Result > 011 Condition code is not set as 11 after SRA


This instruction shifts algebraically, to the right, the bits of the register 1st operand. The sign bit remains unchanged, and the other 31 bits are shifted.The “new” bits to the right are set to zero.It’s an RS instruction, and its bits 12-15 are ignored.The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 15. Example: SRA 5,3Register 5 before Shift FF.80.0A.00Register 5 after Shift 8F.F0.01.40

Mach.Inst.Summary


Machine Instructions - SRDA

SRDA (Shift Right Double Algebraic)Machine Instruction Code

8E (RS Instruction)

Condition code 00 Result = 001 Result < 010 Result > 011 Condition code is not set as 11 after SRDA


The register specified as 1st operand indicates the a pair of registers (R1st and R1st+1), taken as a number with 64-bit (1 bit = sign; 63 bits = number).This instruction shifts algebraically, to the right, the bits of the number inside the 2 registers (both treated as only one number).The sign bit remains unchanged, and the other 63 bits are shifted.The “new” bits to the left are set to zero.It’s an RS instruction, and its bits 12-15 are ignored.The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 63. Example: SRDA 8,4Registers 8 and 9 before Shift 04.20.08.91 C4.00.02.FFRegisters 8 and 9 after Shift 00.42.00.89 1C.40.00.2F

Mach.Inst.Summary


Machine Instructions - SRDL

SRDL (Shift Right Double Logical)Machine Instruction Code

8C (RS Instruction)



The register specified as 1st operand indicates the a pair of registers (R1st and R1st+1), taken as a number with 64-bit.This instruction shifts logically, to the right, the bits of the number inside the 2 registers (both treated as only onr number).All 64 bits are shifted (including sign bit). The “new” bits to the left are set to zero.It’s an RS instruction, and its bits 12-15 are ignored.The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 63. Example: SRDL 8,4Registers 8 and 9 before Shift 12.FE.3D.4C 5B.6A.78.90 8 9Registers 8 and 9 after Shift 01.2F.E3.D4 C5.B6.A7.89 8 9

Mach.Inst.Summary


Machine Instructions - SRL

SRL (Shift Right Logical)

The register specified as 1st operand indicates a register, taken as a 32-bit number.This instruction shifts logically, to the right, the bits of the number inside the register.All 32 bits are shifted (including sign bit). The “new” bits to the left are set to zero.It’s an RS instruction, and its bits 12-15 are ignored.The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 32. Example:

SRL 5,2Register 5 before Shift B9.4F.FF.FF Register 5 after Shift 2E.53.FF.FF


88 (RS Instruction)



Mach.Inst.Summary


Machine Instructions - SRP

SRP (Shift and Round Packed)Machine Instruction Code

F0 (SS Instruction)



This is a SS instruction, and its format is the following: 1 byte = operation code1/2 byte = L1 = 1st operand length - 11/2 byte = I3 = 3rd operand (immediate operand)2 bytes = 1st operand base+displacement address2 bytes = 2nd operand base+displacement address The 1st operand is a decimal packed storage field; it is shifted based upon the information provided by the 2nd operand: the sense of shift and the amount of digits to be shifted.If shift is to be done rightwards the number is rounded accordingly 3rd operand.

Mach.Inst.Summary




F0 (SS Instruction)



The 6 rightmost bits of the number computed as the “address” of 2nd operand are analysed this way:Leftmost bit indicates the sense of the shift: OFF means shift leftwards; ON means rightwards. The number composed by the remaining 5 bits indicates the amount of digits to be shifted (if shift rightwards, this number is negative). The round is done by adding the number specified in the 3rd operand to the last shifted digit and, if it is 1, it is added to the number-result after shift. See the following examples:

Mach.Inst.Summary




F0 (SS Instruction)



SRP TOTAL,61,5 TOTAL Before 12.34.56.78.9C TOTAL After 00.01.23.45.7C

(shifts 3 digits to the right)

SRP TOTAL,3,0 TOTAL Before 12.34.56.78.9C TOTAL After 45.67.89.00.0C

(shifts 3 digits to the left)

These rules make it easier to specify shift sense and amount of digits:Shift leftwards = specify directly the amount of digits SRP TOTAL,3,5 Specify amount in the 2nd operand = shifts “amount” digits to the left

(in the example = 3)

Shift rightwards = specify (64 – amount of digits) SRP TOTAL,64-3,5 Specify [64-amount] in the 2nd operand = shifts “amount” digits to the right

(In the example = 3)

Mach.Inst.Summary


Machine Instructions - ST

ST (Store [from register to storage])Machine Instruction Code

50 (RX Instruction)



The register 1st operand (remain unchanged and) is stored into the 2nd operand 4-byte storage field. Examples:Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register1st operand after 2nd operand after ST 7,FULL FE.DC.BA.98 00.01.00.00 FE.DC.BA.98 FE.DC.BA.98 ST 14,SAVE 00.00.00.11 FF.FF.FF.FD 00.00.00.11 00.00.00.11 Other examples: ST 14,FULL+4 ST 14,0(2) ST 14,0(,8)

Mach.Inst.Summary


Machine Instructions - STC

STC (STore Character)Machine Instruction Code

42 (RX Instruction)



The rightmost byte of register 1st operand (remain unchanged and) is stored into the 2nd operand 1-byte storage field. Examples:Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register1st operand after 2nd operand after STC 7,BYTE FE.DC.BA.98 00 FE.DC.BA.98 98 STC 14,0(5) 00.00.00.11 FF 00.00.00.11 11

Mach.Inst.Summary


Machine Instructions - STCK

STCK (STore ClocK)Machine Instruction Code

B205 (Instrução S)

Condition code 00 Clock status allows set01 Clock status does not allow set10 Clock status is error11 Condition code is not set as 11 after STCK


TOD clock contents is stored into the 8-byte storage field specified in the 2nd operand. Clock must be is set, stop or no-set state.The rightmost bytes are set to zero.If TOD clock is in error state, contents stored is unpredictable. If TOD clock is not operational, all bytes are set to zero.Example: STCK DW

Mach.Inst.Summary


Machine Instructions - STCM

STCM (STore Character under Mask)Machine Instruction Code

BE (RS Instruction)



The format of this instruction is:1st byte: X’BE’ (operation code); 2nd byte, left half : 1st operand register ; 2nd byte, right half : 3rd operand (mask); 3rd and 4th bytes : 2nd operand address, base+displacement format. The 4 bits in the mask correspond to the 4 bytes of the 1st operand register.The storage field specified in the 2nd operand must have as many bytes as the ON bits in the mask. The register 1st operand bytes corresponding to the ON bits of the mask are stored into the 2nd operand storage bytes (taken as a contiguous field).1st operand remains unchanged. Example:Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register1st operand after 2nd operand after STCM 5,B’1010’,TWOBYTES 00.00.45.67 9A.BC 00.00.45.67 00.45

1st byte of register 5 is stored into byte TWOBYTES and 3rd byte of register 5 is stored into byte TWOBYTES+1

Mach.Inst.Summary


Machine Instructions - STH

STH (STore Halfword)Machine Instruction Code

40 (RX Instruction)



The rightmost 2 bytes of register 1st operand (remain unchanged and) are stored into the 2nd operand 2-byte storage field. Example:Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register1st operand after 2nd operand after STH 5,FLD 00.00.00.0A 8A.B4 00.00.00.0A 00.0A STH 8,HWORD FF.FF.FF.FF FF.FF FF.FF.FF.FF FF.FFOther examples: STH 14,SAVE+18 STH 14,0(2) STH 14,0(,8) STH 14,0(2,8) STH 0,FLD

Mach.Inst.Summary


Machine Instructions - STM

STM (STore Multiple)Machine Instruction Code

90 (RX Instruction)



This instruction works with 3 operands: 1st and 3rd are registers, and 2nd is a storage field. It stores the contents of the registers specified as a range by the 1st and 3rd operands into the storage field 2nd perand. The length of the field depends on how many registers must be stored. To store 2 registers, the area must have 8 bytes; to store 3 registers, the area must have 12 bytes, and so on.Example: STM 14,1,SAVE

SAVE = 16 bytes (bytes 0-3 = contents of register 14; bytes 4-7 = contents of register ; bytes 8-11 = contents of register 0; bytes 12-15 = contents of register 1) |------- SAVE --------------------------------|<----------><---------><----------><----------> Reg. 14 Reg.15 Reg.0 Reg.1 Another example: STM 1,7,2(10)

Mach.Inst.Summary


Machine Instructions - SVC

SVC (SuperVisor Call)Machine Instruction Code

0A (RR Instruction)

Condition code (Remains unchanged in the old PSW)


The format of this instruction is:1st byte = operation code; 2nd byte = SVC numberThis instruction causes a program interruption; this interruption demands CPU to execute a call to the operating system (supervisor) to execute some function.The code (2nd byte – from 0 to 255 – X’00’ up to X’FF’) determines the function to be executed by supervisor .Examples: SVC 0 SVC 7Some MVS-z/OS SVCs:X'00' (000) = EXCP/XDAP X'13' (019) = OPENX'01' (001) = WAIT/WAITR/PRTOV X'14' (020) = CLOSEX'02' (002) = POST X'23' (035) = WTO/WTORX'04' (004) = GETMAIN X'24' (036) = WTLX'05' (005) = FREEMAIN X'5D' (093) = TGET/TPUTX'0B' (011) = TIME X'63' (099) = DYNALLOCX'0D' (013) = ABEND X'6B' (107) = MODESET

Mach.Inst.Summary


Machine Instructions - TM

TM (Test under Mask)Machine Instruction Code

91 (SI Instruction)

Condition code 00 All bits tested are OFF, or mask is zero01 Some bits tested are ON and others are OFF10 Condition code is not set as 10 after TM11 All bits tested are ON


This instruction tests the bits of the 1-byte storage field specified by the 1st operand, using the mask specified in the 2nd operand (self-defining term).The mask indicates whose bits must be tested. The ON bits in the mask indicate the bits of the stoprage byte to be tested.Test means: is the bit(s) ON or OFF?To reflect the result, condition code is set.Example: TM BYTE,X'9C' Bits 0, 3, 4 and 5 of BYTE are testedMore examples: TM KEYAB,B'10000001' Bits 0, and 7 of KEYAB are tested TM 0(4),240 Bits 4,5,6 and 7 of [base register 4 + displacement X’0’] are tested TM 2(8),X'80' Bit 0 [base register 8 + displacement X’2’] is tested

Mach.Inst.Summary


Machine Instructions - TR

TR (TRanslate)Machine Instruction Code

DC (SS Instruction – L)



TR instruction moves the contents of 2nd operand to the 1st operand, according to the 1st operand contents.The move is done left to right, each byte at a time, this way: The contents of each byte of the 1st operand is added (internally) to the 2nd operand address; The byte at the resulting address is moved (copied) to the byte of the 1st operand. 2nd operand remains unchangedExample: TR ACSD,TABLEBefore ACSD 02.00.08.FF.05 TABLE C1.48.B9.D7.A1.C3.D9.5C.4B ........1A 256 bytesAfter ACSD B9.C1.4B.1A.C3 TABLE Remains unchangedMore examples : TR 0(5,7),0(10) TR WAREA+7(10),TABASTER TR 2(5,124),FIELD

Mach.Inst.Summary







More examples : To translate uppercase EBCDIC letters into lowercase EBCDIC letters; invalid letters are converted to EBCDIC spaces CONVTB1 DC 256C' ' 256 EBCDIC spaces ORG CONVTB1+C'A' “Return” to Uppercase A DC C'abcdefghi' Substitute original spaces by lowwercase ORG CONVTB1+C'J' “Return” to Uppercase J DC C'jklmnopqr' Substitute original spaces by lowwercase ORG CONVTB1+C'S' “Return” to Uppercase S DC C'stuvwxyz' Substitute original spaces by lowwercase ORG , Return to byte folowing CONVTB1 To translate uppercase EBCDIC letters into uppercase ASCII letters; invalid letters are converted to ASCII spaces CONVTB2 DC 256X'20' 256 ASCII spaces ORG CONVTB2+C'A' “Return” to Uppercase A DC X'414243444546474849' Substitute EBCDIC value by ASCII value ORG CONVTB1+C'J' “Return” to Uppercase J DC X'4A4B4C4D4E4F505152' Substitute EBCDIC value by ASCII value ORG CONVTB1+C'S' “Return” to Uppercase S DC X'535455565758595A' Substitute EBCDIC value by ASCII value ORG , Return to byte folowing CONVTB2

Mach.Inst.Summary







More examples : To translate uppercase ASCII letters into uppercase EBCDIC letters; invalid “letters” are converted to EBCDIC spaces CONVTB3 DC 256X'40' 256 EBCDIC spaces ORG CONVTB2+X'41' Volta para A maiusculo ASCII DC C'ABCDEFGHIJKLMNOPQRSTUVWXYZ' Substitui ASCII value by EBCDIC ORG , Return to byte CONVTB3+256

Mach.Inst.Summary


Machine Instructions - TRT

TRT (TRanslate and Test)Machine Instruction Code

DD (SS Instruction – L)

Condition code 00 All bytes tested are with X'00'01 Test ended before the last byte to be tested.10 Test ended at the last byte to be tested, and it wasn’t with X'00'11 Condition code is not set as 11 after TRTPossible Interruptions 0005

This instruction tests bytes of the 2nd operand, verifying their status (X’00’ or not).The 1st tested byte NOT in X’00’ ends the instruction execution. 1st operand indicates the 2nd operand bytes to be tested: TRT adds the contents of each byte of the 1st operand to the 2nd operand address (same as TR instruction); the byte at the resulting address is tested with X’00’.When a non-X’00’ byte is detected instruction stores in the register 1 (bits 8-31; bits 0-7 remain unchanged) the address of the 1st operand byte that lead to the 2nd operand non-X’00’ byte; it also stores in register 2 (bits 24-31; bits 0-23 remain unchanged) the contents of the 2nd operand byte not in X’00’. This instruction is generally used to:

Mach.Inst.Summary






a) Validate a decimal zoned field (1st operand – only valid digits):

TRT CART+9(6),TABNUM BZ NUMÉRIC . . . TABNUM DC 240X'FF',10X'00',6X'FF'

b) Validate an alphanumeric field (1st operand – only uppercase letters and spaces)

TRT CART+9(6),TABALFAB BZ FABETIC . . TABALFA DC CL256X'FF' ORG TABALFAB+C' ' DC X'00' ORG TABALFAB+C'A' DC 9X'00' ORG TABALFAB+C'J' DC 9X'00' ORG TABALFAB+C'S' DC 8X'00' ORG

Mach.Inst.Summary






c) Find a character (* in the example) in a string of characters (e.g. for parsing). TRT 0(80,7),TABASTER BZ NOTASTER register 1 has the byte with * . . . TABASTER DC 256X'00' ORG TABASTER+C'*' DC X'FF' ORG

Mach.Inst.Summary


Machine Instructions - TS

TS (Test ans Set)Machine Instruction Code

93 (Instrução S)

Condition code 00 Leftmost bit OFF01 Leftmost bit ON10 Condition code is not set as 10 after TS 11 Condition code is not set as 11 after TS


Second byte of instruction is ignored.The leftmost bit of the (only) operand is tested (ON or OFF).After the test all bits of the byte are set to 1 (ON).Condition code is set according to the result of the test.Example:

TS BYTE

Mach.Inst.Summary


Machine Instructions - UNPK

UNPK (UNPacK)Machine Instruction Code




The UNPK instruction moves a storage packed field to a storage zoned field. The intended function is to convert a numeric field from packed format to zoned format. NO validation is done in the sending field; if its contents is not a valid decimal packed number, the operation flows normally.1st operand is the receiving field and 2nd operand is the sending field. The operation is done from right to left.The two halves of the rightmost byte of the sending field are inverted and moved to the rightmost byte of the receiving field.After that, each half byte of the sending field is sent to a right half of a receiving field byte, and the left half is set to X’F’. 2nd operand remains unchanged.If the receiving field is smaller than needed to fit all digits from the sending field, the leftmost digits are truncated.If the receiving field is greater than needed to fit all digits from sending field, the remaining left bytes are filled with X’F0’.Example: UNPK FLDA,FLDB Before After FLDB 12.34.5C 12.34.5C FLDA 92.B8.4C.D0 F2.F3.F4.C5

Mach.Inst.Summary


Machine Instructions - UNPK

UNPK (UNPacK)Machine Instruction Code




More examples:

UNPK FLDA,FLDB Before After FLDB 12.3C 12.3C FLDA 92.B8.4C.D0 F0.F1.F2.C3

UNPK WRITAREA+5(12),TOTLIQ UNPK AX2,2(3,7) UNPK 17(10,8),T4B2F+3(5) UNPK 2(13,10),0(5,3)

Mach.Inst.Summary


Machine Instructions - X

X ([boolean] eXclusive or Character)Machine Instruction Code

57 (RX Instruction)

Condition code 00 Result = 001 Result <> 010 Condition code is not set as 10 after X11 Condition code is not set as 11 after X


This instruction executes a boolean Exclusive OR between a register (1st operand) and a 4-byte storage field (2nd operand).Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = inverted

Example: X 13,FIELDF

Before AfterRegister 13 B4.EF.2F.A8 B4.EF.2F.57FIELDF 00.00.00.FF 00.00.00.FF

Mach.Inst.Summary


Machine Instructions - XC

XC ([boolean] eXclusive or Character)Machine Instruction Code


Condition code 00 Result = 001 Result <> 010 Condition code is not set as 10 after XC11 Condition code is not set as 11 after XC


This instruction executes a boolean EXCLUSIVE OR between 2 storage fields (1st and 2nd operands). Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = invertedExample: XC FLDA,FLDB Before After FLDA EF.2F.A8 EF.2F.57 FLDB 00.00.00 00.00.FF

Mach.Inst.Summary


Machine Instructions - XI

XI ([boolean] eXclusive or [with] Immediate [operand])Machine Instruction Code

97 (SI Instruction)

Condition code 00 Result = 001 Result <> 010 Condition code is not set as 10 after OI11 Condition code is not set as 11 after OI


This instruction executes a boolean EXCLUSIVE OR between 2 storage fields (1 byte each; 1st operand = field specified using its address; 2nd operand = immediate field, it’s the 2nd byte of the instruction). Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = invertedExample: NI BYE,X’0F’

before AfterBYTE B4 BBImmediate operand 0F 0F

Mach.Inst.Summary


Machine Instructions - XR

XR ([boolean] eXclusive or Register)Machine Instruction Code

17 (RR Instruction)

Condition code 00 Result = 001 Result <> 010 Condition code is not set as 10 after XR11 Condition code is not set as 11 after XR


This instruction executes a boolean EXCLUSIVE OR between 2 registers.Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = invertedExample: XR 5,8 Before AfterRegister 5 B4.EF.2F.A8 B4.EF.2F.57Register 8 00.00.00.FF 00.00.00.FF

Mach.Inst.Summary


Machine Instructions - ZAP

ZAP (Zero and Add Packed)Machine Instruction Code


Condition code 00 Sender field = 001 Sender field < 010 Sender field > 011 Overflow


2nd operand must be a packeddecimal storage field. This instruction zeroes (decimal packed zero) the 1st operand and add the value of the 2st operand to the 1st. 2nd operand remains unchanged.

Note that this process is done internally (in the CPU). That’s the reason one can specify the same storage field as 1st and also as 2nd operand; this is often used to test the number (positive, negative or zero) because ZAP sets the condition code When we do ZAP FLD,FLDbefore zeroing FLD, its contents are internally saved. After being zeroed, when add is done the original contents is available; then it returns to the original value.

Mach.Inst.Summary


Machine Instructions - ZAP

ZAP (Zero and Add Packed)Machine Instruction Code


Condition code 00 Se o campo movido = 001 Se o campo movido < 010 Se o campo movido > 011 Overflow


ZAP CPOA,CPOB Before After1st Case CPOB 12.34.5C 12.34.5C CPOA B4.F8 34.5C2nd Case CPOB 12.3C 12.3C CPOA 07.B8.92 00.12.3C More examples: ZAP TOTAL,=P'0' ZAP CONTLIN,=P'2'

Mach.Inst.Summary


Macro Instructions

MACRO INSTRUCTIONS


Macro Instructions

MACRO INSTRUCTIONS

Sorry... It’s not in the scope of this course...


Appendix - Links

LINKS

z/Architecture

http://publibz.boulder.ibm.com/epubs/pdf/dz9zr006.pdf

ESA Enterprise Systems Architecture / XC Extended Configuration (para z/VM)http://publib.boulder.ibm.com/infocenter/zvm/v5r3/index.jsp?topic=/com.ibm.zvm.v53.hcpb6/abstract.htm

High Level Assembler

http://publib.boulder.ibm.com/infocenter/ratdevz/v7r5/topic/com.ibm.ent.asm.zos.doc/topics/fn1lrmst02.htm#wq2


Appendix – Instructions by operation code

Some instructions (ordered by operation code)

Mnemonic Code Type BALR 05 RR BCTR 06 RR BCR 07 RR SVC 0A RR BSM 0B RR BASSM 0C RR BASR 0D RR MVCL 0E RR CLCL 0F RR LPR 10 RR LNR 11 RR LTR 12 RR LCR 13 RR NR 14 RR CLR 15 RR OR 16 RR XR 17 RR LR 18 RR CR 19 RR AR 1A RR

Mnemonic Code Type SR 1B RR MR 1C RR DR 1D RR ALR 1E RR SLR 1F RR STH 40 RX LA 41 RX STC 42 RX IC 43 RX EX 44 RX BAL 45 RX BCT 46 RX BC 47 RX LH 48 RX CH 49 RX AH 4A RX SH 4B RX MH 4C RX BAS 4D RX CVD 4E RX

Mnemonic Code Type CVB 4F RX ST 50 RX LAE 51 RX N 54 RX CL 55 RX O 56 RX X 57 RX L 58 RX C 59 RX A 5A RX S 5B RX M 5C RX D 5D RX AL 5E RX SL 5F RX STD 60 RX MXD 67 RX LD 68 RX CD 69 RX AD 6A RX

Continues...


Appendix – Instructions by operation code

Some instructions (ordered by operation code)

Mnemonic Code Type SD 6B RX MD 6C RX DD 6D RX AW 6E RX SW 6F RX STE 70 RX LE 78 RX CE 79 RX BXH 86 RS BXLE 87 RS SRL 88 RS SLL 89 RS SRA 8A RS SLA 8B RS SRDL 8C RS SLDL 8D RS SRDA 8E RS SLDA 8F RS STM 90 RS TM 91 SI

Mnemonic Code Type MVI 92 SI TS 93 S NI 94 SI CLI 95 SI OI 96 SI XI 97 SI LM 98 RS MC AF SI LRA B1 RX STCK B205 S CS BA RS CDS BB RS CLM BD RS STCM BE RS ICM BF RS MVN D1 SS/L MVC D2 SS/L MVZ D3 SS/L NC D4 SS/L CLC D5 SS/L

Mnemonic Code Type OC D6 SS/L XC D7 SS/L TR DC SS/L TRT DD SS/L ED DE SS/L EDMK DF SS/L MVCIN E8 SS/L SRP F0 SS/L1I3 MVO F1 SS/L1L2 PACK F2 SS/L1L2 UNPK F3 SS/L1L2 ZAP F8 SS/L1L2 CP F9 SS/L1L2 AP FA SS/L1L2 SP FB SS/L1L2 MP FC SS/L1L2 DP FD SS/L1L2


Appendix – Instructions by mnemonic

Some instructions (ordered by mnemonic)

Continues...

Mnemonic Code TypeA 5A RXAD 6A RXAH 4A RXAL 5E RXALR 1E RRAP FA SS/L1L2AR 1A RRAW 6E RXBAL 45 RXBALR 05 RRBAS 4D RXBASR 0D RRBASSM 0C RRBC 47 RXBCR 07 RRBCT 46 RXBCTR 06 RRBSM 0B RRBXH 86 RSBXLE 87 RS

Mnemonic Code TypeC 59 RXCD 69 RXCDS BB RSCE 79 RXCH 49 RXCL 55 RXCLC D5 SS/LCLCL 0F RRCLI 95 SICLM BD RSCLR 15 RRCP F9 SS/L1L2CR 19 RRCS BA RSCVB 4F RXCVD 4E RXD 5D RXDD 6D RXDP FD SS/L1L2DR 1D RR

Mnemonic Code TypeED DE SS/LEDMK DF SS/LEX 44 RXIC 43 RXICM BF RSL 58 RXLA 41 RXLAE 51 RXLCR 13 RRLD 68 RXLE 78 RXLH 48 RXLM 98 RSLNR 11 RRLPR 10 RRLR 18 RRLRA B1 RXLTR 12 RRM 5C RXMC AF SI


Appendix – Instructions by mnemonic

Some instructions (ordered by mnemonic)Mnemonic Code TypeMD 6C RXMH 4C RXMP FC SS/L1L2MR 1C RRMVC D2 SS/LMVCIN E8 SS/LMVCL 0E RRMVI 92 SIMVN D1 SS/LMVO F1 SS/L1L2MVZ D3 SS/LMXD 67 RXN 54 RXNC D4 SS/LNI 94 SINR 14 RRO 56 RXOC D6 SS/LOI 96 SIOR 16 RR

Mnemonic Code TypePACK F2 SS/L1L2S 5B RXSD 6B RXSH 4B RXSL 5F RXSLA 8B RSSLDA 8F RSSLDL 8D RSSLL 89 RSSLR 1F RRSP FB SS/L1L2SR 1B RRSRA 8A RSSRDA 8E RSSRDL 8C RSSRL 88 RSSRP F0 SS/L1I3ST 50 RXSTC 42 RXSTCK B205 S

Mnemonic Code TypeSTCM BE RSSTD 60 RXSTE 70 RXSTH 40 RXSTM 90 RSSVC 0A RRSW 6F RXTM 91 SITR DC SS/LTRT DD SS/LTS 93 SUNPK F3 SS/L1L2X 57 RXXC D7 SS/LXI 97 SIXR 17 RRZAP F8 SS/L1L2


Appendix – EBCDIC - Some characters

Some EBCDIC configurationsHEX CARATER

40 Space 60 - hiphen 81 a A2 s D0 } Right brace F0 0

4B . point 61 / slash 82 b A3 t D1 J F1 1

4C < less than 6B , comma 83 c

A4 u D2 K F2 2

4D ( Left parenheses 6C % percent 84 d A5 v D3 L F3 3

4E + Plus sign 6D _ underscore 85 e A6 w D4 M F4 4

4F | Vertical bar 6E > Greater than 86 f A7 x D5 N F5 5

50 & Ampersand 6F ? Question mark 87 g

A8 y D6 O F6 6

5A ! Exclamation mark 7A : colon 88 h A9 z D7 P F7 7

5B $ Dollar sign 7B # number sign 91 i C0 { Left brace D8 Q F8 8

5C * Asterisk 7C @ at 92 j C1 A D9 R F9 9

5D ) Right parentheses 7D ' apostrophe 93 k

C2 B E0 \ Backslash

5E ; Semicolon 7E = equals 94 l C3 C E2 S

5F Not 7F " quotes 95 m C4 D E3 T

96 n C5 E E4 U

97 o C6 F E5 V

98 p

C7 G E6 W

99 q C8 H E7 X

9A r C9 I E8 Y

E9 Z


Appendix – ASCII - Some characters

Some ASCII configurationsHEX CARATER

20 Space 30 0 zero 40 @ at

50 P 60 ` grave accent 70 p

21 ! exclamation mark

31 1 one 41 A

51 Q 61 a 71 q

22 “ quotes 32 2 two 42 B

52 R 62 b 72 r

23 # number 33 3 three 43 C

53 S 63 c 73 s

24 $ dollar sign 34 4 four 44 D

54 T 64 d 74 t

25 % percent sign 35 5 five 45 E

55 U 65 e 75 u

26 & ampersand 36 6 six 46 F

56 V 66 f 76 v

27 ‘ apostrophe 37 7 seven 47 G

57 W 67 g 77 w

28 ( Left parentheses 38 8 eight 48 H

58 X 68 h 78 x

29 ) Right parentheses

39 9 nine 49 I

59 Y 69 i 79 y

2A * asterisk 3A : colon 4A J

5A Z 6A j 7A z

2B + plus sign 3B ; semicolon 4B K

5B [ Left bracket 6B k 7B { Left brace

2C , comma 3C < less than 4C L

5C \ back slash 6C l 7C | Vertical Slash

2D - hyphen 3D = equals 4D M

5D ] Right bracket 6D m 7D } Right brace

2E . point 3E > greater 4E N

5E ^ circumflex 6E n 7E ~ tilde

2F / slash 3F ? question mark 4F O

5F _ (underscore) 6F o


Questions

Questions


(Q) Exercises 1-12 (Convert decimal to binary)

Exercise 1 : (987654)10 = (?)2

Exercise 2 : (4095)10 = (?)2

Exercise 3 : (7)10 = (?)2

Exercise 4 : (1023)10 = (?)2

Exercise 5 : (4096)10 = (?)2

Exercise 6 : (255)10 = (?)2

Exercise 7 : (1024)10 = (?)2

Exercise 8 : (10010001)10 = (?)2

Exercise 9 : (256)10 = (?)2

Exercise 10 : (1025)10 = (?)2

Exercise 11 : (999888)10 = (?)2

Exercise 12 : (65432)10 = (?)2


(Q) Exercises 13-24 (Convert decimal to hexadecimal)

Exercise 13 : (987654)10 = (?)16

Exercise 14 : (4095)10 = (?)16

Exercise 15 : (7)10 = (?)16

Exercise 16 : (1023)10 = (?)16

Exercise 17 : (4096)10 = (?)16

Exercise 18 : (255)10 = (?)16

Exercise 19 : (1024)10 = (?)16

Exercise 20 : (10010001)10 = (?)16

Exercise 21 : (256)10 = (?)16

Exercise 22 : (1025)10 = (?)16

Exercise 23 : (999888)10 = (?)16

Exercise 24 : (65432)10 = (?)16


(Q) Exercises 25-36 (Convert binary to hexadecimal)

Exercise 25 : (11111000111010100100001 )2 = (?)16

Exercise 26 : (1000000111000111111110000011111110)2 = (?)16

Exercise 27 : (1100)2 = (?)16

Exercise 28 : (11111110001)2 = (?)16

Exercise 29 : (1010101010101000110011000111)2 = (?)16

Exercise 30 : (110011001100110011001)2 = (?)16

Exercise 31 : (1000000000000001)2 = (?)16

Exercise 32 : (1000000001)2 = (?)16

Exercise 33 : (111111100000001111111)2 = (?)16

Exercise 34 : (1)2 = (?)16

Exercise 35 : (1100101011111110)2 = (?)16

Exercise 36 : (101011010111000111000000001111110001111)2 = (?)16


(Q) Exercises 37-48 (Convert hexadecimal to binary)

Exercise 37 : (CAFE)16 = (?)2

Exercise 38 : (CDF)16 = (?)2

Exercise 39 : (1AB4D)16 = (?)2

Exercise 40 : (15)16 = (?)2

Exercise 41 : (F)16 = (?)2

Exercise 42 : (87B54)16 = (?)2

Exercise 43 : (1001)16 = (?)2

Exercise 44 : (234)16 = (?)2

Exercise 45 : (CAD)16 = (?)2

Exercise 46 : (7F7)16 = (?)2

Exercise 47 : (1990)16 = (?)2

Exercise 48 : (33)16 = (?)2


(Q) Exercises 49-60 (Convert binary to decimal)

Exercise 49 : (11)2 = (?)10

Exercise 50 : (100001111111)2 = (?)10

Exercise 51 : (101010010101)2 = (?)10

Exercise 52 : (110000001111111)2 = (?)10

Exercise 53 : (11111110000011)2 = (?)10

Exercise 54 : (11110000111000)2 = (?)10

Exercise 55 : (11)2 = (?)10

Exercise 56 : (111111110)2 = (?)10

Exercise 57 : (1111100001111000111001101)2 = (?)10

Exercise 58 : (1000000000000)2 = (?)10

Exercise 59 : (11111001)2 = (?)10

Exercise 60 : (1000000000000001)2 = (?)10


(Q) Exercises 61-72 (Convert hexadecimal to decimal)

Exercise 61 : (11)16 = (?)10

Exercise 62 : (AAF45)16 = (?)10

Exercise 63 : (1B567)16 = (?)10

Exercise 64 : (100)16 = (?)10

Exercise 65 : (1000)16 = (?)10

Exercise 66 : (FF)16 = (?)10

Exercise 67 : (FFF)16 = (?)10

Exercise 68 : (CDF)16 = (?)10

Exercise 69 : (CAFE)16 = (?)10

Exercise 70 : (FACA)16 = (?)10

Exercise 71 : (DAD0)16 = (?)10

Exercise 72 : (F1E2D3C4)16 = (?)10


(Q) Exercises 73-84 (Add numbers in binary)

Exercise 73 : (11001100)2 + (10101010)2 = (?)2

Exercise 74 : (1111001111)2 + (1001111001)2 = (?)2

Exercise 75 : (1111)2 + (1)2 = (?)2

Exercise 76 : (1111)2 + (111)2 = (?)2

Exercise 77 : (100001)2 + (11110)2 = (?)2

Exercise 78 : (1011110011)2 + (111101111)2 = (?)2

Exercise 79 : (110011001100)2 + (101011110000)2 = (?)2

Exercise 80 : (1111100001111000)2 + (101111)2 = (?)2

Exercise 81 : (111)2 + (1111)2 + (100)2 = (?)2

Exercise 82 : (11)2 + (111)2 + (1111)2 + (11111)2 = (?)2

Exercise 83 : (1111)2 + (1001)2 + (111)2 + (101)2 + (11)2 + (1)2 = (?)2

Exercise 84 : (111)2 + (1000)2 + (1)2 + (1100)2 = (?)2


(Q) Exercises 85-96 (Subtract numbers in binary)

Exercise 85 : (11001100)2 - (1010101)2 = (?)2

Exercise 86 : (1111001111)2 - (1111001)2 = (?)2

Exercise 87 : (1111)2 - (1)2 = (?)2

Exercise 88 : (1111)2 - (111)2 = (?)2

Exercise 89 : (100001)2 - (11110)2 = (?)2

Exercise 90 : (1011110011)2 - (111101111)2 = (?)2

Exercise 91 : (11001100)2 - (111011110000)2 = (?)2

Exercise 92 : (1111000)2 - (101010111)2 = (?)2

Exercise 93 : (111)2 - (1111)2 = (?)2

Exercise 94 : (10001)2 - (111111)2 = (?)2

Exercise 95 : (0)2 - (1)2 = (?)2

Exercise 96 : (0)2 - (10)2 = (?)2


(Q) Exercises 97-108 (Add numbers in hexadecimal)

Exercise 97 : (F12B)16 + (321)16 = (?)16

Exercise 98 : (1100)16 + (111)2 = (?)16

Exercise 99 : (1000F)16 + (F0001)16 = (?)16

Exercise 100 : (A9B8C7)16 + (D6E5F4)16 = (?)16

Exercise 101 : (CAFE)16 + (CDF)16 = (?)16

Exercise 102 : (B001)16 + (FD)16 = (?)16

Exercise 103 : (999)16 + (111)16 = (?)16

Exercise 104 : (123456)16 + (789ABC)16 = (?)16

Exercise 105 : (FFF)16 + (EEE)16 = (?)16

Exercise 106 : (DDD)16 + (333)16 = (?)16

Exercise 107 : (987AED)16 + (CF01)16 = (?)16

Exercise 108 : (FACA)16 + (CAFE)16 = (?)16


(Q) Exercises 109-120 (Subtract numbers in hexadecimal)

Exercise 109 : (F1C5)16 - (101)16 = (?)16

Exercise 110 : (1AD87C)16 - (FDE9)2 = (?)16

Exercise 111 : (112233)16 - (44556)16 = (?)16

Exercise 112 : (AABBCC)16 - (DDEEF)16 = (?)16

Exercise 113 : (F1E2D3)16 - (C4B5A6)16 = (?)16

Exercise 114 : (FF00001)16 - (10000F)16 = (?)16

Exercise 115 : (CAFE)16 - (FACA)16 = (?)16

Exercise 116 : (CDF)16 - (FDC)16 = (?)16

Exercise 117 : (10001)16 - (20001)16 = (?)16

Exercise 118 : (10000)16 - (FFFE)16 = (?)16

Exercise 119 : (0)16 - (9)16 = (?)16

Exercise 120 : (0)16 - (1A)16 = (?)16


(Q) Exercises 121-126 (Representing binary numbers in bytes)

Exercise 121 : (1)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16

= (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16

Exercise 122 : (-1)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16











(Q) Exercises 141-152 (Representing packed numbers in bytes)

Exercise 141 : (1)10 = (in decimal-packed format)

Exercise 142 : (-1)10 = (in decimal-packed format)












(Q) Exercises 153-160 (Representing packed numbers in bytes)










(Q) Exercises 161-172 (Representing zoned numbers in bytes)

Exercise 161 : (1)10 = (in decimal-zoned format)

Exercise 162 : (-1)10 = (in decimal-zoned format)












(Q) Exercises 173-180 (Representing zoned numbers in bytes)










(Q) Exercises 181-194 (Representing character strings in bytes)

Exercise 181 : “17“ = (in alphanumeric EBCDIC) Exercise 182 : “-17“ = (in alphanumeric EBCDIC) Exercise 183 : “AF$BD“ = (in alphanumeric EBCDIC) Exercise 184 : “-AF4BD“ = (in alphanumeric EBCDIC) Exercise 185 : “ALBERTO“ = (in alphanumeric EBCDIC) Exercise 186 : “15-9“ = (in alphanumeric EBCDIC) Exercise 187 : “-4095“ = (in alphanumeric EBCDIC) Exercise 188 : “4095“ = (in alphanumeric EBCDIC) Exercise 189 : “*&$//“ = (in alphanumeric EBCDIC) Exercise 190 : “12+3“ = (in alphanumeric EBCDIC) Exercise 191 : “I LOVE HER“ = (in alphanumeric EBCDIC) Exercise 192 : “US$ 2,584.73“ = (in alphanumeric EBCDIC) Exercise 193 : “US$ 1 MILLION“ = (in alphanumeric EBCDIC) Exercise 194 : “PANCHO’S BAR“ = (in alphanumeric EBCDIC)


(Q) Exercises 195-209 (Representing fields in bytes)

Exercises 195-300 must be considered as a program starting at address X’00000000’, that is, first area (exercise 195) begins at address zero. The DS defined areas must be computed to determine the addresses. Assume the 1st statement of the program is USING *,9.Exercise 195: DC C'123' Exercise 196: DC C'+123' Exercise 197: DC C'-123' Exercise 198: DC C'12.3' Exercise 199: DC C'1AB8' Exercise 200: DC C'01101' Exercise 201: DC C'A+B=C' Exercise 202: DC CL4'A' Exercise 203: DC CL4'ABCDEF' Exercise 204: DC 3CL2'A' Exercise 205: DC 2CL3'A,B' Exercise 206: DC C'ME&&YOU' Exercise 207: DC C'''S MUSIC' Exercise 208: DC C'@@OI' Exercise 209: DC CL3'*'



Exercise 210: DC 3C'*' Exercise 211: DC X'123' Exercise 212: DC X'-123' Exercise 213: DC X'1AB2C3' Exercise 214: DC X'1AB2F4G3' Exercise 215: DC XL3'12D' Exercise 216: DC XL3'AABBCCDDEE' Exercise 217: DC X'1,22,333,4444' Exercise 218: DC XL2'1,22,333' Exercise 219: DC 2X'1,22,333' Exercise 220: DC 2XL2'1,22' Exercise 221: DC B'01010101' Exercise 222: DC B'1' Exercise 223: DC BL2'1111' Exercise 224: DC B'1,1111111111' Exercise 225: DC BL2'1,1111111111'



Exercise 226: DC 2B'1000' Exercise 227: DC 2BL2'1000' Exercise 228: DC F'10' Exercise 229: DC F'+10' Exercise 230: DC F'-10' Exercise 230: DC F'-15,+16' Exercise 231: DC 2F'22' Exercise 232: DC 2F'33,44' Exercise 233: DC FL3'258' Exercise 234: DC 2FL1'255' Exercise 235: DC F'128000' Exercise 236: DC H'10' Exercise 237: DC H'+10' Exercise 238: DC H'-10' Exercise 239: DC H'-15,+16'



Exercise 240: DC 2H'22' Exercise 241: DC 2H'33,44' Exercise 242: DC HL3'258' Exercise 243: DC 2HL1'255' Exercise 244: DC H'128000' Exercise 245: DC P'123' Exercise 246: DC P'+123' Exercise 247: DC P'-123' Exercise 248: DC PL4'456' Exercise 249: DC PL1'789' Exercise 250: DC P'1,-22,333,-4444' Exercise 251: DC PL2'1,-22,333,-4444'Exercise 252: DC 3P'0' Exercise 253: DC PL3'0' Exercise 254: DC 2P'1,22,333'



Exercise 255: DC 2PL2'1,22,333' Exercise 256: DC Z'123' Exercise 257: DC Z'+123' Exercise 258: DC Z'-123' Exercise 259: DC ZL4'456' Exercise 260: DC ZL1'789' Exercise 261: DC Z'1,-22,333,-4444' Exercise 262: DC ZL3'1,-22,333,-4444' Exercise 263: DC 3Z'0' Exercise 264: DC ZL3'0' Exercise 265: DC 2Z'1,22,333' Exercise 266: DC 2ZL3'1,22,333'



Exercise 267: SIMBZZ DC A(0) Exercise 268: SIMBAA DC A(127) Exercise 269: SIMBBB DC A(X'8000') Exercise 270: SIMBCC DC A(B'1111') Exercise 271: SIMBDD DC A(C'*') Exercise 272: SIMBEE DC A(*) Exercise 273: SIMBFF DS CL17 Exercise 274: SIMBGG DC A(*) Exercise 275: SIMBHH DC A(SIMBGG) Exercise 276: SIMBII DC A(SIMBAA+12) Exercise 277: SIMBJJ DC A(SIMBII-SIMBBB) Exercise 278: SIMBKK DC AL1(*-SIMBKK) Exercise 279: SIMBLL DC 5AL1(*-SIMBLL)



Exercise 280: SIMBMM DC AL2(3,5,7) Exercise 281: SIMBNN DC A(SIMBII+5*2) Exercise 282: SIMBOO DC A(SIMBNN+X'80000000') Exercise 283: SIMBPP DC 4AL2(*-SIMBPP) Exercise 284: SIMBQQ DC A(SIMBVV) Exercise 285: SIMBRR DC A(SIMBKK,SIMBJJ) Exercise 286: SIMBSS DC A(SIMBTT+40) Exercise 287: SIMBTT DC A(SIMBUU,*,80) Exercise 288: SIMBUU DC 2A(*-SIMBUU) Exercise 289: SIMBVV DC A(C'AMO') Exercise 290: SIMBWW DC A(X'7FFFFFFF')



Exercise 291: YY1 DC Y(SIMBWW) Exercise 292: YY2 DC Y(10) Exercise 293: YY3 DC Y(L'YY2) Exercise 294: SS1 DC S(SIMBAA) Exercise 295: SS2 DC S(SS1) Exercise 296: SS3 DC S(10) Exercise 297: SS4 DC S(*) Exercise 298: SS5 DC A(125),F'33',C'*',2H'6,18' Exercise 299: SS6 DC X'1,1',B'1,1',C'1,1' Exercise 300: LAST DC 256AL1(255+LAST-*)


(Q) Exercise 301 (Decoding instructions)

Exercise 301 : Decode the following set of instructions; for each one, specify:- Operation code (machine code)- Menmonic Assembler code- Instruction address (suppose 1st instruction at address X’00000000’)- Operands (register, base register, index register, displacement; if operand is in storage, compute the operand address; to compute the operand’s addresses suppose the general registers with the following contents: R00=00112233 R04=00000400 R08=00000800 R12=00000C00R01=00000100 R05=00000500 R09=00000900 R13=00000D00R02=00000200 R06=00000600 R10=00000A00 R14=00000E00R03=00000300 R07=00000700 R11=00000B00 R15=00000F00

Instructions to decode: 1ABB41278CF00A13980F334445E00CB490EC0D00FA82305448CCD28233445566


Answers

Answers


(A) Exercises 1-12 (Convert decimal to binary)

Exercise 1 : (987654)10 = (1111 0001 0010 0000 0110)2

Exercise 2 : (4095)10 = (1111 1111 1111)2

Exercise 3 : (7)10 = (111)2

Exercise 4 : (1023)10 = (11 1111 1111)2

Exercise 5 : (4096)10 = (1 0000 0000 0000)2

Exercise 6 : (255)10 = (1111 1111)2

Exercise 7 : (1024)10 = (100 0000 0000)2

Exercise 8 : (10010001)10 = (1001 1000 1011 1101 1001 0001)2

Exercise 9 : (256)10 = (1 0000 0000)2

Exercise 10 : (1025)10 = (100 0000 0001)2

Exercise 11 : (999888)10 = (1111 0100 0001 1101 0000)2

Exercise 12 : (65432)10 = (1111 1111 1001 1000)2


(A) Exercises 13-24 (Convert decimal to hexadecimal)

Exercise 13 : (987654)10 = (F1206)16

Exercise 14 : (4095)10 = (FFF)16

Exercise 15 : (7)10 = (7)16

Exercise 16 : (1023)10 = (3FF)16

Exercise 17 : (4096)10 = (1000)16

Exercise 18 : (255)10 = (FF)16

Exercise 19 : (1024)10 = (400)16

Exercise 20 : (10010001)10 = (98BD91)16

Exercise 21 : (256)10 = (100)16

Exercise 22 : (1025)10 = (401)16

Exercise 23 : (999888)10 = (F41D0)16

Exercise 24 : (65432)10 = (FF98)16


(A) Exercises 25-36 (Convert binary to hexadecimal)

Exercise 25 : (11111000111010100100001 )2 = (7C7521)16

Exercise 26 : (1000000111000111111110000011111110)2 = (2071FE0FE)16

Exercise 27 : (1100)2 = (C)16

Exercise 28 : (11111110001)2 = (7F1)16

Exercise 29 : (1010101010101000110011000111)2 = (AAA8CC7)16

Exercise 30 : (110011001100110011001)2 = (199999)16

Exercise 31 : (1000000000000001)2 = (8001)16

Exercise 32 : (1000000001)2 = (201)16

Exercise 33 : (111111100000001111111)2 = (1FC07F)16

Exercise 34 : (1)2 = (1)16

Exercise 35 : (1100101011111110)2 = (CAFE)16

Exercise 36 : (101011010111000111000000001111110001111)2 = (56B8E01F8F)16


(A) Exercises 37-48 (Convert hexadecimal to binary)

Exercise 37 : (CAFE)16 = (1100101011111110)2

Exercise 38 : (CDF)16 = (110011011111)2

Exercise 39 : (1AB4D)16 = (11010101101001101)2

Exercise 40 : (15)16 = (10101)2

Exercise 41 : (F)16 = (1111)2

Exercise 42 : (87B54)16 = (10000111101101010100)2

Exercise 43 : (1001)16 = (1000000000001)2

Exercise 44 : (234)16 = (1000110100)2

Exercise 45 : (CAD)16 = (110010101101)2

Exercise 46 : (7F7)16 = (11111110111)2

Exercise 47 : (1990)16 = (1100110010000)2

Exercise 48 : (33)16 = (110011)2


(A) Exercises 49-60 (Convert binary to decimal)

Exercise 49 : (11)2 = (3)10

Exercise 50 : (100001111111)2 = (2175)10

Exercise 51 : (101010010101)2 = (2709)10

Exercise 52 : (110000001111111)2 = (24703)10

Exercise 53 : (11111110000011)2 = (16259)10

Exercise 54 : (11110000111000)2 = (15416)10

Exercise 55 : (11)2 = (3)10

Exercise 56 : (111111110)2 = (510)10

Exercise 57 : (1111100001111000111001101)2 = (32567757)10

Exercise 58 : (1000000000000)2 = (4096)10

Exercise 59 : (11111001)2 = (249)10

Exercise 60 : (1000000000000001)2 = (32769)10


(A) Exercises 61-72 (Convert hexadecimal to decimal)

Exercise 61 : (11)16 = (17)10

Exercise 62 : (AAF45)16 = (700229)10

Exercise 63 : (1B567)16 = (111975)10

Exercise 64 : (100)16 = (256)10

Exercise 65 : (1000)16 = (4096)10

Exercise 66 : (FF)16 = (255)10

Exercise 67 : (FFF)16 = (4095)10

Exercise 68 : (CDF)16 = (3295)10

Exercise 69 : (CAFE)16 = (51966)10

Exercise 70 : (FACA)16 = (64202)10

Exercise 71 : (DAD0)16 = (56016)10

Exercise 72 : (F1E2D3C4)16 = (4058174404)10


(A) Exercises 73-84 (Add numbers in binary)

Exercise 73 : (11001100)2 + (10101010)2 = (1 0111 0110)2

Exercise 74 : (1111001111)2 + (1001111001)2 = (110 0100 1000)2

Exercise 75 : (1111)2 + (1)2 = (10000)2

Exercise 76 : (1111)2 + (111)2 = (10110)2

Exercise 77 : (100001)2 + (11110)2 = (111111)2

Exercise 78 : (1011110011)2 + (111101111)2 = (100 1110 0010)2

Exercise 79 : (110011001100)2 + (101011110000)2 = (1 0111 1011 1100)2

Exercise 80 : (1111100001111000)2 + (101111)2 = (1111 1000 1010 0111)2

Exercise 81 : (111)2 + (1111)2 + (100)2 = (11010)2

Exercise 82 : (11)2 + (111)2 + (1111)2 + (11111)2 = (111000)2

Exercise 83 : (1111)2 + (1001)2 + (111)2 + (101)2 + (11)2 + (1)2 = (101000)2

Exercise 84 : (111)2 + (1000)2 + (1)2 + (1100)2 = (11100)2


(A) Exercises 85-96 (Subtract numbers in binary)

Exercise 85 : (11001100)2 - (1010101)2 = (111 0111)2

Exercise 86 : (1111001111)2 - (1111001)2 = (11 0101 0110)2

Exercise 87 : (1111)2 - (1)2 = (1110)2

Exercise 88 : (1111)2 - (111)2 = (1000)2

Exercise 89 : (100001)2 - (11110)2 = (11)2

Exercise 90 : (1011110011)2 - (111101111)2 = (1 0000 0100)2

Exercise 91 : (11001100)2 - (111011110000)2 = (...1111 1111 1100 1101)2

Exercise 92 : (1111000)2 - (101010111)2 = (... 1111 1111 0010 0001)2

Exercise 93 : (111)2 - (1111)2 = (... 1111 1111 1111 1000)2

Exercise 94 : (10001)2 - (111111)2 = (... 1111 1111 1101 0010)2

Exercise 95 : (0)2 - (1)2 = (... 1111 1111 1111 1111)2

Exercise 96 : (0)2 - (10)2 = (... 1111 1111 1111 1110)2


(A) Exercises 97-108 (Add numbers in hexadecimal)

Exercise 97 : (F12B)16 + (321)16 = (F44C)16

Exercise 98 : (1100)16 + (111)2 = (1211)16

Exercise 99 : (1000F)16 + (F0001)16 = (100010)16

Exercise 100 : (A9B8C7)16 + (D6E5F4)16 = (1809EBB)16

Exercise 101 : (CAFE)16 + (CDF)16 = (D7DD)16

Exercise 102 : (B001)16 + (FD)16 = (B0FE)16

Exercise 103 : (999)16 + (111)16 = (AAA)16

Exercise 104 : (123456)16 + (789ABC)16 = (19BBF12)16

Exercise 105 : (FFF)16 + (EEE)16 = (1EED)16

Exercise 106 : (DDD)16 + (333)16 = (1110)16

Exercise 107 : (987AED)16 + (CF01)16 = (9949EE)16

Exercise 108 : (FACA)16 + (CAFE)16 = (1C5C8)16


(A) Exercises 109-120 (Subtract numbers in hexadecimal)

Exercise 109 : (F1C5)16 - (101)16 = (F0C4)16

Exercise 110 : (1AD87C)16 - (FDE9)2 = (19DA93)16

Exercise 111 : (112233)16 - (44556)16 = (CDCDD)16

Exercise 112 : (AABBCC)16 - (DDEEF)16 = (9CDCDD)16

Exercise 113 : (F1E2D3)16 - (C4B5A6)16 = (2D2D2D)16

Exercise 114 : (FF00001)16 - (10000F)16 = (FDFFFF2)16

Exercise 115 : (CAFE)16 - (FACA)16 = (...FFFFD034)16

Exercise 116 : (CDF)16 - (FDC)16 = (...FFFFFD03)16

Exercise 117 : (10001)16 - (20001)16 = (...FFFF0000)16

Exercise 118 : (10000)16 - (FFFE)16 = (2)16

Exercise 119 : (0)16 - (9)16 = (...FFFFFFF7)16

Exercise 120 : (0)16 - (1A)16 = (...FFFFFFE6)16


(A) Exercises 121-126 (Representing binary numbers in bytes)

Exercise 121 : (1)10 = (0000 0000 0000 0001)2 = (0001)16

= (0000 0000 0000 0000 0000 0000 0000 0001)2 = (00000001)16

Exercise 122 : (-1)10 = (1111 1111 1111 1111)2 = (FFFF)16

= (1111 1111 1111 1111 1111 1111 1111 1111)2 = (FFFFFFFF)16

Exercise 123 : (10)10 = (0000 0000 0000 1010)2 = (000A)16

= (0000 0000 0000 0000 0000 0000 0000 1010)2 = (0000000A)16

Exercise 124 : (-10)10 = (1111 1111 1111 0110)2 = (FFF6)16

= (1111 1111 1111 1111 1111 1111 1111 0110)2 = (FFFFFFF6)16

Exercise 125 : (17)10 = (0000 0000 0001 0001)2 = (0011)16

= (0000 0000 0000 0000 0000 0000 0001 0001)2 = (00000011)16

Exercise 126 : (-17)10 = (1111 1111 1110 1111)2 = (FFEF)16

= (1111 1111 1111 1111 1111 1111 1110 1111)2 = (FFFFFFEF)16



Exercise 127 : (254)10 = (0000 0000 1111 1110)2 = (00FE)16

= (0000 0000 0000 0000 0000 0000 1111 1110)2 = (000000FE)16

Exercise 128 : (-254)10 = (1111 1111 0000 0010)2 = (FF02)16

= (1111 1111 1111 1111 1111 1111 0000 0010)2 = (FFFFFF02)16

Exercise 129 : (100000)10 = (impossible to represent in 2 bytes)

= (0000 0000 0000 0001 1000 0110 1010 0000)2 = (000186A0)16

Exercise 130 : (-100000)10 = (impossible to represent in 2 bytes)

= (1111 1111 1111 1110 0111 1001 0110 0000)2 = (FFFE7960)16

Exercise 131 : (32000)10 = (0111 1101 0000 0000)2 = (7D00)16

= (0000 0000 0000 0000 0111 1101 0000 0000)2 = (00007D00)16

Exercise 132 : (-32000)10 = (1000 0011 0000 0000)2 = (8300)16

= (1111 1111 1111 1111 1000 0011 0000 0000)2 = (FFFF8300)16



Exercise 133 : (63000)10 = (impossible to represent in 2 bytes)

= (1111 1111 1111 1111 1111 0110 0001 1000 )2 = (FFFFF618)16

Exercise 134 : (-63000)10 = (impossible to represent in 2 bytes)

= (1111 1111 1111 1111 0000 1001 1110 1000)2 = (FFFF09E8)16

Exercise 135 : (1010)10 = (0000 0011 1111 0010)2 = (03F2)16

= (0000 0000 0000 0000 0000 0011 1111 0010)2 = (000003F2)16

Exercise 136 : (-1010)10 = (1111 1100 0000 1110)2 = (FC0E)16

= (1111 1111 1111 1111 1111 1100 0000 1110)2 = (FFFFFC0E)16

Exercise 137 : (4095)10 = (0000 1111 1111 1111)2 = (0FFF)16

= (0000 0000 0000 0000 0000 1111 1111 1111)2 = (00000FFF)16

Exercise 138 : (-4095)10 = (1111 0000 0000 0001)2 = (F001)16

= (1111 1111 1111 1111 1111 0000 0000 0001)2 = (FFFFF001)16



Exercise 139 : (4097)10 = (0001 0000 0000 0001)2 = (1001)16

= (0000 0000 0000 0000 0001 0000 0000 0001)2 = (00001001)16

Exercise 140 : (-4097)10 = (1110 1111 1111 1111)2 = (EFFF)16

= (1111 1111 1111 1111 1110 1111 1111 1111)2 = (FFFFEFFF)16


(A) Exercises 141-152 (Representing packed numbers in bytes)

Exercise 141 : (1)10 = [ 0001 1100 ] = [ 1C ]

Exercise 142 : (-1)10 = [ 0001 1101 } = [ 1D ]

Exercise 143 : (10)10 = [ 0000 0001 0000 1100 ] = [ 010C ]

Exercise 144 : (-10)10 = [ 0000 0001 0000 1101 ] = [ 10D ]

Exercise 145 : (17)10 = [ 0000 0001 0111 1100 ] = [ 017C ]

Exercise 146 : (-17)10 = [ 0000 0001 0111 1101 ] = [ 017D ]

Exercise 147 : (254)10 = [ 0010 0101 0100 1100 ] = [ 254C ]

Exercise 148 : (-254)10 = [0010 0101 0100 1101 ] = [ 254D ]

Exercise 149 : (100000)10 = [ 0000 0001 0000 0000 0000 0000 0000 1100 ] = [ 0100000C ]

Exercise 150 : (100000)10 = [ 0000 0001 0000 0000 0000 0000 0000 1101 ] = [ 0100000D ]

Exercise 151 : (32000)10 = [ 0011 0010 0000 0000 0000 1100 ] = [ 32000C ]

Exercise 152 : (-32000)10 = [ 0011 0010 0000 0000 0000 1101 ] = [ 32000D ]


(A) Exercises 153-160 (Representing packed numbers in bytes)

Exercise 153 : (63000)10 = [ 0110 0011 0000 0000 0000 1100 ] = [ 63000C ]

Exercise 154 : (-63000)10 = [ 0110 0011 0000 0000 0000 1101 ] = [ 63000D ]

Exercise 155 : (1010)10 = [ 0000 0001 0000 0001 0000 1100 ] = [ 01010C ]

Exercise 156 : (-1010)10 = [ 0000 0001 0000 0001 0000 1100 ] = [ 01010D ]

Exercise 157 : (4095)10 = [ 0000 0100 0000 1001 0101 1100 ] = [ 04095C ]

Exercise 158 : (-4095)10 = [ 0000 0100 0000 1001 0101 1101 ] = [ 04095D ]

Exercise 159 : (4097)10 = [ 0000 0100 0000 1001 0111 1100 ] = [ 04097C ]

Exercise 160 : (-4097)10 = [ 0000 0100 0000 1001 0111 1101 ] = [ 04097D ]


(A) Exercises 161-172 (Representing zoned numbers in bytes)

Exercise 161 : (1)10 = [ 1111 0001 ] = [ F1 ]Exercise 162 : (-1)10 = [ 1101 0001 } = [ D1 ]Exercise 163 : (10)10 = [ 1111 0001 1111 0000 ] = [ F1F0 ]Exercise 164 : (-10)10 = [ 1111 0001 1101 0000 ] = [ F1D0 ]Exercise 165 : (17)10 = [ 1111 0001 1111 0111 ] = [ F1F7 ]Exercise 166 : (-17)10 = [ 1111 0001 1101 0111 ] = [ F1D7 ]Exercise 167 : (254)10 = [ 1111 0010 1111 0101 1111 0100 ] = [ F2F5F4 ]Exercise 168 : (-254)10 = [ 1111 0010 1111 0101 1101 0100 ] = [ F2F5D4 ]Exercise 169 : (100000)10 = [ 1111 0001 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 ] = [ F1F0F0F0F0F0 ]Exercise 170 : (-100000)10 = [ 1111 0001 1111 0000 1111 0000 1111 0000 1111 0000 1101 0000 ] = [ F1F0F0F0F0D0 ]Exercise 171 : (32000)10 = [ 1111 0011 1111 0010 1111 0000 1111 0000 1111 0000 ] = [ F3F2F0F0F0 ]Exercise 172 : (-32000)10 = [ 1111 0011 1111 0010 1111 0000 1111 0000 1111 0000 ] = [ F3F2F0F0D0 ]


(A) Exercises 173-180 (Representing zoned numbers in bytes)

Exercise 173 : (63000)10 =

[ 1111 0110 1111 0011 1111 0000 1111 0000 1111 0000 ] = [ F6F3F0F0F0 ]

Exercise 174 : (-63000)10 =

[ 1111 0110 1111 0011 1111 0000 1111 0000 1101 0000 ] = [ F6F3F0F0D0 ]

Exercise 175 : (1010)10 = [ 1111 0001 1111 0000 1111 0001 1111 0000 ] = [ F1F0F1F0 ]

Exercise 176 : (-1010)10 = [ 1111 0001 1111 0000 1111 0001 1101 0000 ] = [ F1F0F1D0 ]

Exercise 177 : (4095)10 = [ 1111 0100 1111 0000 1111 1001 1111 0101 ] = [ F4F0F9F5 ]

Exercise 178 : (-4095)10 = [ 1111 0100 1111 0000 1111 1001 1101 0101 ] = [ F4F0F9D5 ]

Exercise 179 : (4097)10 = [ 1111 0100 1111 0000 1111 1001 1111 1111 ] = [ F4F0F9F7 ]

Exercise 180 : (-4097)10 = [ 1111 0100 1111 0000 1111 1001 1101 0111 ] = [ F4F0F9D7 ]


(A) Exercises 181-194 (Representing character strings in bytes)

Exercise 181 : “17“ = [ F1F7 ]Exercise 182 : “-17“ = [ 60F1F7 ]Exercise 183 : “AF$BD“ = [ C1C66BC2C4 ]Exercise 184 : “-AF4BD“ = [ 60C1C6F4C2C4 ]Exercise 185 : “ALBERTO“ = [ C1D3C2C5D9E3D6 ] Exercise 186 : “15-9“ = [ F1F560F9 ] Exercise 187 : “-4095“ = [ 60F4F0F9F5 ] Exercise 188 : “4095“ = [ F4F0F9F5 ] Exercise 189 : “*&$//“ = [ 5C505B6161 ] Exercise 190 : “12+3“ = [ F1F24EF3 ] Exercise 191 : “I LOVE HER“ = [ C940D3D6E5C540C8C5D9 ] Exercise 192 : “US$ 2,584.73“ = [ E4E25B40F26BF5F8F44BF7F3 ] Exercise 193 : “US$ 1 MILLION“ = [ E4E25B40F140D4C9D3D3C9D6D5 ]Exercise 194 : “PANCHO’S BAR“ = [ D7C1C5C3C8D67DE240C2C1D9 ]


(A) Exercises 195-209 (Representing fields in bytes)

Exercises 195-300 must be considered as a program starting at address X’00000000’, that is, first area (exercise 195) begins at address zero. The DS defined areas must be computed to determine the addresses. Assume the 1st statement of the program is USING *,9.* Address Contents

Exercise 195: DC C'123' 0000 F1.F2.F3Exercise 196: DC C'+123' 0003 4E.F1.F2.F3Exercise 197: DC C'-123' 0007 60.F1.F2.F3Exercise 198: DC C'12.3' 000B F1.F2.4B.F3Exercise 199: DC C'1AB8' 000F F1.C1.C2.F8Exercise 200: DC C'01101' 0013 F0.F1.F1.F0.F1Exercise 201: DC C'A+B=C' 0018 C1.4E.C2.7E.C3Exercise 202: DC CL4'A' 001D C1.40.40.40Exercise 203: DC CL4'ABCDEF' 0021 C1.C2.C3.C4Exercise 204: DC 3CL2'A' 0025 C1.40.C1.40.C1.40 Exercise 205: DC 2CL3'A,B' 002B C1.6B.C2.C1.6B.C2Exercise 206: DC C'ME&&YOU' 0031 D4.C5.50.E8.D6.E4Exercise 207: DC C'''S MUSIC' 0037 7D.E2.40.D4.E4.E2.C9.C3Exercise 208: DC C'@@OI' 003F 7C.7C.D6.C9Exercise 209: DC CL3'*' 0043 5C.40.40



* Address Contents

Exercise 210: DC 3C'*' 0046 5C.5C.5CExercise 211: DC X'123' 0049 01.23Exercise 212: DC X'-123' *** error *** Exercise 213: DC X'1AB2C3' 004B 1A.B2.C3Exercise 214: DC X'1AB2F4G3' *** error ***Exercise 215: DC XL3'12D' 004E 00.01.2DExercise 216: DC XL3'AABBCCDDEE' 0051 CC.DD.EE Exercise 217: DC X'1,22,333,4444' 0054 01.22.03.33.44.44 Exercise 218: DC XL2'1,22,333' 005A 00.01.00.22.03.33 Exercise 219: DC 2X'1,22,333' 0060 01.22.03.33.01.22.03.33 Exercise 220: DC 2XL2'1,22' 0068 00.01.00.22.00.01.00.22Exercise 221: DC B'01010101' 0070 55Exercise 222: DC B'1' 0071 01Exercise 223: DC BL2'1111' 0072 00.0FExercise 224: DC B'1,1111111111' 0074 01.03.FFExercise 225: DC BL2'1,1111111111' 0077 00.01.03.FF



* Address Contents

Exercise 226: DC 2B'1000' 007B 08.08Exercise 227: DC 2BL2'1000' 007D 00.08.00.08 0081 00.00.00 (align) Exercise 228: DC F'10' 0084 00.00.00.0A Exercise 229: DC F'+10' 0088 00.00.00.0AExercise 230: DC F'-10' 008C FF.FF.FF.F6Exercise 230: DC F'-15,+16' 0090 FF.FF.FF.F1.00.00.00.10Exercise 231: DC 2F'22' 0098 00.00.00.16.00.00.00.16Exercise 232: DC 2F'33,44' 00A0 00.00.00.21.00.00.00.2C 00.00.00.21.00.00.00.2C Exercise 233: DC FL3'258' 00B0 00.01.02Exercise 234: DC 2FL1'255' 00B3 FF.FF 00B5 00.00.00 (align)Exercise 235: DC F'128000' 00B8 00.01.F4.00Exercise 236: DC H'10' 00BC 00.0AExercise 237: DC H'+10' 00BE 00.0AExercise 238: DC H'-10' 00C0 FF.F6Exercise 239: DC H'-15,+16' 00C2 FF.F1.00.10



* Address Contents

Exercise 240: DC 2H'22' 00C6 00.16.00.16 Exercise 241: DC 2H'33,44' 00CA 00.21.00.2C.00.21.00.2C Exercise 242: DC HL3'258' 00D2 00.01.02 Exercise 243: DC 2HL1'255' 00D5 FF.FF 00D7 00 (align)Exercise 244: DC H'128000' 00D8 F4.00 Exercise 245: DC P'123' 00DA 12.3C Exercise 246: DC P'+123' 00DC 12.3C Exercise 247: DC P'-123' 00DE 12.3DExercise 248: DC PL4'456' 00E0 00.00.45.6CExercise 249: DC PL1'789' 00E4 9C Exercise 250: DC P'1,-22,333,-4444' 00E5 1C.02.2D.33.3C.04.44.4DExercise 251: DC PL2'1,-22,333,-4444' 00ED 00.1C.02.2D.33.3C.44.4DExercise 252: DC 3P'0' 00F5 0C.0C.0C Exercise 253: DC PL3'0' 00F8 00.00.0CExercise 254: DC 2P'1,22,333' 00FB 1C.02.2C.33.3C.1C.02.2C.33.3C



* Address Contents

Exercise 255: DC 2PL2'1,22,333' 0105 00.1C.02.2C.33.3C 00.1C.02.2C.33.3CExercise 256: DC Z'123' 0111 F1.F2.C3Exercise 257: DC Z'+123' 0114 F1.F2.C3Exercise 258: DC Z'-123' 0117 F1.F2.D3Exercise 259: DC ZL4'456' 011A F0.F4.F5.C6Exercise 260: DC ZL1'789' 011E C9Exercise 261: DC Z'1,-22,333,-4444' 011F F1.F2.D2.F3.F3.C3.F4.F4.F4.D4Exercise 262: DC ZL3'1,-22,333,-4444' 0129 F0.F0.C1.F0.F2.D2.F3.F3.C3 F4.F4.F4.D4Exercise 263: DC 3Z'0' 0135 C0.C0.C0Exercise 264: DC ZL3'0' 0138 F0.F0.F0Exercise 265: DC 2Z'1,22,333' 013B C1.F2.C2.F3.F3.C3 C1.F2.C2.F3.F3.C3Exercise 266: DC 2ZL3'1,22,333' 0147 F0.F0.C1.F0.F2.C2.F3.F3.C3 F0.F0.C1.F0.F2.C2.F3.F3.C3



* Address Contents

0159 00.00.00 (align)Exercise 267: SIMBZZ DC A(0) 015C 00.00.00.00Exercise 268: SIMBAA DC A(127) 0160 00.00.00.7FExercise 269: SIMBBB DC A(X'8000') 0164 00.00.80.00Exercise 270: SIMBCC DC A(B'1111') 0168 00.00.00.0FExercise 271: SIMBDD DC A(C'*') 016C 00.00.00.5CExercise 272: SIMBEE DC A(*) 0170 00.00.01.70Exercise 273: SIMBFF DS CL17 0174 ??.??.??.??.??.??.??.??.?? ??.??.??.??.??.??.??.?? 0185 00.00.00 (align)Exercise 274: SIMBGG DC A(*) 0188 00.00.01.88Exercise 275: SIMBHH DC A(SIMBGG) 018C 00.00.01.88Exercise 276: SIMBII DC A(SIMBAA+12) 0190 00.00.01.6CExercise 277: SIMBJJ DC A(SIMBII-SIMBBB) 0194 00.00.00.2C Exercise 278: SIMBKK DC AL1(*-SIMBKK) 0198 00Exercise 279: SIMBLL DC 5AL1(*-SIMBLL) 0199 00.01.02.03.04



* Endereço Conteúdo

Exercise 280: SIMBMM DC AL2(3,5,7) 019E 00.03.00.05.00.07 Exercise 281: SIMBNN DC A(SIMBII+5*2) 01A4 00.00.01.9A Exercise 282: SIMBOO DC A(SIMBNN+X'80000000') 01A8 80.00.01.A4Exercise 283: SIMBPP DC 4AL2(*-SIMBPP) 01AC 00.00.00.02.00.04 00.06Exercise 284: SIMBQQ DC A(SIMBVV) 01B4 00.00.01.D8Exercise 285: SIMBRR DC A(SIMBKK,SIMBJJ) 01B8 00.00.01.98 00.00.01.94 Exercise 286: SIMBSS DC A(SIMBTT+40) 01C0 00.00.01.ECExercise 287: SIMBTT DC A(SIMBUU,*,80) 01C4 00.00.01.D0 00.00.01.C8 00.00.00.50 Exercise 288: SIMBUU DC 2A(*-SIMBUU) 01D0 00.00.00.00 00.00.00.04Exercise 289: SIMBVV DC A(C'AMO') 01D8 00.C1.D4.D6Exercise 290: SIMBWW DC A(X'7FFFFFFF') 01DC 7F.FF.FF.FF



* Address Contents

Exercise 291: YY1 DC Y(SIMBWW) 01E0 01.DCExercise 292: YY2 DC Y(10) 01E2 00.0AExercise 293: YY3 DC Y(L'YY2) 01E4 00.02Exercise 294: SS1 DC S(SIMBAA) 01E6 91.60 Exercise 295: SS2 DC S(SS1) 01E8 91.E6Exercise 296: SS3 DC S(10) 01EA 00.0A Exercise 297: SS4 DC S(*) 01EC 91.EC 01EE 00.00 (align) Exercise 298: SS5 DC A(125),F'33',C'*',2H'6,18' 01F0 00.00.00.7D 00.00.00.21 5C 00 (align) 00.06.00.12 00.06.00.12 Exercise 299: SS6 DC X'1,1',B'1,1',C'1,1' 0202 01.01.01.01 F1.6B.F1


(A) Exercise 300 (Representing fields in bytes)

* Endereço Conteúdo

Exercise 300: LAST DC 256AL1(255+LAST-*) 0209 FF.FE.FD.FC.FB.FA.F9.F8.F7.F6.F5.F4.F3.F2.F1.F0* 0219 EF.EE.ED.EC.EB.EA.E9.E8.E7.E6.E5.E4.E3.E2.E1.E0* 0229 DF.DE.DD.DC.DB.DA.D9.D8.D7.D6.D5.D4.D3.D2.D1.D0* 0239 CF.CE.CD.CC.CB.CA.C9.C8.C7.C6.C5.C4.C3.C2.C1.C0* 0249 BF.BE.BD.BC.BB.BA.B9.B8.B7.B6.B5.B4.B3.B2.B1.B0* 0259 AF.AE.AD.AC.AB.AA.A9.A8.A7.A6.A5.A4.A3.A2.A1.A0* 0269 9F.9E.9D.9C.9B.9A.99.98.97.96.95.94.93.92.91.90* 0279 8F.8E.8D.8C.8B.8A.89.88.87.86.85.84.83.82.81.80* 0289 7F.7E.7D.7C.7B.7A.79.78.77.76.75.74.73.72.71.70* 0299 6F.6E.6D.6C.6B.6A.69.68.67.66.65.64.63.62.61.60* 02A9 5F.5E.5D.5C.5B.5A.59.58.57.56.55.54.53.52.51.50* 02B9 4F.4E.4D.4C.4B.4A.49.48.47.46.45.44.43.42.41.40* 02C9 3F.3E.3D.3C.3B.3A.39.38.37.36.35.34.33.32.31.30* 02D9 2F.2E.2D.2C.2B.2A.29.28.27.26.25.24.23.22.21.20* 02E9 1F.1E.1D.1C.1B.1A.19.18.17.16.15.14.13.12.11.10* 02F9 0F.0E.0D.0C.0B.0A.09.08.07.06.05.04.03.02.01.00


(A) Exercise 301 (Decoding instructions)

Exercise 301 : Decode the following set of instructions1ABB41278CF00A13980F334445E00CB490EC0D00FA82305448CCD28233445566----////////----////////--------////////------------////////////

Suppose the general registers with the following values:

R00=00112233 R04=00000400 R08=00000800 R12=00000C00R01=00000100 R05=00000500 R09=00000900 R13=00000D00R02=00000200 R06=00000600 R10=00000A00 R14=00000E00R03=00000300 R07=00000700 R11=00000B00 R15=00000F00



Exercise 301 : Decode the following set of instructions1ABB41278CF00A13980F334445E00CB490EC0D00FA82305448CCD28233445566----////////----////////--------////////------------////////////1ABB - Operation code (machine code) = 1A- Mnemonic Assembler code = AR (add register)- Instruction address = X’00000000’- Operands = 1st operand = register 11; 2nd operand = register 11

41278CF0 - Operation code (machine code) = 41- Mnemonic Assembler code = LA (load address)- Instruction address = X’00000002’-Operands = 1st operand = register 2; 2nd operand : index register = register 7 2nd operand : base register = register 8

2nd operand : displacement = X’CF0’ 2nd operand address = X’ 00000700’+X’00000800’+X’CF0’= X’00001BF0’

Continues...



Exercise 301 : Decode the following set of instructions1ABB41278CF00A13980F334445E00CB490EC0D00FA82305448CCD28233445566----////////----////////--------////////------------////////////0A13 - Operation code (machine code) = 0A- Mnemonic Assembler code = SVC (supervisor call)- Instruction address = X’00000006’- Operands = supervisor call code = X’13’ = (19)10 = open

980F3344 - Operation code (machine code) = 98- Mnemonic Assembler code = LM (load multiple)- Instruction address = X’00000008’-Operands = 1st operand = register 0; 3rd operand : register = register 15 (X’F’) 2nd operand : base register = register 3

2nd operand : displacement = X’344’ 2nd operand address = X’00000300’+X’344’= X’00000644’

Continues...



Exercise 301 : Decode the following set of instructions1ABB41278CF00A13980F334445E00CB490EC0D00FA82305448CCD28233445566----////////----////////--------////////------------////////////45E00CB4 - Operation code (machine code) = 45- Mnemonic Assembler code = BAL (branch and link)- Instruction address = X’0000000C’-Operands = 1st operand = register 14 (X’E’); 2nd operand : index register = register 0 2nd operand : base register = register 0; 2nd operand : displacement = X’CB4’

2nd operand address = X’CB4’= X’00000CB4’

90EC0D00 - Operation code (machine code) = 90- Mnemonic Assembler code = STM (store multiple)- Instruction address = X’00000010’-Operands = 1st operand = register 14 (X’E’); 3rd operand : register = register 12 (X’C’) 2nd operand : base register = register 0; 2nd operand : displacement = X’D00’

2nd operand address = X’D00’= X’00000D00’ Continues...



Exercise 301 : Decode the following set of instructions1ABB41278CF00A13980F334445E00CB490EC0D00FA82305448CCD28233445566----////////----////////--------////////------------////////////FA82305448CC - Operation code (machine code) = FA- Mnemonic Assembler code = AP (add packed)- Instruction address = X’00000014’- 1st operand length = 9 bytes; 1st operand base register = register 3; 1st operand displacement= X’054’; 1st operand address= X’00000300’+X’054’ = X’00000354’- 2nd operand length = 3 bytes; 2nd operand base register = register 4; 2nd operand displacement = X’8CC’; 2nd operand address= X’00000400’+X’8CC’ = X’00000CCC’

D28233445566 - Operation code (machine code) = D2- Mnemonic Assembler code = MVC (move character)- Instruction address = X’0000001A’- 1st operand length = 131 bytes; 1st operand base register = register 3; 1st operand displacement= X’344’; 1st operand address= X’00000300’+X’344’ = X’00000644’- 2nd operand length = 131 bytes; 2nd operand base register = register 5; 2nd operand displacement = X566’; 2nd operand address= X’00000500’+X’566’ = X’00000A66’


Programming Hints

Programming Hints


Programming Hints

Interesting things,

useful things, awful

but used things, etc...


Programming Hints

1 base register load

PROG START 0 USING *,3 LR 3,15 LOAD FIRST AND ONLY BASE REGISTER* REG 3 CONTAINS THE ENTRY POINT ADDRESS* THIS TYPE OF LOAD (WITH LR) IS OFTEN USED IN MVS

PROG START 0 USING *,3 BALR 3,0 LOAD INTO R3 THE ADDRESS JUST AFTER BALR BCTR 3,0 SUBTRACTS 1 BCTR 3,0 SUBTRACTS 1 ONCE MORE* HERE REGISTER 3 IS OK; * IT HAS THE ENTRY POINT ADDRESS


Programming Hints

2 base registers load

PROG START 0 USING *,3,4 LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,4096(4) LOAD INTO R4 THE VALUE OF R3 + 4096

NO! Why not? Because maximum displacement is 4095 (X’FFF’) !!!Assembly error !

May I do this way?


Programming Hints


PROG START 0 USING *,3,4 LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,1 LOAD NUMBER 1 INTO REG 4 LA 4,4095(4) ADD 4095 * RESULT = 4096 AR 4,3 ADD ENTRY POINT. * R4 CONTENTS = ENTRY POINT + 4096 * OR ENTRY POINT + X’001000’ * OK ! R3 AND R4 PROPERLY LOADED !

You may do this way...


Programming Hints


PROG START 0 USING *,3,4 LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,4095 LOAD NUMBER 4095 INTO REG 4 LA 4,1(4) ADD 1* RESULT = 4096 AR 4,3 ADD ENTRY POINT. * R4 CONTENTS = ENTRY POINT + 4096 * OR ENTRY POINT + X’001000’ * OK ! R3 AND R4 PROPERLY LOADED !

Or that way...


Programming Hints


PROG START 0 USING *,3,4 LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,1 LOAD NUMBER 1 INTO REG 4 LA 4,4095(3,4) ADD 4095 + ENTRY POINT* R4 CONTENTS = ENTRY POINT + 4096 * OR ENTRY POINT + X’001000’ * OK ! R3 AND R4 PROPERLY LOADED !

Even this way...


Programming Hints


PROG START 0 USING *,3,4 LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,2048 LOAD NUMBER 1 INTO REG 4 LA 4,2048(3,4) ADD 2048 + ENTRY POINT* R4 CONTENTS = ENTRY POINT + 4096 * OR ENTRY POINT + X’001000’ * OK ! R3 AND R4 PROPERLY LOADED !

You may do like this...


Programming Hints


PROG START 0 USING *,3,4 LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,1000 CARREGA NRO 1000 NO REG 4 LA 4,3096(3,4) SOMA 3096 + ENTRY POINT* R4 CONTENTS = ENTRY POINT + 4096 * OR ENTRY POINT + X’001000’ * OK ! R3 AND R4 PROPERLY LOADED !

Or like this...


Programming Hints


PROG START 0 USING *,3,4 LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,PROG+4096 LOAD “DIRECTLY” ENTRY POINT + 4096

Is it correct?

NO! Why not?Because the address PROG+40096 isn’t in the range of first base register (R3), so far the only one correctly loaded. Assembly error.


Programming Hints


PROG START 0 USING *,3,4 LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS L 4,=A(PROG+4096) CARREGA “DIRETO” ENTRY POINT + 4096

And about this way?

IT DEPENDS ON ... ! The contents of the literal is being loaded into R4.If the literal is outside the range of the FIRST BASE REGISTER (R3) (THE ONLY ONE CORRECTLY LOADED SO FAR), THEN this is INVALID to prepare the second base register. Assembly error. (case 1) ELSE, this way (using the literal) is VALID. (case 2)


Programming Hints

2 base registers loadCASE 1 : Literal is outside range of the 1st base register (R3), and it is the only one prepared so far. You can’t do this way ! Assembly error.

PROG START 0 USING *,3,4 LR 3,15 L 4,=A(PROG+4096) ... ( L needs the 2nd base register prepared, but... L prepares the 2nd base register! Execution time error!)

END ( literals are declared after END)

... =A(PROG+4096)

Program = 8k

This part is served by 1st base register

This part is served by 2nd base register


Programming Hints

2 base registers loadCASE 2 : Literal is in the range of the first base register (R3), and it is the only one prepared so far, so you can do this way.

PROG START 0 USING *,3,4 LR 3,15 L 4,=A(PROG+4096) B SKIP LTORG =A(PROG+4096) SKIP ...

END (other literals declared here)

... =... =...

Program = 8k

This part is served by 1st base register

Forces the literal to be

defined here.

This part is served by 2nd base register


Complete Developed Programs

Complete developed programs



PGMTSE01



PGMTSE01 START 0 NO BASE REGISTER REQUIRED !

LA 15,0 LOAD RETURN CODE INTO REG 15

BR 14 BYE BYE ...

END



PGMTSE02



PGMTSE02 START 0 * DUE TO THE LITERAL, A BASE REGISTER IS NEEDED * THE ADDRESS OF THE LITERAL MUST BE CONVERTED TO BASE+DISPLACEMENT* IN THE L INSTRUCTION. * INICIALIZATION ---------------------------------------------------- USING *,15 INDICATES BASE REGISTER AND ITS * PRESUMED VALUE AT EXECUTION TIME * NOTE THAT BASE REGISTER 15 IS ALREADY * LOADED WITH ENTRY POINT BY THE * OPERATING SYSTEM * FINALIZATION ------------------------------------------------------ L 15,=F'0' RETURN CODE INTO REG 15 * WOW! * IN THE SAME INSTRUCTION ( L ) REG 15 IS USED TO ADDRESS THE LITERAL * AND IT HAD BEEN LOADED WITH ZERO. * SO, THE VALUE USED AS BASE VALUE IN THE BASE REGISTER IS DESTROYED. * IF ONLY 1 MORE INSTRUCTION NEED A BASE REGISTER READY, NO ONE * IS OK BR 14 BYE BYE ... END



PGMTSE03



PGMTSE03 START 0 * INICIALIZATION----------------------------------------------------- USING *,3 REG 3 IS THE BASE REGISTER * AND ITS PRESUMED VALUE AT EXECUTION TIME IS THE ENTRY POINT LR 3,15 LOAD ENTRY POINT INTO BASE REGISTER * BASE REGISTER OK. * FINALIZATION ------------------------------------------------------ L 15,=F'0' RETURN CODE INTO REG 15 BR 14 BYE BYE ... END



PGMTSE04



PGMTSE04 START 0 * INICIALIZATION ---------------------------------------------------- USING *,3,4,5,6,7 BASE REGISTERS ARE 3,4,5,6 AND 7 * PRESUMED CONTENTS AT RUN TIME: * REG 3 = ENTRY POINT * REG 4 = ENTRY POINT + X'1000' * REG 5 = ENTRY POINT + X'2000' * REG 6 = ENTRY POINT + X'3000' * REG 7 = ENTRY POINT + X'4000' STM 14,12,12(R13) SAVE REGISTERS INTO CALLER' SAVEAREA* LOAD BASE REGISTERS LR 3,15 LOAD ENTRY POINT INTO R3 LA 4,1 LOAD #1 INTO R4 LA 4,1 LOAD #1 INTO R4 LA 4,4095(3,4) R4 = R3 + X'1000' * LINKAGE CONVENTIONS LA 15,SAVEZZZZ LOAD MY SAVEAREA ADDRESS INTO 15 ST 15,8(13) SAVE MY SAVEAREA ADDRESS INTO * CALLER'S SAVEAREA LR 13,15 LOAD R13 WITH MY SAVEAREA ADRS * EXECUTE PROGRAM ----------------------------------------------------



OPEN (RELAT,OUTPUT) OPEN PRINT FILE MVC LINGERAL,=CL133' HELLO WORLD' MOVE MESSAGE PUT RELAT,LINGERAL PRINT LINE CLOSE (RELAT) CLOSE PRINT FILE * FINALIZATION ------------------------------------------------------ L 2,=F'0' RETURN CODE INTO R2 L 13,SAVEZZZZ+4 RESTORE CALLER SAVEAREA ADDRESS ST 2,16(13) RET CODE INTO R15 RESTORE AREA LM 14,12,12(13) RESTORE REGISTERS BR 14 BYE BYE ... *----------------------------------------------------------- * AREAS AND DATASETS *----------------------------------------------------------- RELAT DCB LRECL=133,DSORG=PS,RECFM=FA,DDNAME=SYSPRINT,MACRF=PM LINGERAL DC CL133' ' PRINT LINE *--------------------------------- END , LAST SOURCE STATEMENT



PGMTSE05



PGMTST05 START 0 * REGISTER EQUATES SO THAT THEY APPEAR AT THE CROSS REFERENCE -------R0 EQU 0 R1 EQU 1 R2 EQU 2 R3 EQU 3 R4 EQU 4 R5 EQU 5 R6 EQU 6 R7 EQU 7 R8 EQU 8 R9 EQU 9 R10 EQU 10 R11 EQU 11 R12 EQU 12 R13 EQU 13 R14 EQU 14 R15 EQU 15



* INICIALIZING ------------------------------------------------------ USING *,R3,R4,R5,R6,R7 INDICATE BASE REGISTERS AND ITS * PRESUMED CONTENTS AT EXECUTION STM R14,R12,12(R13) SAVE REGISTERS IN CALLER' * SAVEAREA * LOAD BASE REGISTERS LR R3,R15 LOAD R3 WITH ENTRY POINT LA R4,1 LOAD R4 WITH 1 LA R4,4095(R3,R4) R4 = R3 + 4096 LA R5,1 LOAD R5 WITH 1 LA R5,4095(R4,R5) R5 = R4 + 4096 LA R6,1 LOAD R6 WITH 1 LA R6,1 LOAD R6 WITH 1 LA R6,4095(R5,6) R6 = R5 + 4096 LA R7,1 LOAD R6 WITH 1 LA R7,4095(R6,R7) R7 = R6 + 4096 * ADJUST POINTERS TO SAVEAREAS---------------------------------------- ST R13,SAVEZZZZ+4 SAVE CALLER SAVEAREA'S ADDRESS * IN MY SAVEAREA LA R15,SAVEZZZZ LOAD R15 WITH MY SAVEAREA ADDRS ST R15,8(R13) SAVE MY SAVEAREA'S ADDRESS * IN CALLER'S SAVEAREA LR R13,R15 LOAD R13 WITH MY SAVEAREA ADDRS



EX R15,*+4+4 SAVE PARM IN MY AREA * BY EXECUTING THE MVC BELLOW B PARMLEN@+4 GO EXECUTE THE PROGRAM MVC PARMTEXT(0),2(R1) MOVE PARM TO MY AREA * DEFINE INITIALIZATION AREA SAVEZZZZ DC 18F'0' MY SAVEAREA PARMTEXT DC CL100' ' MY PARM AREA PARMLEN@ DC F'0' PARM LENGTH * EXECUTES THE PROGRAM BAL R14,ROTMAIN WHOLE PROGRAM (EXCEPT INIT) * FINALIZATION ------------------------------------------------------ L R2,=F'22' LOAD R2 WITH RETURN CODE L R13,SAVEZZZZ+4 RESTORE CALLER'S SAVEAREA ST R2,16(R13) STORE RETURN CODE WHERE R15 * WILL BE LOADED FROM LM R14,R12,12(R13) RESTORE REGISTERS BR R14 BYE BYE ... *----------------------------------------------------------- * ROUTINES *-----------------------------------------------------------



*--------------------------------- * ROTMAIN *--------------------------------- DC A(0) RETURN ADDRESS ROTMAIN ST R14,*-4 SAVE RETURN ADDRESS * GET INTO AND DO WHAT I HAVE TO DO OPEN (RELAT,OUTPUT) OPEN FILE MVC LINGERAL,=CL133' HELLO WORLD' MOVE MESSAGE BAL R14,IMPLIN PRINT LINE WITH ABOVE MESSAGE MVC LINGERAL+1(25),=C'TAMANHO PARM INFORMADO = ' MOVE MSG L R14,PARMLEN@ LOAD R14 WITH PARM LENGTH CVD R14,WDOUBLE CONVERT IT TO PACKED DECIMAL UNPK LINGERAL+26(3),WDOUBLE CONVERT IT TO ZONED DECIMAL OI LINGERAL+28,X'F0' FORCE ZONE F BAL R14,IMPLIN PRINT LINE WITH PARM LENGTH MVC LINGERAL+1(18),=C'PARM INFORMADO = ' MESSAGE MVC LINGERAL+19(100),PARMTEXT PARM TEXT BAL R14,IMPLIN PRINT LINE WITH PARM TEXT CLOSE (RELAT) CLOSE FILE * EXIT ROUTINE L R14,ROTMAIN-4 RESTORE RETURN ADDRESS BR R14 RETURN



*--------------------------------- * PRINT A LINE *--------------------------------- DC A(0) RETURN ADDRESS IMPLIN ST R14,*-4 SAVE RETURN ADDRESS PUT RELAT,LINGERAL PRINT LINE MVC LINGERAL,=CL133' ' CLEAR LINE AP LINS,=P'1' UPDATE LINE COUNTER L R14,IMPLIN-4 RESTORE RETURN ADDRESS BR R14 RETURN *----------------------------------------------------------- * DECLARE FILES AND AREAS *----------------------------------------------------------- * FILES RELAT DCB LRECL=133,DSORG=PS,RECFM=FA,DDNAME=SYSPRINT,MACRF=PM* AREAS WDOUBLE DC D'0' DOUBLE FOR WORK LINGERAL DC CL133' ' PRINT LINE LINS DC PL4'0' LINE COUNTER *--------------------------------- END , LAST SOURCE STMT



PGMTSE06The input file has the following contents:From To Position Position Length Description01 04 04 Branch code05 34 30 Branch name35 54 20 Branch address55 67 13 Branch balance68 80 23 (no info)

The output lines must be as following :From To Position Position Length Description01 04 04 Branch code05 06 02 Spaces07 36 30 Branch name37 37 01 Spaces38 57 20 Branch address58 59 02 Spaces60 72 13 Branch balance73 132 60 Spaces

This program reads an input file, and for each record read, it prints a detail line



PGMTSE06 START 0 * REGISTER EQUATES SO THAT THEY APPEAR AT THE CROSS REFERENCE -------R0 EQU 0 R1 EQU 1 R2 EQU 2 R3 EQU 3 R4 EQU 4 R5 EQU 5 R6 EQU 6 R7 EQU 7 R8 EQU 8 R9 EQU 9 R10 EQU 10 R11 EQU 11 R12 EQU 12 R13 EQU 13 R14 EQU 14 R15 EQU 15



* INICIALIZING ------------------------------------------------------ USING *,R3,R4,R5,R6,R7 INDICATE BASE REGISTERS AND ITS* PRESUMED CONTENTS AT EXECUTION STM R14,R12,12(R13) SAVE REGISTERS IN CALLER' * SAVEAREA * LOAD BASE REGISTERS LR R3,R15 LOAD R3 WITH ENTRY POINT LA R4,1 LOAD R4 WITH 1 LA R4,4095(R3,R4) R4 = R3 + 4096 LA R5,1 LOAD R5 WITH 1 LA R5,4095(R4,R5) R5 = R4 + 4096 LA R6,1 LOAD R6 WITH 1 LA R6,4095(R5,6) R6 = R5 + 4096 LA R7,1 LOAD R6 WITH 1 LA R7,4095(R6,R7) R7 = R6 + 4096 * ADJUST POINTERS TO SAVEAREAS---------------------------------------- ST R13,SAVEZZZZ+4 SAVE CALLER SAVEAREA'S ADDRESS * IN MY SAVEAREA LA R15,SAVEZZZZ LOAD R15 WITH MY SAVEAREA ADDRS ST R15,8(R13) SAVE MY SAVEAREA'S ADDRESS * IN CALLER'S SAVEAREA LR R13,R15 LOAD R13 WITH MY SAVEAREA ADDRS



* TAKE PARM AND LET IT IN PARMTEXT------------------------------------ L R1,0(R1) LOAD R1 WITH PARM ADDRESS MVC PARMLEN@+2(2),0(R1) SAVE PARM LENGTH L R15,PARMLEN@ LOAD R15 WITH PARM LENGTH LTR R15,R15 IS THERE PARM? BZ PARMLEN@+4 IF LENGTH ZERO, NO PARM CAME BCTR R15,R0 SUBTRACT 1 FROM R15 EX R15,*+4+4 SAVE PARM IN MY AREA B PARMLEN@+4 GO EXECUTE THE PROGRAM MVC PARMTEXT(0),2(R1) MOVE PARM TO MY AREA * DEFINE INITIALIZATION AREAS SAVEZZZZ DC 18F'0' MY SAVEAREA PARMTEXT DC CL100' ' MY PARM AREA PARMLEN@ DC F'0' PARM LENGTH * EXECUTES THE PROGRAM BAL R14,ROTMAIN WHOLE PROGRAM (EXCEPT INIT) * FINALIZATION ---------------------------------------------------- L R2,=F'0' LOAD R2 WITH RETURN CODE L R13,SAVEZZZZ+4 RESTORE CALLER'S SAVEAREA ST R2,16(R13) STORE RETURN CODE LM R14,R12,12(R13) RESTORE REGISTERS BR R14 BYE BYE ...



*----------------------------------------------------------- * ROUTINES *----------------------------------------------------------- *--------------------------------- * ROTMAIN *--------------------------------- DC A(0) RETURN ADDRESS ROTMAIN ST R14,*-4 SAVE RETURN ADDRESS * GET INTO AND DO WHAT I HAVE TO DO OPEN (BRANCHES,INPUT) OPEN FILE OPEN (REPOR,OUTPUT) OPEN FILE RDAGAIN BAL 14,READREC READ AN INPUT FILE RECORD BAL R14,PROCREC PROCESS THE RECORD B RDAGAIN BACK TO READ ENDRECS CLOSE (REPOR) CLOSE OUTPUT FILE CLOSE (BRANCHES) CLOSE INPUT FILE * EXIT ROUTINE L R14,ROTMAIN-4 RESTORE RETURN ADDRESS BR R14 RETURN



*--------------------------------- * PRINT A LINE *--------------------------------- DC A(0) RETURN ADDRESS PRILINE ST R14,*-4 SAVE RETURN ADDRESS PUT REPOR,DETLINE PRINT LINE MVC DETLINE,=CL133' ' CLEAR LINE L R14,PRILINE-4 RESTORE RETURN ADDRESS BR R14 RETURN *--------------------------------- * READ A RECORD *--------------------------------- DC A(0) RETURN ADDRESS READREC ST R14,*-4 SAVE RETURN ADDRESS GET BRANCHES,LRECAREA READ A LOGICAL RECORD L R14,READREC-4 RESTORE RETURN ADDRESS BR R14 RETURN



*--------------------------------- * PROCESS A RECORD *--------------------------------- DC A(0) RETURN ADDRESS PROCREC ST R14,*-4 SAVE RETURN ADDRESS MVC DETLINE+1(4),LRECAREA MOVE BRANCH CODE MVC DETLINE+7(30),LRECAREA+4 MOVE BRANCH NAME MVC DETLINE+38(20),LRECAREA+34 MOVE BRANCH ADDRESS MVC DETLINE+60(13),LRECAREA+54 MOVE BRANCH BALANCE BAL R14,PRILINE PRINT DETAIL LINE L R14,PROCREC-4 RESTORE RETURN ADDRESS BR R14 RETURN *----------------------------------------------------------- * DECLARE FILES AND AREAS *----------------------------------------------------------- * FILES REPOR DCB LRECL=133,DSORG=PS,RECFM=FA,DDNAME=SYSPRINT,MACRF=PM BRANCHES DCB LRECL=80,DSORG=PS,DDNAME=BRANCHES,MACRF=GM,EODAD=ENDRECS* AREAS WDOUBLE DC D'0' DOUBLE FOR WORK LRECAREA DC CL80' ' LOGICAL RECORD INPUT AREA DETLINE DC CL133' ' DETAIL LINE *--------------------------------- END , LAST SOURCE STMT



If the input file is an in-stream data file with this records (the ruler in blue is just to facilitate the visualization): 1 2 3 4 5 6 7 1234567890123456789012345678901234567890123456789012345678901234567890 0001BRANCH 0001 NAME ------------*BRANCH 0001 ADDRESS*00000000000010002BRANCH 0002 NAME ------------*BRANCH 0002 ADDRESS*00000000000020003BRANCH 0003 NAME ------------*BRANCH 0003 ADDRESS*00000000000030004BRANCH 0004 NAME ------------*BRANCH 0004 ADDRESS*00000000000040005BRANCH 0005 NAME ------------*BRANCH 0005 ADDRESS*0000000000005

The output produced is the following (the ruler in blue is just to facilitate the visualization): 1 2 3 4 5 6 7 123456789012345678901234567890123456789012345678901234567890123456789012 0001 BRANCH 0001 NAME ------------* BRANCH 0001 ADDRESS* 00000000000010002 BRANCH 0002 NAME ------------* BRANCH 0002 ADDRESS* 00000000000020003 BRANCH 0003 NAME ------------* BRANCH 0003 ADDRESS* 00000000000030004 BRANCH 0004 NAME ------------* BRANCH 0004 ADDRESS* 00000000000040005 BRANCH 0005 NAME ------------* BRANCH 0005 ADDRESS* 0000000000005



PGMTSE07



PGMTSE08



PGMTSE09


THE END

machine instructions

Documents