lect10 combinational circuits
TRANSCRIPT
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TA C162
Lecture 10 Combinational Circuits
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Todays AgendaCombinational Circuit Examples
Multiplexer
PLA
Tuesday, February 02, 2010 2Biju K Raveendran@BITS Pilani.
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Combinational Logic Structures
Full Adder
Multiplexer (MUX)
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Adding two bits: Half AdderTruth Table:A B Sum Carry
0 0 0 00 1 1 0
1 0 1 0
Boolean Expressions
C = A AND B
4
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Adding Three Bits: Full Adder4-Bit Full Adder
Requirement: Adds the two bits and a carry
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Full Adder: Truth TableA B Cin S Cout0 0 0 0 0
0 1 0 1 0
1 0 0 1 0
1 1 0 0 1
SOP for Sum S = A.B.C + A.B.C + A.B.C + A.B.C
= . . . . . . . .
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Full Adder Logic Implementation
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Combinational Circuit Example 2Requirement:n-bit selector and 2n in uts one out ut
Output equals one of the inputs, depending onselecto A B
Selection bits = 1
In uts =2 A0 A1 S
Output is according to the table
0 A0
O 8
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Truth TableS A1 A0 Y
SOP Expression for Y???
=
0 0 0 00 0 1 1
. . . . . . . .
0 1 0 0
0 1 1 1
1 0 0 0Lets draw the circuit !!!
1 1 0 1 It is called as Multiplexer!!!
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4 x 1 MUX Circuit Diagram
-t -1MUX
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Multiplexer Many (2N) inputs are connected to one output Uses select lines (N-bits) to determine which
input is connected to the output. De endin on select lines (N-bits), one of the
2N inputs are transferred to output.
MUX Abbreviation of multi lexer consists of2N input lines, N select lines and 1 output line
Example: 2:1 MUX will have 2 input lines, 1 select
line and 1 output line
Example 16:1 MUX will have 16 input lines, 4se ect nes an output ne
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Demultiplexer ne nput s connecte to any outputs
Uses select lines (N-bits) to determine whichou pu s connec e o e npu .
Depending on select lines (N-bits), input is.
DeMUX or DMUX(Abbreviation of demultiplexer),output lines
line and 2 output lines
Example 1:16 DEMUX will have 1 input line, 4 selectlines and 16 output lines
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1:8 demulti lexer
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Combinational Circuit Example 3Lets design a circuit, that takes an n-bit binary
output lines.
,
Exactly one output is 1 for each possible input
Example:
e n = npu s en ou pu s Bit patterns are 00 01 10 11
a e as Deco er !!!
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What a decoder does?The n inputs represent a binary number that determines which ofthe 2
noutputs is uniquely true.
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The 2-bit input (S1,S0), and four outputs (A0, A1, A2, A3).
If S1 S0 =00 decimal 0 then out ut A0 is true and A1A2, A3 are all false.
If (S1 S0) = 01, then A1 is true & all other outputs false If (S1 S0) = 10, then A2 is true & all other outputs false
If (S1 S0) = 11, then A3 is true & all other outputs false
This circuit decodes a binary number into a one-of-fourcode.
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Decoder
Exactly one of its outputs is 1 and all the rest
One output which is 1corresponds to the
detect
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How can you build a 2-to-4 decoder?
We have a truth table, so we can write equations for each- -,
S1).
S1 S0 A0 A1 A2 A3
0 0 1 0 0 0
A0= S1 S0
A1 = S1 S0
0 1 0 1 0 0
1 0 0 0 1 0
A2= S1 S0
A3= S1 S0
1 1 0 0 0 1
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2-to-4 decoder
S1 S0 A0 A1 A2 A30 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
A0=S1.S0
A1=S1.S0
A2=S1.S0
.
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Decoder
N
Outputi is 1 iff the binary value of the N-bit
At any time, exactly one output is 1, all others
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PLA y
Used for implementing any collection of logic
Consists of an array of AND gates (called ANDarra followed b an arra of OR ates called ORarray)
Number of AND gates corresponds to the number ofinput combinations (rows) in truth table for which atleast one of the output is 1
, Number of OR gates corresponds to the number of
out ut columns in the truth table
Tuesday, February 02, 2010 20Biju K Raveendran@BITS Pilani.