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An Ultra Low Power Voltage Reference using Charge-pump and

Switched Capacitor Network

A Thesis Presented

by

Shikhar Tewari

to

The Department of Electrical and Computer Engineering

in partial fulfillment of the requirements

for the degree of

Master of Science

in the field of

Electrical and Computer Engineering

Northeastern University

Boston, Massachusetts

August 2018

To my family and friends.

i

Contents

List of Figures iv

List of Tables vi

Acknowledgments vii

Abstract of the Thesis viii

1 Introduction 11.1 Ultra low power for IoT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1.1 Power management Techniques for Ultra low power consumption . . . . . 21.1.2 Applications of voltage reference in an SoC . . . . . . . . . . . . . . . . . 2

1.2 Standard specifications for a reference voltage . . . . . . . . . . . . . . . . . . . . 41.2.1 Temperature Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.2.2 Power Supply Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.2.3 Variation across Process . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.2.4 Output Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3 Principle of voltage reference circuit design . . . . . . . . . . . . . . . . . . . . . 51.4 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.5 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Review of the Literature 92.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.2 State-of-the-art voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.1 Conventional bandgap voltage reference . . . . . . . . . . . . . . . . . . 102.2.2 Sub-bandgap voltage reference . . . . . . . . . . . . . . . . . . . . . . . 12

2.3 Low power bandgap voltage references . . . . . . . . . . . . . . . . . . . . . . . . 142.3.1 MOSFET based sub-bandgap voltage references . . . . . . . . . . . . . . 142.3.2 BJT based sub-bandgap voltage references . . . . . . . . . . . . . . . . . 19

3 An Ultra Low Power voltage reference using Charge-pump 223.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.2 Charge-pump based VEB generation . . . . . . . . . . . . . . . . . . . . . . . . . 233.3 Switched capacitor network for ∆VEB generation . . . . . . . . . . . . . . . . . . 24

ii

3.3.1 B × ∆VEB generation circuit . . . . . . . . . . . . . . . . . . . . . . . . 253.4 Reference voltage generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.4.1 K × VEB generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . 283.4.2 Summing CTAT and PTAT voltages . . . . . . . . . . . . . . . . . . . . . 293.4.3 Top level implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.5 Improved version of charge-pump based BGR . . . . . . . . . . . . . . . . . . . . 333.5.1 Improving Power Supply variation . . . . . . . . . . . . . . . . . . . . . . 333.5.2 Improving temperature variation . . . . . . . . . . . . . . . . . . . . . . . 34

3.6 Reference Voltage scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353.6.2 Techniques for reference voltage scaling . . . . . . . . . . . . . . . . . . . 363.6.3 Switched capacitor based reference voltage scaling . . . . . . . . . . . . . 37

4 Implementation and Results 394.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394.2 Design of current source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394.3 Ring Oscillator and Clock doubler . . . . . . . . . . . . . . . . . . . . . . . . . . 414.4 Charge-pump and switched capacitor network . . . . . . . . . . . . . . . . . . . . 42

4.4.1 Trimming circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434.4.2 Temperature based trimming . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.5 Biasing circuit and Leakage compensation . . . . . . . . . . . . . . . . . . . . . . 444.6 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.6.1 Temperature and Supply Variation . . . . . . . . . . . . . . . . . . . . . . 454.6.2 Monte-Carlo Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . 474.6.3 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494.6.4 PSRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504.6.5 Temperature based trimming . . . . . . . . . . . . . . . . . . . . . . . . . 504.6.6 Post Layout Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5 Conclusion and Future Work 555.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Bibliography 57

A List of Publications 62

iii

List of Figures

1.1 A basic block diagram of an SoC powered with harvested energy . . . . . . . . . . 31.2 Operating principle of a bandgap voltage reference . . . . . . . . . . . . . . . . . 5

2.1 A conventional BGR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.2 Curvature in Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.3 Principle of the sub-1V reference . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.4 Banba bandgap voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.5 Sub-1V Bandgap Reference based on MOSFETs biased in weak inversion proposed

by G. Giustolisi et al . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.6 Simplified circuit of BGR proposed by proposed by G. De Vita et al . . . . . . . . 162.7 Sub-1V Bandgap Reference operational at 0.6V supply proposed by C. Huang et al 182.8 Sub-1V voltage Reference using BJT proposed by Y. Osaki et al . . . . . . . . . . 192.9 PTAT voltage generator used by architecture proposed by Oscar E. Mattia et al . . 202.10 Sub-1V voltage Reference using BJT and MOSFET proposed by Oscar E. Mattia et al 21

3.1 Charge-pump circuit for biasing BJT . . . . . . . . . . . . . . . . . . . . . . . . . 233.2 ∆VEB generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253.3 2 × ∆VEB generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263.4 B × ∆VEB generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263.5 Architecture for reference voltage generation using charge-pump and switched ca-

pacitor network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.6 K × VEB generator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.7 3 × VEB generation and summing circuit . . . . . . . . . . . . . . . . . . . . . . 293.8 Top level implementation of bandgap reference. . . . . . . . . . . . . . . . . . . . 303.9 Current starved ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313.10 Clock doubler circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323.11 Top level implementation of sub-bandgap reference . . . . . . . . . . . . . . . . . 333.12 Temperature based trimming scheme . . . . . . . . . . . . . . . . . . . . . . . . . 343.13 Resistive scaling of Voltage reference . . . . . . . . . . . . . . . . . . . . . . . . 363.14 Reference voltage scaling using switch-cap network . . . . . . . . . . . . . . . . . 373.15 Simulation result for the reference voltage scaling using switch-cap network . . . . 38

4.1 Circuit for PTAT current source . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404.2 Simulated PTAT current with 3σ variation . . . . . . . . . . . . . . . . . . . . . . 40

iv

4.3 Simulated frequency from the ring oscillator with 3σ variation . . . . . . . . . . . 414.4 Top level implementation of bandgap reference. . . . . . . . . . . . . . . . . . . . 424.5 Trimming circuit for process variation . . . . . . . . . . . . . . . . . . . . . . . . 434.6 Temperature based trimming circuit . . . . . . . . . . . . . . . . . . . . . . . . . 444.7 Variation of reference voltage Vref across temperature for different power supplies 454.8 Variation of reference voltage Vref across different power supplies at 400C . . . . . 464.9 Variation of reference voltage Vref across different power supplies for different tem-

perature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464.10 Monte-Carlo simulation of Vref for 500 points across temperature . . . . . . . . . 474.11 Variation in ppm/0C across 500 Monte-Carlo Simulation points . . . . . . . . . . . 484.12 Variation in Vref across 500 Monte-Carlo Simulation points at 400C and 600mV

supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484.13 Total current consumption across temperature for different supply voltages . . . . . 494.14 Distribution of power consumption at 600mV at 270C . . . . . . . . . . . . . . . . 494.15 PSRR of the voltage reference circuit . . . . . . . . . . . . . . . . . . . . . . . . . 504.16 Results for temperature based trimming . . . . . . . . . . . . . . . . . . . . . . . 514.17 Layout of the voltage reference circuit . . . . . . . . . . . . . . . . . . . . . . . . 524.18 Variation of VREF across temperature after post-layout simulations . . . . . . . . . 534.19 Variation of VREF across temperature after after trimming (post-layout) . . . . . . 53

v

List of Tables

4.1 Comparision Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

vi

Acknowledgments

I would first like to express my heartiest gratitude to my teacher, my mentor and my research advisor,Prof. Aatmesh Shrivastava. He accepted to guide me at a time when my circuit design knowledgewas at a nascent stage. In two years of association with him, he has given me several opportunitiesto learn and has worked really hard to nurture my skills. He has also been very understanding ofpersonal issues, like financial problems and has always been approachable whenever I went to himwith any problem. I am really inspired by his hardworking nature and his knowledge, and feel veryfortunate to be under his guidance.I would also like to acknowledge Professor Onabajo, and Professor Kim as the second readers ofthis thesis, and I am gratefully indebted to them for their very valuable comments on this thesis.I would also like to thank my group mates Nikita and Xu. We have spend numerous nights in thelab working together, and helped each other at every stage possible. I don’t think I could have foundbetter group-mates, and now friends, like you.In the end, I can’t thank enough for the love and support of my Maa, Papa, my brother Apratim andmy best friends, Gaurav and Vidhi. They have provided me with unfailing support and continuousencouragement throughout my years of study and through the process of researching. I have alwaysfelt better and cheerful after having long conversations with them. I believe this accomplishmentwould not have been possible without them.

vii

Abstract of the Thesis

An Ultra Low Power Voltage Reference using Charge-pump and Switched

Capacitor Network

by

Shikhar Tewari

Master of Science in Electrical and Computer Engineering

Northeastern University, August 2018

Prof. Aatmesh Shrivastava, Advisor

With millions of new Internet of Things (IoT) devices getting interconnected in the existingnetwork, operating IoT systems on harvested energy is the only feasible option to eliminate the costof millions of battery replacements. Operating IoT systems by harvesting energy from availableambient sources necessitate ultra low power (ULP) consumption of all new IoT systems, which aremade up of a number of different analog/mixed signal blocks. An essential element of all theseanalog/mixed signal blocks is a stable and precise voltage reference.

The thesis presents an ultra low power sub-bandgap voltage reference implemented in 130nmBiCMOS process. It consumes 32.8nW, and is operational from a 600mV supply. The design usescharge-pumps to bias parasitic Bipolar Junction Transistors (BJTs) and generate a reference volt-age at the output of a switched capacitor network. Use of BJTs ensures less drift in the referencevoltage across process corners when compared to other CMOS-only voltage references also con-suming ultra low power. The voltage reference of 500mV is achieved with a temperature variationof 46.7ppm/C, and PSRR (Power Supply Rejection Ratio) of -59dB at DC using current sourcearchitecture. The circuit has an area of 0.0436mm2. The design also incorporates trimming circuitsfor process variation and a temperature based trimming scheme to reduce the temperature varia-tion of the reference voltage. The thesis also presents a switched capacitor based reference voltagescaling circuit, to provide dynamic voltage scaling (DVS) capabilities.

viii

Chapter 1

Introduction

1.1 Ultra low power for IoT

Internet of Things (IoT) is a concept of connecting ‘Things’ or objects of everyday life to each other

using a network where they can communicate to each other, often including a central system. This

not only allows user to have easier and remote access to all of the ‘Things’ at once using the central

system, but also to a pool of data generated by these ‘Things’ or systems, which can be used to

improve their efficiency or even make them smart. There are thousands of diverse applications of

IoT which may include - a network of sensors in a farm which could be used to collect data about

temperature, humidity, and nutrients in the soil to improve productivity; a network of sensors fitted

to Oils and Gas pipelines which detects leaks and provide maintenance alerts; a system of Elec-

troencephalogram (EEG), Electrocardiogram (EKG) and Electromyogram (EMG) sensors which

broadcast real-time data of patients to hospitals so that it can be used to detect early signs of life

threatening events; and so many others.

Due to unlimited possible applications, IoT has attracted users not only from consumer space

but also from industrial space, leading to an exponential growth in number of connected systems

every passing year. To have consistent IoT support, it is important that these systems should be made

IoT compatible. Most of the times, these systems are deployed in remote locations, and hence need

to be either battery operated or have ability to run on harvested energy. However, as the number of

connected systems increase each year, running all IoT based systems on battery will become more

challenging. It is estimated that it may take up-to 274M battery replacement everyday, if all IoT

devices are powered by battery [1]. Operating IoT systems using harvesting energy from ambient

sources is a viable alternative to eliminate the requirement of battery replacements. However, energy

1

CHAPTER 1. INTRODUCTION

available through ambient sources in our environment is very low. Hence, one of the most important

feature of these systems should be that they should consume ultra low power (ULP).

1.1.1 Power management Techniques for Ultra low power consumption

Control over the power consumption in an System-on-Chip (SoC) for an IoT is important for its

performance and longer life. Since power harvested from ambient sources is very low, it is important

to have dynamic control on the power consumption of the SoC in time domain so as to have ability

to conserve power whenever possible. Many different techniques have been proposed which use

different methods to scale supply voltage and operating frequency. Power consumption in CMOS

designs can be divided into two parts - Dynamic (or switching) power and Leakage power, where

Dynamic power consumption can be expressed as

Powerdynamic = αCV 2DDf (1.1)

where α denotes the switching activity, VDD represents the operating supply voltage and f shows

the operating frequency. Thus, having control over supply voltage and frequency gives a third order

control over the dynamic power consumption. On the other hand, Leakage power consumption is

because of the sub-threshold conduction in transistors and can be expressed as

Powerleakage = Isub−threshold × VDD (1.2)

Both kinds of power consumptions are controlled using different techniques. Dynamic Volt-

age Scaling (DVS) is one of the most commonly applied technique to control the dynamic power

of the SoC. This technique involves reduction in supply voltage to reduce power consumption, at

the cost of system performance, whenever feasible [2]. Another technique called Adaptive Voltage

Scaling (AVS) uses on-chip temperature and process monitors to determine the required voltage for

operation [3]. To control the leakage power, Adaptive Body Biasing (ABB) technique is used, where

body terminal of transistors is biased to change the threshold voltage and reduce sub-threshold con-

duction [4]. However, to ensure efficient power conservation in the SoC, it is important to first bring

down power consumption of the building blocks of an SoC at circuit level.

1.1.2 Applications of voltage reference in an SoC

System-on-Chip (SoCs) designed for IoT contain a number of Analog/Mixed signal circuits, which

are used to design Analog Front-End (AFE) for sensors, Analog-to-Digital Converter (ADC) for

2


Figure 1.1: A basic block diagram of an SoC powered with harvested energy.

digital processing units, a Radio-Frequency (RF) transmission unit for wireless communication,

and an on-chip Power Management Unit (PMU). A precise reference voltage is a key requirement in

each of these analog and mixed signal blocks. A PMU may include Low dropout regulators (LDO)

or DC-DC converters to provide different levels of supply voltage for different blocks. A precise

reference voltage is required for both; to provide them ability to regulate the supply voltage and

provide high load and line regulation. A key building block for an AFE is an operational amplifier

which requires a common-mode feedback (CMFB) circuit. A constant reference voltage is needed

in a CMFB circuit to maintain stable a bias point to desirable level and achieve common-mode

rejection. An accurate reference voltage is also required for comparisons and conversion of analog

signal to digital bits in an Analog-to-Digital Converter (ADC), where accuracy of the reference

voltage directly affects the Effective Number of Bits (ENOB) of an ADC. Most of the energy in any

SoC is spent during wireless data exchange. The RF block is usually kept in off-state and turned

on only when in data is to be sent or received. A wake-up receiver is used in all RF transmission

units for this purpose which continuously monitors the channel for any incoming transmissions. A

stable reference voltage is needed in various wake-up radio architectures for incoming transmission

detection and powering up the trans-receiver blocks. Hence, a reference voltage circuit is vital

for generation of an on-chip, precise and constant reference voltage, which can be utilized as a

‘reference’ to measure, compare, regulate or detect various other voltages on the system.

3


1.2 Standard specifications for a reference voltage

Due to its widespread significant applications a voltage reference circuit is a critical block for an

SoC. Since the reference voltage Vref has direct impact on the functionality and performance of a

system, there are a few standardized specifications for a reference voltage circuit for determining its

performance.

1.2.1 Temperature Variation

The most standard parameter for any reference voltage circuit is the variation of its output Vref

across a range of temperature. Temperature variation, temperature stability, or temperature coeffi-

cient (TC) of Vref is measured in parts-per-million per degree Celsius (ppm/C). There are many

different methods which can be used to calculate the temperature stability, but most commonly used

is the box method. Across a given temperature range (Tmin and Tmax), it uses the maximum value

Vrefmax , minimum value Vrefmin, and the average value of the reference voltage Vrefavg in the given

temperature range to calculation the TC as

TC(ppm/C) =Vrefmax − Vrefmin

Vrefavg × (Tmax − Tmin)× 106 (1.3)

1.2.2 Power Supply Rejection

A Vref produced by a voltage reference circuit should be constant not only with temperature vari-

ations but also with changes in power supply voltages. Changes in DC level of power supply from

a non-ideal power source can be caused by many factors, including discharging of a power source

with time. Dependence of Vref on supply voltage level will contribute significantly towards the

total system error. Also, sometimes power lines can get coupled with an ac signal, hence producing

small ripples of various frequencies at the output of the supply voltage. A Vref has to be invariant

to all supply voltage variations at DC levels and to any noisy frequencies from a few Hz to a few

MHz according to the SoC requirements.

1.2.3 Variation across Process

Another important characteristic of a Vref is its reproducibility. Naturally occurring variation in

the fabrication process leads to slight differences in performance of every chip. An ideal reference

voltage should be unaffected by these process variations, as deviations in Vref may cause overall

4


system performance to fall below given specifications, reducing the overall yield of the production

of these expensive SoCs.

1.2.4 Output Noise

All circuits designed using silicon devices produce thermal noise. Noise generated by a reference

voltage circuit degrades the performance of an Analog-to-Digital converter (ADC) as it adds noise

to the output signal-to-noise ratio (SNR) of an ADC, thus reducing the total effective number of bits

(ENOB), reducing the performance of an ADC.

1.3 Principle of voltage reference circuit design

Figure 1.2: Operating principle of a bandgap voltage reference (a) two current biased diode-connected pnp transistors used to produce two CTAT voltages (VEB1 and VEB2) (b) the base-emittervoltages are used to generate a PTAT voltage ∆VEB and a bandgap reference VREF .

Until early 60s, Zener diodes and Avalanche diodes were commonly used for reference voltage

generation [5]. With suitable precautionary measures, it was possible to obtain stable reference

voltage over moderate ranges of temperature for a short period of time [6]. Efforts were made to

study the breakdown mechanism in silicon junction diodes [7] and to quantify the voltage behavior

with mathematical equations [8]. But because of high current consumption of these diodes, it was

difficult to achieve a time constant behavior for longer period of time. Also, they required tight

5


process control to maintain a given tolerance, and were implemented as an off-chip component,

which made them highly incompatible for Integrated Circuit (IC) applications.

This led to innovations in the design of the reference voltage source, where designers started

to explore and manipulate the temperature dependent voltages by canceling their temperature de-

pendencies. Widlar came up with the first known circuit implementation of a voltage reference [9].

The approach involved generation of a CTAT (Complementary to Absolute Temperature) voltage,

obtained from a forward biased Bipolar Junction Transistor (BJT) diode. As shown in Figure 1.2,

the negative coefficient of the emitter-base voltage VEB obtained was canceled using the positive

temperature coefficient of a PTAT (Proportional to Absolute Temperature) emitter-base voltage dif-

ferential ∆VEB of two transistors operating at different current densities, which produced a zero

temperature co-efficient (ZTC) reference. Since, the obtained reference voltage was equal to the

bandgap voltage of Silicon at absolute zero (0K), it became known as Bandgap voltage reference.

The temperature stability of this generated voltage was much better than Zener diodes, however

the major advantage of this circuit was that emitter-base voltage of BJT transistors was the most

studied and well understood parameter in an IC. Hence, it was easier to control the tolerance of the

generated reference voltage. Also, unlike Zener diode, which consumed hundreds of mA of current,

the circuit consumed lower power and hence, could provide time-constant voltage.

1.4 Motivation

With the advent of IoT, designing of voltage reference circuits has become critical because its per-

formance requirements have become more stringent. Apart from the typical requirements of low

process, supply voltage, and temperature (PVT) variations, additional requirements also needed to

be met for voltage reference circuits designed for self powered SoCs [10]. Since these SoCs needs

to have ability to run from harvested energy, one of the evident features of the reference voltage

generation circuit will have to be that it should have ultra low power consumption in the nW range.

This is necessary because voltage reference circuit is one of the blocks which is always on, even in

an idle-state where most of the power consuming blocks are shut down. Hence, power consumption

of the reference voltage will directly affect the battery life and ability of an SoC to run from har-

vested energy. Another important feature will have to be that the reference voltage circuit should

become operational at lower voltage, i.e. should have low supply operation. This is very critical

for ULP SoCs because the voltage at which reference voltage becomes operational is typically the

system start-up voltage. Since, the start-up voltage determines the voltage at which all the power

6


supplies are active, lower the startup voltage, lower is the power consumption, and easier it is to

operate using harvested energy. Also, the silicon area consumption of the voltage reference circuit

will have to be small. Moreover, to have control on the overall power consumption of SoC, it is also

necessary for the voltage reference to have ability to scale, so that various system level techniques

(like DVS and AVS) can be implemented.

Over a period of years, development in reference voltage circuit design techniques have

produced a number of different architectures to generate a reference voltage, however the concept

behind all have remained the same. Manipulating CTAT and PTAT voltages from diode connected

BJTs as proposed by [9] has always been the most popular technique to generate reference voltage

close to 1.2V. Typically in a CMOS process, parasitic P-N-P BJT are used in diode configuration

to generate these CTAT and PTAT voltages. Alternatively, PTAT and CTAT voltages have also

been generated by obtaining gate-to-source voltage Vgs of enhancement and depletion mode MOS

transistors [11]. Other approaches involve generation and addition of CTAT and PTAT currents [12]

instead of voltages. Reference voltages have also been generated by exploiting the CTAT nature of

threshold voltage VTH [13].

All the above works have achieved highly precise, low noise and stable reference voltages,

but still fall short in some critical parameters, so as to be usable in SoCs specifically designed for

IoT. A major drawback of all the above works is that they generate a reference voltage of 1.2V.

This means their startup voltage or minimum operational supply can not be less than 1.2V, which

is too high for any SoC to operate from harvested energy [14, 15]. There is a separate category of

reference voltage circuits called Sub-Bandgap voltage reference circuits, which provide reference

voltage less than the bandgap voltage of silicon. Hence, they are operational at supply voltages less

than the bandgap voltage i.e. 1.2V. Additionally, above works achieved low power operation in µW

range, but even lower power consumption is needed for ULP applications. Some recent publications

[16, 17, 18] have achieved operation in ultra low power, but have found very limited use as they are

not able to fulfill all the discussed performance requirements for a voltage reference circuit which

could be used for IoT compatible SoCs. In this thesis, an ultra low power low voltage reference using

a charge-pump circuit and switched capacitor network has been presented. The presented voltage

reference circuit, is designed to have ULP power consumption, while satisfying the requirements

of low area consumption and low start-up voltage, so that it can be used as building block for ULP

SoC for IoT devices. The thesis also presents a switch-capacitor based voltage scaling technique for

the voltage reference which consumes 10nW.

7


1.5 Organization of the Thesis

The thesis has been organized as follows.

• Chapter 2 presents the prior state-of-the-art bandgap reference architectures including few

recent architectures, and discusses their limitations particularly in respect to the performance

requirements of a voltage reference circuit for an ULP system.

• Chapter 3 presents the concept of the previously published voltage reference based on charge-

pump and switched capacitor network. It also presents the improvements made to this already

proposed architecture so as to achieve higher Power Supply Rejection (PSR) and better tem-

perature stability. Towards the end, it briefly discusses about reference voltage scaling, its

need and implementation, and presents a ultra low power consuming switched capacitor based

technique to scale the reference voltage.

• Chapter 4 focuses on the implementation details of the design. It discusses about the design

choices made for designing sub-circuits, and presents simulation results.

• Chapter 5 presents the conclusions and recommendations for future work.

8

Chapter 2

Review of the Literature

2.1 Introduction

Due to evolving CMOS process and changing performance requirements, voltage reference circuit

design has been under constant development since the first circuit proposed by Wildar in 1971 [9].

A voltage reference then was required to produce a reference voltage which was stable against tem-

perature and time, and could replace relatively noisier Zener diode. Within an year, a different

variation for the Widlar’s circuit were proposed by Kuijk [19] and later by Brokaw [20]. Tempera-

ture variation was first addressed by Meijer in 1982 who came up with first second order curvature

corrected BGR [21]. Gradually, with increasing demands of low power consumption for battery

operated portable devices, a first sub-bandgap reference was proposed by [22] which operated at

supply voltage of less than 1V. Since then, numerous architectures have been proposed by designers

targeting different performance metrics of the voltage reference, but mostly focusing on power con-

sumption, low supply operation and high temperature stability for good temperature ranges. Since

last decade, the focus has shifted on need for an ultra low power consumption and low voltage

operation in voltage references.

In vast pool of literature containing thousands of architectures of different Bandgap and

Sub-bandgap voltage references, we will very briefly look into only a few of them in this Chapter.

The first section will cover the state-of-the-art architectures of Bandgap and sub-bandgap voltage

references. Since the focus of the thesis is on Ultra low power sub-bandgap voltage references, in

second section, we directly go on to discuss some recently presented architectures which have been

proposed to be used for ULP applications.

9

CHAPTER 2. REVIEW OF THE LITERATURE

2.2 State-of-the-art voltage references

2.2.1 Conventional bandgap voltage reference

Nearly every device characteristic used in an Integrated circuit (IC) is temperature dependent, and

is either CTAT or PTAT. However, most commonly used CTAT voltage is the voltage across a

forward biased diode, mainly because of its good linearity against temperature and high value of

slope (∼ −2mV/K). Commonly, these diodes are implemented as diode connected BJTs, which

are readily available in any CMOS process.

Figure 2.1: A conventional BGR.

A conventional BGR circuit looks like Figure 2.1. When the BJT Q1 is biased with a current

Ibias(T ), which is a function of temperature, we obtain a CTAT voltage VEB1 at node X. To under-

stand the CTAT behavior of VEB1 , we first need to look into the expression for collector current of

a BJT with unit area, as given in Equation 2.1.

IC(T ) = IS(T )exp

(q(VEB(T )

kT

)(2.1)

Here, Vg0 is the extrapolated bandgap voltage at 0K, and IS is the saturation current, which as a

function of temperature can be written as [23],

IS(T ) = CT ηexp

(−qVg0kT

)(2.2)

10


where C is a constant which includes the size of BJT and η is model parameter whose theoretical

value cant be greater than 4. Substituting this expression in 2.1, we obtain,

IC(T ) = CT ηexp

(q(VEB(T ) − Vg0

kT

)(2.3)

Writing this equation again for a specified temperature value T = Tr, dividing it with 2.3, and

rearranging the terms, we can obtain an expression for VEB as [23],

VEB(T ) = Vg0

(1 − T

Tr

)+T

TrVEB(Tr) − η

kT

qlnT

Tr+kT

qlnIC(T )

IC(Tr)(2.4)

Figure 2.2: Curvature in VEB shows up as curvature in Vref .

From this expression, we can conclude two things. First, when we extrapolate the equation

to T = 0K, the base-emitter voltage VEB is equal to bandgap voltage Vg0. And second, first two

terms in the equation show that with rising temperature, value of VEB will decrease linearly, while

the last two terms will add a curvature to that linear dependency. Hence, VEB1 exhibits a CTAT

nature.

Also if we write Equation 2.3 for the diode Q2 with area A times the area of Q1, we can

show that for a same bias current Ibias = IC1 = IC2 ,

∆VEB = VEB1 − VEB2 =kT

qlnA = VT lnA (2.5)

where VT is the thermal voltage, and A is the ratio of the area of transistors Q1 and Q2. From this

expression, we can realize that ∆VEB linearly increases with temperature, and is PTAT in nature.

11


In Figure 2.1, we have both CTAT and PTAT voltages present in the circuit. At node X,

voltage is VEB1 and amplifier maintains equal voltage at node X and Y. Hence, current I flowing in

R2 is ∆VEB/R2. Thus, Vref can be expressed as,

Vref = VEB2 +∆VEBR2

(R1 +R2) = VEB2 + VT lnA

(1 +

R1

R2

)(2.6)

The above equation shows that Vref is a summation of CTAT and PTAT voltages, and with careful

selection of A,R1 andR2, slope of PTAT voltage (2nd term in the equation) can be scaled to be equal

to slope of CTAT voltage(1st term in the equation) to achieve a constant temperature independent

voltage. Ignoring the logarithmic terms in Equation 2.4 for simplicity, we can say that for,

lnA

(1 +

R1

R2

)=Vg0 − VEB2(Tr)

kTrq

(2.7)

Vout will be completely independent of temperature and will be equal to Vg0, the bandgap voltage

of silicon.

Although, Vout is not exactly temperature independent, but has a parabolic shaped curvature

shaped like “inverted U” as shown in Figure 2.2. This is because of the logarithmic terms in Equa-

tion 2.4, which we ignored in above calculations. Hence, we use Temperature Coefficient (TC) to

measure the variation or curvature in ppm/K or ppm/C.

The bandgap reference circuit shown uses resistors and Op-amp to provide an almost ideal

on-chip voltage reference circuit which performs very well with the variation of voltage, tempera-

ture, and and process. However, the circuit possesses serious limitations when it is to be used in

ULP space. Firstly, the nominal current consumption of this topology is in µA range. Secondly, the

reference voltage produced is close to 1.2V , which means that it can not operate at a supply of less

that 1.4-1.5V .

2.2.2 Sub-bandgap voltage reference

Apart from high power consumption, conventional bandgap reference suffered from another key

drawback that it’s output reference voltage was 1.2V, which is higher than modern-day supply

voltages used for circuits in ULP regime. This also limits the minimum supply voltage of this

architecture as supply voltage can not be less than the output voltage. Hence, for low power-low

voltage applications, it was necessary to have a ‘Sub-Bandgap’ voltage reference, which not only

gives output reference voltage less than the bandgap voltage, but is also operational at lower supply

voltages.

12


Figure 2.3: A scaled down version of CTAT voltage K × VEB is added to a scaled PTAT voltage∆VEB to generate a reference voltage K × Vg0 .

The basic principle behind generating a sub-bandgap reference voltage lies in scaling down

CTAT voltage. As it can be seen from Equation 2.4, value of VEB at 0K is equal to Vg0 , which is

1.2V. If a PTAT voltage is scaled up to cancel the slope of that VEB , it will result in a reference

voltage which will be equal to Vg0 . The same was also suggested by Equation 2.6. As shown in

Figure 2.3, scaling down CTAT voltage or VEB , can bring down reference voltage. An architecture

proposed by [22], generated PTAT and CTAT currents, and to generate scaled down CTAT voltage

and obtained a sub-bandgap reference.

The architecture proposed by Banba has become a state-of-the-art sub-1V BGR [22]. It was

first voltage reference circuit which could operate at less than 1V supply and generate a sub-bandgap

reference. Figure 2.4 shows the architecture proposed in [22]. The dimensions of PMOS transistors

M1, M2 and M3 are same. Hence currents I1, I2 and I3 are also same. Since, Op-amp keeps the

nodes Va = Vb = VEB1 , currents I2a and I2b can be expressed as,

I2a =∆VEBR2

(2.8)

I2b =VEB2

R1(2.9)

It is clear that I2a is a PTAT current and I2b is a CTAT current. I2 is the sum of both currents, and

13


Figure 2.4: Architecture of the Sub-1V voltage reference in [22].

hence Vref can be expressed as,

Vref = I3R3 = I2R3 =

(∆VEBR2

+VEB1

R1

)R3 (2.10)

With proper selection of resistor values, the reference voltage can be scaled down below

bandgap voltage. Reference voltage achieved using this technique was 515 ± 3mV from 27C to

125C [22]. Figure 2.4 shows that the minimum operational supply for the architecture can be

written as VEB + VDS . The reported minimum supply was 840mV, which could be brought down

further to 750mV with current technologies. However, even lower voltage operation is needed for

circuits to be employed for the ULP applications. Moreover, the presence of an Op-Amp kept the

operational current high. Also, large values of resistances increased the overall area of the voltage

reference, which makes it unsuitable for ULP applications.

2.3 Low power bandgap voltage references

2.3.1 MOSFET based sub-bandgap voltage references

A standard MOSFET operating in sub-threshold region also exhibits exponential voltage to current

behavior very similar to BJT. Since, the threshold voltage of MOSFET generally lies in 400mV-

14


500mV range, MOSFETS in subthreshold region also have been used to generate sub-bandgap

voltage reference which consume low power.

Figure 2.5: Sub-1V BGR based on MOSFETs biased in weak inversion proposed in [24].

Figure 2.5 shows architecture proposed in [24]. Transistors M1−4 are used to generate a

CTAT current in resistor R1. The feedback around M1 forces the current to be,

IR1 =VGS1

R1(2.11)

This current is mirrored in transistors in M5 and M6. Inspection of the circuit shows that the output

voltage Vref can be written as,

Vref = R4I4 + VR3 (2.12)

where VR3 and IR4 can be written as,

IR4 =VR3

R3− IR1

S6

S4(2.13)

VR3 =S6

S4

R2

R1VGS1 + VT ln

S8

S7

S5

S6(2.14)

Hence, equation for Vref can be re-written as,

Vref = αVGS1 + βVT (2.15)

15


where VGS is the CTAT voltage, VT or thermal voltage is the PTAT voltage, andα =(R4R5

+ 1)R2R1

S5S4−

R4R1

and β =(R4R5

+ 1)

ln S8S7

S5S6

. In these definitions, S refers to the aspect ratio of transistors. With

proper selection of transistor sizes, the slope of CTAT voltage ( VGS1) and PTAT voltage (VT ) can

be canceled out. The reported output voltage using this approach was 295.3mV ± 10.8mV. The

current consumption of this architecture was 3.6µA, with minimum operating supply voltage of 1.2

volts.

Figure 2.6: Simplified circuit for bandgap proposed in [25].

2.3.1.1 MOSFET based ULP voltage reference architectures

MOSFET based voltage reference proposed in [24] was low power, but not low enough to belong to

circuits of ULP classification. Ultra low power MOSFET based architectures have been proposed

by [25] and [17], which have achieved much improved results when compared to [24].

Figure 2.6 shows the architecture proposed by [25]. Equation for current in MOSFET oper-

ation in weak inversion and strong inversion ignoring channel-length modulation can written as,

IDSI=

1

2µnCox

W

L(Vgs − Vth)2 (2.16)

IDWI= 2µnCox

W

LV 2T exp

(Vgs − VthmVT

)(2.17)

16


where where µn is the mobility, Cox is gate oxide capacitance, W and L are the channel width

and length, VT is the thermal voltage, Vth is the threshold voltage and m is the subthreshold swing

parameter. Assuming that transistor M0 is operating in strong inversion, the expression for output

reference voltage from Equation 2.16 would be given by,

Vref = Vth1 +

√I0

µnCoxW0L0

(2.18)

where I0 is the bias current of M1 and Vth1 is the threshold voltage which is CTAT in nature.

It can be inferred that a PTAT2 bias current having quadratic temperature dependency is required

to cancel the negative coefficient of Vth1 to generate a ZTC reference voltage. PTAT2 current is

generated using transistors M1−8.

M1 and M3 are high Vth devices, while M2 and M4 are normal MOSFTES. Therefore it is

be safe to assume thatM1 andM3 can operate in weak inversion andM2 andM4 can can operate in

strong inversion for same bias conditions. Since gate-source voltages of M1 and M2 are identical,

and M3 and M4 are also identical, using Equations 2.16 and 2.17, we can write,

Vth1 +mVT ln

(I1

2µnCoxW1L1

)= Vth2 +

√2I0

µnCoxW2L2

(2.19)

Vth3 +mVT ln

(I3

2µnCoxW3L3

)= Vth4 +

√2I0

µnCoxW4L4

(2.20)

For Vth1 = Vth2 , and Vth3 = Vth4 , solving for current I0 in Equations 2.19 and 2.20, we can

have the expression for I0 which will be a PTAT2 current,

I0 =µnCox

W4L4

2

(√W4L4

/W2L2

− 1

)2m2V 2

T ln2

(W3

L3

/W1

L1

)(2.21)

In [25], a reference voltage of 670mV was generated with a temperature variation of 10ppm/C,

operating at minimum supply voltage of 0.9V and consuming 36nW power. However, 0.9V is still

high for circuits to be used for low-voltage applications. The work in [17] was able to bring down

minimum operational supply to 0.6V.

In [17], an architecture using MOSFETs in subthreshold region was used, as shown in Figure

2.7. The architecture used different-threshold and same-threshold MOSFET pairs to generate the

CTAT and PTAT voltages. From Figure 2.7, we can see that voltage at node VN is a consist of CTAT

and PTAT voltages, which can be written as,

VN = VGS5 − VGS4 = Vth5 − Vth4 + ηVT lnS4

S5(2.22)

17


in which Vthi and Si represent the threshold voltage and aspect ratio of transistors Mi respectively.

Since, VN and VP are same, current I0 is mirrored in M3. Hence, generated Vref at drain of M7 can

be written as,

Vref = A

(∆Vth + ηVT ln

S4

S5

)+ ηVT ln

S6

S7(2.23)

where A is the ratio of resistance R1 and R2. Zero temperature sensitivity can be achieved by

adjusting the parameters S4S5

and S6S7

. The architecture proposed generated 218mV with 23ppm/and

consumed 30.5nW at 0.6V supply.

Figure 2.7: Sub-1V BGR proposed in [17] operational at 0.6V supply.

2.3.1.2 Limitations

MOSFET based voltage references seem to be a fairly attractive option for ULP sub-bandgap volt-

age reference, however, most of the above architectures suffered a common drawback, that their

performance as compared to BJTs based BGRs is poor. The reference voltage Vref generated in all

MOSFET based voltage references has some dependence on threshold voltage Vth of MOSFET. Vth

being the most process dependent quantity makes Vref more susceptible to process variations. Pro-

cess spread (3σµ %) for MOSFET based bandgap reference in in [24] is 3.6%, which is almost twice

of what is usually achieved from bandgap references based on BJTs (close to 1.5% after Op-amp

offset cancellation [26]). Similarly for sub-bandgap voltage references, simulated process spread of

14% and 21% was achieved for reference voltage in [17] and [27] respectively. Hence, most of the

18


voltage reference circuits designed in CMOS process prefer using parasitic lateral BJTs available in

the process, instead of MOSFETs.

2.3.2 BJT based sub-bandgap voltage references

In the past decade, few voltage reference architectures have been proposed which consume power

in nW range using BJTs. Different flavors of conventional sub-bandgap architecture proposed by

[22] have been used to generate sub-bandgap voltage reference in [28, 29], but do not have power

consumption in nW range. However, the architecture in [22] can be used at Ultra low power levels,

but is not, because of the resistors in the architectures. Since the value of resistors have a direct

control on the current consumption of the architecture, maintaining current levels in nA range will

cause very large value of resistances (in MΩs range), causing large layout areas.

2.3.2.1 BJT based ULP voltage reference architectures

Figure 2.8: Sub-1V BGR proposed in [30] using BJT a) A simple block diagram b) PTAT generatorcircuit using a differential pair.

To have lower area with lower power consumption, a resistor less architecture was proposed by

[30] which used single BJT for CTAT voltage generation and a MOSFET differential pair with

current mirror, as shown in Figure 2.8b) for PTAT voltage generation. When operated in sub-

threshold region, difference between output and input voltage of the differential pair can be written

as Equation 2.27, which is PTAT in nature.

∆VGG = Vin − V out = VGS1 − VGS2 = ηVT ln

(S1S2

S3S4

)(2.24)

19


Figure 2.8a) shows a simple block diagram of the architecture proposed. It uses a voltage

divider to scale down the VEB by a division ratio M, and then adds PTAT voltage to it by cascading

PTAT voltage generators. The expression for reference voltage can be easily written as,

Vref =VEBM

+N∑i=1

VGGi (2.25)

where N is the number of differential pairs. It achieved 52.5nW of power with low area

consumption, and minimum operational supply of 0.7V. However, choice of MOSFET for PTAT

voltage generation deteriorated the performance against process.

Figure 2.9: A PTAT cell used in [18].

Similar concept is used by [18] to design a resistor less sub-bandgap voltage reference which

consumed only 5nW of power. It uses a very popular self-cascode structure using MOSFET to

generate PTAT voltage as proposed by [31], shown in Figure 2.9. When both transistors M1 and

M2 are operated in weak inversion, using Equation 2.17, expression for VPTAT can be written as,

VPTATcell = VDS2 = VGS2 − VGS1 = VT ln

(S1

S2+ 1

)+ VOS (2.26)

where Si is the aspect ratio of transistor Mi, and VOS is the offset voltage generated due

to mismatch between the transistors M1 and M2. Scaling CTAT voltage produced by VEB , and

stacking PTAT cells over it as shown in Figure 2.10 , a reference voltage Vref was obtained which

can be expressed as,

Vref =VEBM

+

N∑i=1

VPTATcell(i) (2.27)

20


Figure 2.10: A block diagram for Sub-1V BGR proposed in [18] using BJT and PTAT cells.

where M is the scaling ratio, and N is the number of PTAT cells, which is 2 for the proposed

architecture. The circuit obtained a reference voltage of 479mV and provided ultra low power

consumption, high temperature stability, and minimum supply operation of 0.9V, but suffered high

process variations due to use of MOSFETs operating in sub-threshold regions.

2.3.2.2 Limitations

BJTs when compared to MOSFETs provide much linear and more process invariant temperature

dependence in their characteristics. Hence, use of BJTs has been preferable more than MOSFETs

for designing highly precise bandgap voltage references. However, most of the architectures for

ULP voltage references based on BJTs use MOSFETs to generate the PTAT voltage to limit the

total current consumption, but at a cost of high process variation. Another disadvantage of using

BJTs for ULP sub-bandgap references is high minimum supply voltage. BJT requires minimum of

700mV of voltage across its base-emmiter junction to operate in active region. Hence, it has been

challenging to bring down supply of a BJT based voltage reference below 700mV.

21

Chapter 3

An Ultra Low Power voltage reference

using Charge-pump

3.1 Overview

BJT based voltage references have shown to perform better when compared to MOSFET based

voltage references, but one important limitation seen in almost all of the BJT based designs is that

they can not operate below 700mV supply. BJTs, together with MOSFETs (for PTAT voltage gen-

eration) have been used to generate reference voltage operational at sub-1V power supply but is not

low enough. Moreover, the output reference voltage suffers from high process variation. A charge-

pump based voltage reference overcomes this limitation. Biasing BJT with charge-pump not only

allows low voltage operation but also provides low power consumption. Also, PTAT voltage gener-

ation is done by traditional ‘∆VEB’ method, hence generating reference voltage less vulnerable to

process variations. In coming sections, detailed operation of charge-pump based voltage reference

and it’s underlying theory is described, which is followed by the description of switched capacitor

network which provides low area solution for generation of PTAT (∆VEB) voltage. The next section

describes how the reference voltage is generated by scaling and adding PTAT and CTAT voltages

using switch-cap network and presents the results achieved by implementing the voltage reference

in [32]. The next section discusses the drawbacks of that implementation and presents an improved

version of the voltage reference based on similar architecture. The last section briefly discusses

about reference voltage scaling, its need, and presents a switched capacitor based reference voltage

scaling method which consumes ultra low power and has less area in respect to other methods.

22

CHAPTER 3. AN ULTRA LOW POWER VOLTAGE REFERENCE USING CHARGE-PUMP

3.2 Charge-pump based VEB generation

Figure 3.1: Charge-pump circuit for biasing BJT [32].

Figure 3.1 shows a voltage doubler charge pump circuit being used to bias a BJT. An important

advantage of this circuit is that minimum supply voltage can go below VEBmax . Since this is a

voltage doubler, the minimum operation supply VDDmin can be obtained by Equation 3.1. If we use

voltage tripler or higher order charge pump, even lower VDDmin can be achieved.

VDDmin >VEBmax

2(3.1)

As seen in the Figure 3.1, input of this voltage doubler circuit is connected to VDD while

output is connected to Transistor Q1. In absence of BJT, the output node would have gone to twice

of VDD, but BJT clamps the output voltage to VEB by sinking the additional current through itself.

The expression of the current flowing in the BJT can be obtained by looking at the charge transferred

in each switching cycle. The charge-pump uses two non overlapping phases of clock φ1 and φ2. In

phase φ1, charge across capacitor Cf can be expressed as,

Qφ1 = Cf1VDD (3.2)

However, in phase φ2, the voltage at the output gets clamped to VEB . Hence, charge across capacitor

in phase φ2 can be given by,

Qφ2 = Cf1(VEB − VDD) (3.3)

Hence, charge flowing in BJT each switching cycle is given as,

∆Q = Cf1(2VDD − VEB) (3.4)

23


And the, current flowing in BJT is given as,

I =∆Q

∆T= Cf1f(2VDD − VEB) (3.5)

where f(= 1

∆T

)is the clock frequency. We also know that current through transistor is given as,

I = IS expVEBVT (3.6)

where VT is thermal voltage and IS is the saturation current whose temperature dependency is given

as

IS = CTn exp−Vg0VT (3.7)

where C is a constant, n is the temperature dependency order and Vg0 is the semiconductor bandgap

voltage. Comparing Equations 3.5 and 3.6, we can obtain the expression for VEB just like we did

for Equation 2.4.

VEB(T ) = Vg0

(1 − T

Tr

)+T

TrVEB(Tr)−ηVT ln

T

Tr+VT ln

(2VDD − VEB(T )

2VDD − VEB(Tr)

f(T )

f(Tr)

)(3.8)

This equation is very similar to Equation 2.4, and hence, the VEB voltage (stored in the capacitor

CVEB) obtained using the charge-pump biasing of the BJT shows linear behavior against tempera-

ture.

3.3 Switched capacitor network for ∆VEB generation

PTAT voltage generation is done by taking difference of two VEB voltages. Two BJTs Q1 and

Q2 with different emitter areas, are biased using the charge-pump technique described above to

generate VEB1 and VEB2 voltages at the output capacitors of their respective charge-pumps. A

switched capacitor network is then used to generate ∆VEB voltage. A major advantage of using

such a combination of switches and capacitors are that the power consumption of this architecture is

negligible. Figure 3.2 shows operation of a simple switch-cap network that generates ∆VEB using

same non-overlapping clock phases φ1 and φ2.

The capacitor Cx is connected between voltages VEB1 and VEB2 in phase φ2, which stores

charge QCx = ∆VEB × Cx in capacitor in that phase. In the next phase φ1, for extraction of this

∆VEB , bottom plate of the capacitorCB is connected to ground. Since, the total chargeQCx in both

phases has to be conserved, the top plate holds ∆VEB voltage on it. The ∆VEB voltage generated

on the top plate of the capacitor Cx phase φ1 can be either used for summation with VEB voltage or

other ∆VEB voltages as shown in the next section.

24


Figure 3.2: ∆VEB generation circuit.

3.3.1 B ×∆VEB generation circuit

To generate a temperature independent reference voltage, it is necessary to have ability to scale

the PTAT voltage so that its positive temperature coefficient could completely nullify the negative

temperature coefficient of the CTAT voltage. Switched capacitor network technique, as described

previously, can be used to scale ∆VEB voltage. Figure 3.3 shows a switch-cap network circuit to

generate a 2 × ∆VEB on the top plate of capacitor Cx2 . Very similar to ∆VEB generation circuit,

in phase φ2, the top plates and bottom plates of capacitors Cx1 and Cx2 are connected to VEB1 and

VEB2 voltages respectively. Hence, the charges stores on Cx1 and Cx2 are QCx1= ∆VEB × Cx1

and QCx2= ∆VEB × Cx2 respectively.

In phase φ1, the connections of the capacitors are rearranged such a way that top plate of

Cx1 is connected to bottom plate of Cx2 , and the bottom plate of Cx1 is connected to ground. The

total charge on each capacitor is conserved because there is no path for charge to go out of the

capacitor. Hence, the difference between the voltages of top and bottom plates of both capacitors in

both phases will remain same. Therefore, the top plate of Cx1 will hold ∆VEB , while the top plate

Cx1 will hold 2 × ∆VEB . In a similar fashion, we can easily obtain even more multiples of ∆VEB

as shown in Figure 3.4, where the number of multiples are only limited by requirements related the

non ideal nature of the switch implementation, for example clock swing.

25


Figure 3.3: 2 × ∆VEB generation circuit.

Figure 3.4: B × ∆VEB generation circuit.

26


3.4 Reference voltage generation

Figure 3.5 shows the architecture of the charge-pump and switched capacitor network based sub-

bandgap voltage reference. The two CTAT voltages VEB1 and VEB2 , of different slopes are gen-

erated using the charge-pump technique described in Section 3.2, and the fed inside a switched

capacitor network. This switched capacitor network consists of blocks that generates scaling con-

stants K and B for VEB1 and ∆VEB respectively, and sums the scaled CTAT and PTAT voltages.

A version of B × ∆VEB generator circuit for B = 3 as described in previous sections, is used to

simultaneously generate B × ∆VEB voltage and add K × VEB1 to it, which gets stored in the out-

put capacitance Cref . The expression for the obtained sub-bandgap voltage reference can be simply

written as

VREF = (K × VEB) + (B × ∆VEB) (3.9)

Together, charge-pump technique for CTAT voltage generation and switched capacitor net-

work for generating PTAT voltage and performing summation operation, ensure low minimum sup-

ply voltage and ultra-low power consumption for the architecture. Switched capacitor schemes used

in the architecture are discussed as follows.

Figure 3.5: Architecture for reference voltage generation using charge-pump and switched capaci-tor network.

27


3.4.1 K × VEB generation circuit

As discussed in Section 2.2.2, VEB needs to be scaled down before adding to PTAT voltage to gen-

erate a sub-bandgap reference voltage. A scaled K ×VEB (where K < 1) voltage, can be generated

using switched capacitor network as shown in Figure 3.6. It also uses two non-overlapping clock

phases φ1 and φ2. In phase φ2, the top plate of C2 is connected to the output of the charge-pump

circuit which generates VEB , while plates of capacitor C1 is connected to the ground and kept dis-

charged. Hence, capacitor C2 holds charge QC2 = VEB × C2, while C2 holds no charge. In phase

φ1, the top plates of C1 and C2 are connected together and charge on C1 gets shared between both

capacitors. Since, total charge on all the capacitors remain the same after each cycle, it can be easily

shown that voltage Vx on top plate of CL is given by

Vx = K × VEB =C2

C1 + C2VEB (3.10)

By proper selection of C1 and C2, a constant scaled down VEB can be generated at the

output of capacitor CL. It can be noticed that the generated K × VEB voltage gets stored at output

capacitor CL in every phase φ1 and has no path to discharge. Hence it is available for next step of

operation in both phases φ1 and φ2.

Figure 3.6: K × VEB generator circuit.

28


3.4.2 Summing CTAT and PTAT voltages

Figure 3.7: 3 × VEB generation and summing circuit.

A scaled up PTAT voltage B × ∆VEB (B = 3) is generated and added to K × VEB in consecutive

phases of clocks by using the switched capacitor techniques previously discussed in Section 3.3

to generate a sub-bandgap reference voltage Vref . As shown in Figure 3.7, this circuit also uses

same non-overlapping clocks phases φ1 and φ2. The operation of 3×VEB generation and summing

circuit is discussed as follows.

In phase φ2, top plate of capacitors Cx1 , Cx2 and Cx3 is connected to VEB1 , while bottom

plate is connected to VEB2 . So the voltage across the plates of Cx1 , Cx2 and Cx3 is ∆VEB . In

phase φ1, to sum the voltages, top plate of CL is connected to the bottom plate of capacitor Cx1 ,

29


and connections to other plates of capacitors are rearranged just like B×∆VEB circuit as shown in

Figure 3.7. Since there is no path for the charge to flow, the charge on each capacitor Cx1 , Cx2 and

Cx3 is conserved in both phases. Hence, as explained previously in Section 3.3.1, voltage at the top

plate of the capacitor Cx3 , which is equal to Vref and can be simply expressed as

Vref = (K × VEB) + 3∆VEB =C2

C1 + C2VEB + 3∆VEB =

C2

C1 + C2VEB + 3

kT

qlnN (3.11)

where k is the Boltzmann constant, q is the value of charge of a single electron, and N is the ratio

of number of fingers between Q2 and Q1.

3.4.3 Top level implementation

Figure 3.8: Top level implementation of bandgap reference.

Figure 3.8 shows a top level implementation of the voltage reference circuit with other sub-

circuits. The voltage reference uses clocked switched capacitor network and a charge-pump circuit

which use two non-overlapping phases of clocks. External clock can be used for this purpose but

a low power current starved ring oscillator has been designed to eliminate the requirement of any

external circuitry. The ring oscillator is biased using a PTAT current source which provides current

in nA range to keep the current burnout low. Further, the switches used in charge-pump circuit need

to pass VEB voltage through them, which is a voltage higher than VDD. Therefore, the clock phases

φ1 and φ2 need to have a swing from 0 to 2 × VDD, for which a clock doubler circuit is used.

30


3.4.3.1 Current Starved Ring Oscillator

Figure 3.9: Current starved ring oscillator.

The voltage reference uses two non overlapping phases of a clock switching at very low frequency to

keep the overall power consumption low. To provide a controlled low frequency oscillating signal,

a 3 stage current starved ring oscillator as shown in Figure 3.9 is used which is uses current from a

(nA) PTAT current source, and hence consumes ultra low power in nW. The output frequency of the

clock source is given by

FreqCLK = 3 × I

CVDD(3.12)

We can see that the clock frequency is inversely proportional to supply voltage. Since, power

consumption of BGR increases with increasing supply voltage, decreasing frequency of clock with

increasing supply helps to regulate the overall power consumption of voltage reference circuit.

3.4.3.2 Clock doubler circuit

CLK from ring oscillator is fed in a latch to generate two non overlapping clock phases p1 and p2

which swing from 0 to VDD. A clock doubler circuit is used to double the swing of these clock

phases as shown in Figure 3.10. The phases p1 and p2 are fed into inverters (A,B) which drive

capacitors CV1 and CV2 respectively, whose top plate is connected to diode connected NMOS with

low threshold voltage. When output of inverter A is low, the top plate of capacitor CV1 is charged to

VDD from the leakage of diode. When output of inverter A goes high to VDD, the top plate of CV1goes to 2 × VDD. This way two another non overlapping clock phases X1 and X2 are generated,

which swing from VDD to 2 × VDD. In the next step, we use these signals p1, p2, X1 and X2 to

31


Figure 3.10: Clock doubler circuit.

generate φ1 and φ2 as shown in Figure 3.10. When p1 is high, φ2 is pulled down to ground. When

p1 is low, X2 is also low and X1 is high, hence φ2 is pulled up to 2 × VDD. In similar way, φ1 is

also generated which swings from 0 to 2 × VDD.

3.4.3.3 Results after implementation

The voltage reference circuit presented above was implemented in 130nm CMOS process in [32].

The circuit was verified for temperature range of 0C to 80C. The circuit was operational at sup-

ply voltage as low as 0.4V and consumed consumes 32nW power at 27C and 0.5V supply. The

voltage reference circuit achieved output reference voltage of 500mV, with temperature variation

of 75ppm/K. The circuit achieved a 3σ deviation of 2% across process and mismatch variations.

Also, the output reference was trimmable because of by trimming the capacitor C1 used in switched

capacitor circuits as shown in Figure 3.7.

Although, the circuit shows excellent performance in all specifications, the power supply

variation of the bandagap reference is quite high (about -40dB at DC). Using a cascode configuration

as in [32], the power supply variation was suppressed to -52dB, but it is still high when compared

to other works. Also, the temperature variation obtained when compared to other works is high.

Hence, in next section we present a next version of the design which overcomes the high power

supply variation and presents a method to reduce temperature variation against temperature.

32


3.5 Improved version of charge-pump based BGR

The charge-pump based voltage reference explained in above sections provides low power, and

lower area solution for a reference voltage circuit design. However, the circuit suffers from high

variation with power supply variation. The output of the bandgap reference varies by 5mV with a

variation 1V in power supply. The high variation of the bandgap reference circuit is because of the

large variation of the power supply causes a large variation in the bias current for BJT transistors

and hence the VEB voltage. Hence, a method utilizing power supply rejection (PSR) of current

mirror is proposed to reduce the supply variation in reference voltage. Also, due to comparatively

high variation across the temperature range, a temperature based trimming circuit is proposed to

reduce voltage variation across temperature.

3.5.1 Improving Power Supply variation

Figure 3.11: Top level implementation of improved sub-bandgap voltage reference.

Figure 3.11 presents a circuit that overcomes the power supply variation by utilizing a current source

based design. The circuit takes advantage of the high PSR of the current source. As the current

generated in current source is highly insensitive to supply variation, the current generated in the

current source is used to bias the core reference circuit. Current from the PTAT current source is

mirrored as IMirror in transistorMP . A part of that current IDiode is fed in a diode which clamps the

voltage, hence creating a virtual supply VDDvirtualfor the BGR. Since the mirrored current IMirror

33


doesn’t changes much with change in supply, the virtual supply remains constant, hence improving

the variation of reference voltage. Also, because of the switching circuits in the core BGR circuit, a

decoupling capacitor CV is put at the virtual supply node.

However, since the BGR is current biased, at some corners the diode starts to leak a lot of

current at high temperatures, which may pull down the virtual supply below the startup voltage.

Hence, a transistor Mleak operating in off-state is used so as to compensate for the leakage in the

diode. The effect of leakage compensation is discussed in the next chapter.

3.5.2 Improving temperature variation

The temperature variation in the reference voltage generated in presented architecture will be be-

cause of the logarithmic terms present in the Equation 3.9 whose terms are very similar to terms

in Equation 2.6. Hence, the curvature of reference voltage against temperature have a parabolic

shape, very similar to Figure 2.2. Hence, there is a need for temperature compensation to reduce the

2nd order temperature variation. A temperature based trimming scheme is proposed for improving

temperature stability of the reference voltage.

Figure 3.12: Temperature based trimming scheme.

The circuit uses digital bits to trim the capacitor C2 in theK×VEB generator circuit. Figure

3.12 shows the temperature variation of Vref curves with untrimmed capacitor C2 and capacitor C2

trimmed to slightly lower values. As the value of C2 is decreased a little, the CTAT term in Equation

3.11 is also reduced, and hence a the reference voltage also decreases. The temperature based

trimming circuit utilizes this behavior, and selects different reference voltage curves for different

temperature ranges as shown in Figure 3.12, bringing down the effective temperature variation.

34


But this also means that the the bit code driving the trimming circuit needs to change for different

temperature ranges. This can be achieved by generating trimming bits from a temperature sensor,

which is mostly available in many mixed signal blocks. It may be noted that the accuracy and

resolution requirements of the temperature sensor needed for this trimming circuit are not very

high, because the temperature ranges are large enough. An ultra low power temperature sensor

with accuracy of +1.5C/-1.7C has already been designed by [33] which consumes only 23nW of

power, and provides far more accuracy than required.

It is important to notice that unlike process and mismatch trimming circuit, the aim of this

circuit is to bring very small change in the reference voltage with each trimming bit. Assuming a

temperature deviation of 2.5mV for Curve 1, change in the reference voltage after each trimming

bit operation should be about 300µV only. Hence, the ∆C capacitors need to be few fFs only.

3.6 Reference Voltage scaling

3.6.1 Introduction

In order to improve energy efficiency, power supply voltage scaling methods are being implemented

aggressively, on essentially every SoC designed. Effective control on the power consumption of

SoC serves many purposes. Reduced power consumption means reduced heat dissipation, which

means reduced cost and weight of the system due to lesser bulky thermal management systems. For

SoCs running from harvested energy, it is important to optimize power consumption because even

smallest amount of energy can not be wasted.

Dynamic voltage scaling is an effective strategy to reduce power consumption where supply

voltage is scaled up (Over-volting) and down (Under-volting), such that the performance is reduced

just enough to finish a task within a given deadline. For example, when a sensor is not taking

any readings, supply voltage in the Analog Front-End for that sensor can be reduced so that the

power consumption in idle state is low. Supply voltage is also scaled up when there is requirement

of high performance, for e.g. data processing or radio communication. Dynamic voltage scaling

alone can give up to 20% of power savings and when used with other voltage scaling schemes like

Adaptive Body Biasing (ABB), it may save upto 40% of power [2]. To implement this technique,

it is important that communication is maintained between the Power Management Unit and other

blocks in the SoC which require DVS. Also, special supply regulation circuits are which are DVS-

capable, are required for implementation of this technique.

35


Various DC-DC converters which have ability of DVS have been designed in [34, 35]. A

common feature of all these DC-DC converters is that they either require multiple reference volt-

ages, or assume a presence of multilevel reference voltage, and use it to scale the output supply

voltage. Hence, it is necessary to have some kind of reference voltage scaling scheme to support

these DC-DC converters.

3.6.2 Techniques for reference voltage scaling

Figure 3.13: Resistive scaling of Voltage reference a) Off-chip implementation b) On-chipimplementation

The most common reference voltage scaling technique is to use resistive divider network. As shown

in Figure 3.13a), a buffer is used in front of a reference voltage and current is drawn into a series

of resistances. At the end of each resistor, we can get a scaled version of voltage reference which

is the given by the ratio of resistances to the total resistance at that point. This technique is suitable

for any off chip implementation.

For on-chip implementation of this circuit which is shown in Figure 3.13b), a resistor is

digitally trimmed using ADC to generate different reference voltages whenever required. However,

this is not suitable for ULP operations. A power consumption of nW in these circuits can only

be achieved using very high value of resistances, which will take up a lot of area. A 100MΩs of

resistance would be needed to implement such circuit for only 10nA of current consumption at

1V supply [36]. Hence, designers sometimes refrain from using these type of circuits, and rather

36


prefer having multiple reference voltages on chip which will consume lesser power and lesser area.

However, even this is not a suitable option for a SoC running from harvested energy, where each

nW of power is important.

3.6.3 Switched capacitor based reference voltage scaling

Figure 3.14: Reference voltage scaling using switch-cap network

Switched capacitor based reference voltage generation is a good alternative which can provide low

power and low area consumption. Figure 3.14 shows operation of a switched capacitance based

reference voltage scheme using a nW power Op-amp. It operates in three clock phases φ1, φ2 and

φ3, where φ1 and φ2 are non overlapping clock phases. In phase φ1, the switches are connected such

that the the Op-amp is in voltage follower configuration. Hence, the output voltage Vout is equal to

the reference voltage Vref . In phase φ2, the Op-amp is gets configured as a non-inverting amplifier

using the capacitors C1 and C2. It can be shown that output of the Op-amp in this configuration is

given by following expression.

Vout = Vref ×(

1 +C1

C2

)(3.13)

However, the output of Op-amp will slowly rise up to this value because of capacitive con-

figuration. To speed-up the process, another Op-amp with voltage follower configuration is used.

This way, at the very start of phase φ2, inverting and non-inverting ends of Op-amp are at at Vref .

Also, a phase φ3 is used, just before the start of phase φ1, to ensure that Vout is settled, and then

sampled and stored at the output capacitance Cout. Hence, after few cycles of sampling, the voltage

37


VREFDV Swill be equal to Vref ×

(1 + C1

C2

). The value of VREFDV S

can be changed by trimming

the value of capacitor C2.

0

0.2

0.4

0.6

0.8

1

Vo

lta

ge

(V)

b0

0.55

0.6

0.65

Vo

lta

ge

(V

)

VREF

DVS

Figure 3.15: Simulation result for the reference voltage scaling using switch-cap network

Figure 3.15 shows the simulation results of the presented reference voltage scaling circuit.

Here, bit b0 is used for trimming of capacitor C2. When b0 is set high, the reference voltage is set to

0.6V, when b0 is set low, the reference voltage is set to 0.55V. Each Op-Amp used consumes only

5nA of current, making the total current consumption 10nA for this scheme. Since, small value of

capacitors are used, it consumes much lower area than a resistive network.

38

Chapter 4

Implementation and Results

4.1 Overview

This chapter discusses important details about the design process and device choices made for vari-

ous sub-circuits described in the previous chapter. It also presents simulation results obtained from

each sub-circuit. Later, it presents the simulation results of the sub-bandgap voltage reference im-

plemented in 130nm BiCMOS process. Post-layout simulations are also presented to verify the

results achieved.

4.2 Design of current source

A PTAT current source as shown in Figure 4.1 is designed where transistors operate in sub-threshold

region. This current source is designed to consume current in nA range so as to keep overall power

consumption of circuit to a few nW. A cascode structure was chosen so as to have low supply varia-

tion in the output current, because the same current has to be used to bias the core voltage reference

circuit. However, both NMOS and PMOS cannot be cascoded because of the low minimum sup-

ply voltage requirements. Hence, NMOS of longer lengths are used to control the channel length

modulation in the circuit. A high density poly resistor is used to implement resistor R which lies

in MΩs range. It provides ±15% variation, but consumes low area. This choice was made because

the variation in PTAT current source has low impact on the reference voltage. Simulation results of

the PTAT current source are shown in Figure 4.2. The current source generates 5nA of current at

room temperature at 0.6V supply. A 3σ variation of 2nA was achieved for 500 point Monte-Carlo

simulation.

39

CHAPTER 4. IMPLEMENTATION AND RESULTS

Figure 4.1: Circuit for PTAT current source.

-20 0 20 40 60 80 100

Temperature (0C)

2

3

4

5

6

7

8

9

I PT

AT (

A)

10-9

+3

-3

Figure 4.2: Simulated PTAT current at 600mV with 3σ variation

40


4.3 Ring Oscillator and Clock doubler

The key features of the ring oscillator are that it needs to have low power consumption and low fre-

quency output. To control the power consumption of the ring oscillator, it is biased from nA PTAT

current source, producing PTAT frequency as shown in Figure 4.3. PTAT frequency is beneficial

for the curvature of the reference voltage as it helps to reduce the co-efficients of curvature causing

logarithmic terms in Equation 3.8 [23]. With PTAT frequency, coefficient for the term VT ln TTr

is

reduced to −η + 1. The output frequency of the ring oscillator at 27C is 12KHz. The frequency

-20 0 20 40 60 80 100

Temperature (0C)

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

2.2

Fre

qu

en

cy (

Hz)

104

+3

-3

Figure 4.3: Simulated frequency from the ring oscillator at 600mV supply with 3σ variation.

of the ring oscillator is kept low so that the digital gates used in the clock doubler circuit consume

low power. Since, dynamic power consumption of the gates is proportional to frequency as shown

in Equation 1.2, reducing the operational frequency helps controlling the power consumption of

digital circuits. At 27C, the ring oscillator together with clock doubler circuit consumes 3.68nW

at 600mV supply. A 3σ variation of 0.43kHz in frequency was achieved for 500 point Monte-Carlo

simulation.

41


4.4 Charge-pump and switched capacitor network

All capacitors used in charge-pump circuit and switched capacitor network are implemented using

MIM caps, for different reasons. In charge-pump circuit as shown in Figure 3.1, the flying cap

Cf has different potential both switching cycles.Similarly, the capacitors Cb in ∆VEB generation

circuit in Figure 3.2 were also implemented using MIM caps.

For the load capacitances CL, in charge-pump and capacitors Cref in ∆VEB generation

circuit, MOS-capacitors could have been used, but using MIM cap allows it to float in high metal

layers, saving the substrate space for other circuits, thus reducing area.

Capacitors inK×VEB generator circuit as shown in Figure 3.6 requires precise capacitance

values. Therefore MIM cap, being the closest to ideal and most precise capacitor, was used to

implement capacitors C1 and C2.

Figure 4.4: Use of Transmission gates to cancel charge injection.

Other important ingredient of both circuits is the switch. Switches were implemented as

transmission gates so as to cancel out charge injection at the nodes of switch cap network. The

switches had to be designed using thick oxide transistors, so as to control leakage. But thick oxide

MOSFETs have high gate-to-drain capacitance, causing clock feed-through. Thus, there is an un-

avoidable trade-off between leakage control and clock feed-through in the reference voltage in the

current technology.

42


Figure 4.5: Trimming of Q2 transistor for process variations.

4.4.1 Trimming circuits

4.4.1.1 Process and Mismatch trimming

Even after careful leakage compensation, due to mismatch in Vth and mismatch in current mirrors,

the reference voltage might deviate from its nominal value. Hence, to compensate for these changes,

a digital trimming circuit is used which changes the number of fingers in Q2. The trimming circuit

uses 5 bit scheme b0−4 as shown in Figure 4.5. This allows the number of fingers in Q2 change in

binary multiples and bring Vref back to its nominal value at different process corners.

4.4.2 Temperature based trimming

Temperature based trimming scheme to improve temperature variation of the reference voltage in-

volves trimming of capacitor C2 in K × VEB generation circuit. Figure 4.6 shows the circuit used

for digital trimming which uses 3 bits b0−2 to add or remove binary multiples of ∆C capacitance.

Since the value of ∆C lies in few fFs range, it is implemented as NMOS capacitor operating in

accumulation region, because such small value of capacitances can only be realized using MOS

capacitors. However, MIM caps would have been the best choice but the minimum value obtainable

from the current process used is much higher than the required value.

43


Figure 4.6: Temperature based trimming circuit.

4.5 Biasing circuit and Leakage compensation

The voltage reference is biased by a virtual supply VDDvirtual, generated by passing current on a

diode implemented at MOS diode as shown in Figure 3.11. It needs to be ensured that diode doesn’t

leaks a lot of current so much current that it becomes the leading current drawing part in the circuit.

Hence, a thick oxide MOS is used to implement the diode. However, there is a trade-off in using

the thick oxide. Since the Vth of thick oxide at room temperature lies in 400mV-450mV range, it

gets regulated at voltage supplies higher than ∼ VthMD+ VDSMP

. Hence, there has to be a careful

selection for the sizing of the MD transistor.

Despite careful section of MD transistor, there will be corners in which the diode will have

a low threshold voltage and leak current at high temperature. Since, MD is implemented as PMOS,

a PMOS transistor in off-state is used to compensate for the leakage. The transistor Mleak is com-

pletely off and conducts no current at normal temperatures at a typical corner. It leaks slightly

at higher temperatures which helps compensating for leakage in the digital circuitry. However, the

transistorMleak will also leak at the corners whereMD will leak, thus compensating for the leakage

in diode.

A large capacitor is also needed to suppress the effect of switching circuits on the bias

current and virtual supply. Hence, a large decoupling capacitor CV is required at the virtual supply

generation node, which is implemented using MOS-capacitor as its capacitive density is the highest.

44


4.6 Simulation Results

4.6.1 Temperature and Supply Variation

After the sub-circuits are designed, they are assembled together to design the voltage reference

circuit as shown in Figure 3.11. The designed voltage reference circuit was simulated over a tem-

perature range from -20C to 100C using power supply varying from 600mV-1.5V. Figure 4.7

shows the simulation results for the Vref across the temperature range. It shows that temperature

variation of 29ppm/0C was obtained at 600mV, which seems to get better at higher supply voltages.

-20 0 20 40 60 80 100

Temperature (0C)

0.5

0.5005

0.501

0.5015

0.502

0.5025

0.503

0.5035

VR

EF (

V)

600m

625m

675m

700m

800m

1

1.2

1.5

1.7mV

Figure 4.7: Variation of reference voltage Vref across temperature for different power supplies.

Figure 4.8 shows supply variation of Vref against supply voltage at 40C. Variation in Vref

is only 1mV from 600mV to 1.5V, and just 0.01mV variation from 0.7 to 1.5V variation. The output

voltage changes differently with supply variation for different temperatures as shown in Figure 4.9.

The best supply variation was seen between temperature range 30C-60C. However, the worst case

variation with supply takes place at 0C. Vref varies 2mV from 600mV to 700mV, and 0.8mV from

700mV to 1.5V. This happens because the virtual supply gets regulated at supply voltages higher

than ∼ VthMD+ VDSMP

. Since VthMDhas a CTAT behavior, at low temperatures slightly higher

supply is needed for regulated Vref .

45


0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5V

DD (V)

0.5018

0.502

0.5022

0.5024

0.5026

0.5028

0.503

0.5032V

RE

F (

V)

0.5mV

0.01mV

0.6mV

Figure 4.8: Variation of reference voltage Vref across different power supplies at 40C.

0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5

VDD

(V)

0.5

0.5005

0.501

0.5015

0.502

0.5025

0.503

0.5035

VR

EF (

V)

-200C

-100C

00C

100C

200C

300C

400C

500C

600C

700C

800C

900C

1000C

1.5mV

0.9mV

1.6mV

1.1mV

Figure 4.9: Variation of reference voltage Vref across different power supplies for different tem-perature .

46


-20 0 20 40 60 80 100

Temperature (0C)

0.485

0.4875

0.49

0.4925

0.495

0.4975

0.500

0.5025

0.505

0.5075

0.510

VR

EF (

mV

)

-3

+3

Figure 4.10: Monte-Carlo simulation of Vref for 500 points across temperature.

4.6.2 Monte-Carlo Simulations

Figure 4.10 shows a 500 point Monte-Carlo run for process and mismatch variation of untrimmed

voltage reference circuit at over a temperature range from -20C to 100C. It can be comprehended

that process and mismatch variation affects the reference voltage most at 100C with a 3σ variation

of 10.5mV. Without the leakage compensation, this was 20mV, because at some fast corners the

Virtual supply may go below to 300mV due to leakage in the diode and the digital gates at higher

temperatures, thus, making it difficult for the charge-pump circuit to bias the BJTs properly. Hence,

a leakage transistor Mleak was used. However, due to threshold voltage mismatch, the leakage

transistor Mleak might not be able to fully compensate for the diode leakage and leakage in digital

circuits at some corners, or may over-compensate at some corners. Additionally, there is leakage in

transmission gates at fast corners as well. Together, they slightly increase the standard deviation of

Vref at 100C.

Figure 4.12 shows the distribution of Vref across process and mismatch at 40C. The simu-

lation shows an untrimmed accuracy (3σ) of 1.5%. Figure 4.11 shows the variation in temperature

variation across process and mismatch. The design achieves a mean variation of 40ppm/0C with

standard deviation of 23ppm/0C.

47


Figure 4.11: Variation in ppm/C across 500 Monte-Carlo Simulation points.

490 492 494 496 498 500 502 504 506 508 510

Vref

(mV)

0

20

40

60

80

100

120

Fre

qu

en

cy

= 501.3mV

= 2.5mV

Figure 4.12: Variation in Vref across 500 Monte-Carlo Simulation points at 40C and 600mVsupply.

48


4.6.3 Power Consumption

-20 0 20 40 60 80 100

Temperature (0C)

30

40

50

60

70

80

90

100

110

120

130

To

tal cu

rre

nt

co

nsu

mp

tio

n (

nA

)

1.5V

1.2V

800mV

700mV

675mV

625mV

600mV

Figure 4.13: Total current consumption across temperature for different supply voltages.

Figure 4.14: Distribution of current consumption at 600mV at 270C (Total = 54.53nA).

Figure 4.13 shows the total current consumption of the voltage reference circuit over a temperature

range from -20C to 100C. At 27C, the voltage reference circuit consumes 54.53nA at 600mV, i.e.

32.7nW. Figure 4.14 shows the current distribution of the circuit at 600mV at 27C for different sub-

circuits. The current source consumes 10.17nA, the charge pump and switch cap network consumes

33.2nA, the ring oscillator consumes 3.3nA and the clock doubler circuit consumes 2.7nA, while

the rest of current is consumed by the diode to maintain virtual supply.

49


4.6.4 PSRR

101

102

103

104

Frequency(Hz)

-76

-74

-72

-70

-68

-66

-64

-62

-60

-58

-56

PS

RR

(dB

)

Figure 4.15: PSRR of the voltage reference circuit.

The PSRR of the presented voltage reference circuit should show a low pass filter type response.

It can be verified by the simulation result as shown in Figure 4.15. This happens because of the

decoupling cap CV used at the virtual supply node. It acts as an ac-short for higher frequencies,

thus improving PSRR for higher frequencies. Hence, the worst case PSRR is observed at DC or

0Hz.

4.6.5 Temperature based trimming

Figure 4.16 shows the operation of temperature based trimming circuit on VREF obtained for

600mV supply at TT corner. Different reference voltage curves are obtained for different value

of capacitor C2, using the trimming bits b2−0 in the circuit shown in Figure 4.6. The temperature

variation before trimming is 29ppm/C. It can be observed than when different Vref curves are se-

lected for different temperature ranges (shown by the vertical lines) using a temperature dependent

trimming code, temperature variation in Vref reduces to 11.6ppm/C. It can also be noted that the

minimum resolution for a temperature sensor needed for trimming in this case was 5C.

50


-20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100

Temperature (OC)

0.4985

0.499

0.4995

0.5

0.5005

0.501

0.5015

0.502V

RE

F (

V)

VREF

(04)

VREF

(03)

VREF

(02)

VREF

(01)

VREF

selected1.7mV

0104 03 02 03 04

700 V

Trim bit code (Octal)

Figure 4.16: Operation of temperature based trimming circuit on VREF obtained for 600mV supplyat TT.

4.6.6 Post Layout Results

Figure 4.17 shows the screen-shot of the layout. The layout shows that the circuit has an area of

0.0436mm2. Figure 4.18 shows the reference voltage across temperature range (-20C to 100C)

after post layout simulations. A temperature variation of 46.7ppm/C is obtained at TT corner which

improves to 25ppm/C at SS corner. It can be noted that the circuit shows inferior performance at

the FF corner due to the leakage at high temperatures. The temperature variation at FF corner is

70ppm/C. However, this can be improved by trimming the reference voltage for process variation.

Figure 4.19 shows the curvatures of VREF for TT, SS and FF corners for temperature range -20C

to 100C after trimming. Trimming improves temperature variation at FF corner to 63.33ppm/C,

which can now be further improved using temperature based trimming scheme. The minimum and

maximum values obtained for VREF at 25C are 504.1mV and 498.6mV.

51


Figure 4.17: Layout of the voltage reference circuit.

52


-20 0 20 40 60 80 100

Temperature (0C)

0.497

0.4975

0.498

0.4985

0.499

0.4995

0.5

0.5005

0.501

0.5015

0.502

VR

EF (

mV

)

TT

FF

SS

1.5mV

2.8mV

4.1mV

Figure 4.18: Variation of VREF across temperature after post-layout simulations.

-20 0 20 40 60 80 100

Temperature (0C)

0.498

0.499

0.5

0.501

0.502

0.503

0.504

0.505

VR

EF (

V)

TT(0b10000)

FF(0b10101)

SS(0b01110)

1.4mV

2.8mV

3.8mV

Figure 4.19: Variation of VREF across temperature after after trimming (post-layout).

53


Para

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Type

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54

Chapter 5

Conclusion and Future Work

5.1 Conclusion

The presented bandgap voltage reference achieves Ultra low power operation of 32.8nW. It provides

a reference voltage of 500mV, with an untrimmed accuracy of 1.5% at 400C. With a minimum op-

erating supply of 600mV, its uses current source structure to provide a PSRR of -58.58dB at DC for

supply voltage range 675mV-1.5V. Against higher frequency, PSRR improves even more because of

the low pass filter type response provided by the decoupling capacitance. The voltage reference cir-

cuit shows a temperature stability of 46.7ppm/0C (post-layout) at 600mV which improves at higher

supply voltages. A new temperature based trimming scheme is used and a reduction of 60% in the

temperature variation is obtained. The total area consumption of the circuit is 0.0436mm2.

[17] and [16] obtained comparable power consumption but have higher minimum supply voltage

and greater process variation due to MOSFET based reference voltage design. Other designs [37,

27] have achieved comparable or better untrimmed temperature stability, but consume 10 times

more power. The presented voltage reference provides low supply voltage operation, ultra low

power consumption, low variation across process and less area occupation, which satisfies all the

performance requirements for a voltage reference circuit suited for IoT devices.

A switch-capacitor based reference voltage scaling circuit is also presented which uses Op-amps.

It consumes a total of 10nA current and occupies less area than resistive divider based reference

scaling technique. Hence, this scheme is suitable for implementing reference voltage scaling for

DVS capabilities in an ULP SoC.

55

CHAPTER 5. CONCLUSION AND FUTURE WORK

5.2 Future Work

It will be interesting to look into following topics to study in a future reference

• The presented voltage reference uses current mirror to reduce the power supply variation, but

increases the minimum operational supply voltage from 0.4V to 0.6V. Hence, a new method

needs to be investigated to reduce the PSRR, while keeping the minimum operating supply

low.

• A method for second order temperature compensation in the reference voltage is needed to

reduce its temperature variation, without trimming.

• The process currently used for implementing has high Vth devices but have large minimum

gate area, which causes increased ripple at the output reference voltage. Hence, it will be

interesting to implement the circuit in a different process which is more suitable for low

power circuit designing with a mechanism to suppress the non ideal behavior of switches

used.

56

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[36] N. Shafiee, S. Tewari, B. Calhoun, and A. Shrivastava. Infrastructure circuits for lifetime

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61

Appendix A

List of Publications

[A1] Shikhar Tewari, Aatmesh Shrivastava, “Ultra-low power charge-pump based Bandgap Refer-

ences, 26th Workshop on Advances in Analog Circuit Design, Eindhoven, The Netherlands, March

28-29-30, 2017

[A2] Shikhar Tewari, Aatmesh Shrivastava (2018), “Ultra-low Power Charge-Pump-Based Bandgap

References”, in “Hybrid ADCs, Smart Sensors for the IoT, and Sub-1V & Advanced Node Analog

Circuit Design”, Springer International Publishing, Springer

[A3] N. Shafiee, S. Tewari, B. Calhoun, and A. Shrivastava, “Infrastructure circuits for lifetime im-

provement of ultra-low power IoT devices”, IEEE Transactions on Circuits and Systems I: Regular

Papers, 64(9):25982610, Sept 2017.

62

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