a new general topology for cascaded multilevel inverters

3932 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 8, AUGUST 2014

A New General Topology for Cascaded MultilevelInverters With Reduced Number of Components

Based on Developed H-BridgeEbrahim Babaei, Member, IEEE, Somayeh Alilu, and Sara Laali, Student Member, IEEE

Abstract—In this paper, a new general cascaded multilevelinverter using developed H-bridges is proposed. The proposedtopology requires a lesser number of dc voltage sources and powerswitches and consists of lower blocking voltage on switches, whichresults in decreased complexity and total cost of the inverter.These abilities obtained within comparing the proposed topologywith the conventional topologies from aforementioned points ofview. Moreover, a new algorithm to determine the magnitude ofdc voltage sources is proposed. The performance and functionalaccuracy of the proposed topology using the new algorithm ingenerating all voltage levels for a 31-level inverter are confirmedby simulation and experimental results.

Index Terms—Cascaded multilevel inverter, developedH-bridge, multilevel inverter, voltage source inverter.

I. INTRODUCTION

NOWADAYS, multilevel inverters have received more at-tention for their ability on high-power and medium-

voltage operation and because of other advantages such as highpower quality, lower order harmonics, lower switching losses,and better electromagnetic interference [1], [2]. These invertersgenerate a stepped voltage waveform by using a number of dcvoltage sources as the input and an appropriate arrangement ofthe power-semiconductor-based devices [3].

Three main structures of the multilevel inverters have beenpresented: “diode clamped multilevel inverter,” “flying capaci-tor multilevel inverter,” and “cascaded multilevel inverter” [4].The cascaded multilevel inverter is composed of a number ofsingle-phase H-bridge inverters and is classified into symmetricand asymmetric groups based on the magnitude of dc voltagesources. In the symmetric types, the magnitudes of the dc volt-age sources of all H-bridges are equal while in the asymmetrictypes, the values of the dc voltage sources of all H-bridges aredifferent.

In recent years, several topologies with various control tech-niques have been presented for cascaded multilevel inverters[5]–[8]. In [4] and [9]–[15], different symmetric cascaded mul-tilevel inverters have been presented. The main advantage of allthese structures is the low variety of dc voltage sources, which

Manuscript received February 18, 2013; revised June 8, 2013; acceptedAugust 4, 2013. Date of publication October 21, 2013; date of current versionFebruary 7, 2014.

The authors are with the Faculty of Electrical and Computer Engineer-ing, University of Tabriz, Tabriz 51664, Iran (e-mail: [email protected];[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2013.2286561

is one of the most important features in determining the costof the inverter. On the other hand, because some of them use ahigh number of bidirectional power switches, a high number ofinsulated gate bipolar transistors (IGBTs) are required, whichis the main disadvantage of these topologies. An asymmetrictopology has been presented in [16]. The main disadvantageof this structure is related to its bidirectional power switches,which cause an increase in the number of IGBTs and thetotal cost of the inverter. In [15], a new topology with threealgorithms have been presented, which reduce the number ofrequired power switches but increase the variety of dc voltagesources. In [1], [4] and [17], and [18], several algorithmsfor determining the magnitudes of dc voltage sources for theconventional cascaded multilevel inverter have been presented.The major advantage of this topology and its algorithms isrelated to its ability to generate a considerable number of outputvoltage levels by using a low number of dc voltage sourcesand power switches but the high variety in the magnitude ofdc voltage sources is their most remarkable disadvantage.

In this paper, in order to increase the number of outputvoltage levels and reduce the number of power switches, drivercircuits, and the total cost of the inverter, a new topology ofcascaded multilevel inverters is proposed. It is important tonote that in the proposed topology, the unidirectional powerswitches are used. Then, to determine the magnitude of thedc voltage sources, a new algorithm is proposed. Moreover,the proposed topology is compared with other topologies fromdifferent points of view such as the number of IGBTs, numberof dc voltage sources, the variety of the values of the dcvoltage sources, and the value of the blocking voltages perswitch. Finally, the performance of the proposed topology ingenerating all voltage levels through a 31-level inverter isconfirmed by simulation using power system computer aideddesign (PSCAD) software and experimental results.

II. PROPOSED TOPOLOGY

In Fig. 1, two new topologies are proposed for a seven-levelinverter [19]. As shown in Fig. 1, the proposed topologies areobtained by adding two unidirectional power switches and onedc voltage source to the H-bridge inverter structure. In otherwords, the proposed inverters are comprised of six unidirec-tional power switches (Sa, Sb, SL,1, SL,2, SR,1, and SR,2) andtwo dc voltage sources (VL,1 and VR,1). In this paper, thesetopologies are called developed H-bridge. As shown in Fig. 1,the simultaneous turn-on of SL,1 and SL,2 (or SR,1 and SR,2)

0278-0046 © 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

BABAEI et al.: TOPOLOGY FOR CASCADED MULTILEVEL INVERTERS WITH REDUCED NUMBER OF COMPONENTS 3933

Fig. 1. Proposed seven-level inverters. (a) First proposed topology. (b) Secondproposed topology.

TABLE IOUTPUT VOLTAGES OF THE PROPOSED SEVEN-LEVEL INVERTERS

causes the voltage sources to short-circuit. Therefore, the si-multaneous turn-on of the mentioned switches must be avoided.In addition, Sa and Sb should not turn on, simultaneously. Thedifference in the topologies illustrated in Fig. 1 is in the connec-tion of the dc voltage sources polarity. Table I shows the outputvoltages of the proposed inverters for different states of theswitches. In this table, 1 and 0 indicate the ON- and OFF-statesof the switches, respectively. As it is obvious from Table I, ifthe values of the dc voltage sources are equal, the number ofvoltage levels decreases to three. Therefore, the values of dcvoltage sources should be different to generate more voltagelevels without increasing the number of switches and dc voltagesources. Considering Table I, to generate all voltage levels (oddand even) in the proposed topology shown in Fig. 1(a), themagnitudes of VL,1 and VR,1 should be considered 3pu and1pu, respectively. Similarly, for the topology shown in Fig. 1(a),the magnitudes of VL,1 and VR,1 should be considered 2pu and1pu, respectively. Considering the aforementioned explana-tions, the total cost of the proposed topology in Fig. 1(b) is lowbecause dc voltage sources with low magnitudes are needed.

By developing the seven-level inverter shown in Fig. 1(b),the 31-level inverter shown in Fig. 2 can be proposed. Thistopology consists of ten unidirectional power switches and fourdc voltage sources. According to Fig. 2, if the power switches of(SL,1, SL,2), (SL,3, SL,4), (SR,1, SR,2), and (SR,3, SR,4) turnon simultaneously, the dc voltage sources of VL,1, VL,2, VR,1,and VR,2 will be short-circuited, respectively. Therefore, thesimultaneous turn-on of these switches should be avoided. Inaddition, Sa and Sb should not turn on simultaneously. It isimportant to note that the 31-level topology can be providedthrough the structure presented in Fig. 1(a), where the only dif-ference will be in the polarity of the applied dc voltage sources.

By developing the proposed 31-level inverter, a 127-levelinverter can be proposed as shown in Fig. 3. This topology

Fig. 2. Proposed 31-level inverter.

Fig. 3. Proposed 127-level inverter.

Fig. 4. Proposed general topology.

consists of 14 unidirectional power switches and 6 dc voltagesources. Similarly, by developing the proposed basic topology,a general topology, as shown in Fig. 4, can be proposed. Thegeneral topology consists of 2n dc voltage sources (n is thenumber of the dc voltage sources on each leg) and 4n+ 2unidirectional power switches.

In the proposed general topology, the number of outputvoltage levels (Nstep), number of switches (Nswitch), numberof dc voltage sources (Nsource), and the maximum magnitudeof the generated voltage (Vo,max) are calculated as follows,respectively:

Nstep =22n+1 − 1 (1)

Nswitch =4n+ 2 (2)

Nsource =2n (3)

Vo,max =VL,n + VR,n. (4)


The other important parameters of the total cost of a mul-tilevel inverter for evaluation are the variety of the values ofdc voltage sources and the value of the blocking voltage of theswitches. As the variety of dc voltage sources and the value ofthe blocking voltage of the switches are low, the inverter’s totalcost decreases [20]. The number of variety of the values of dcvoltage sources (Nvariety) is given by

Nvariety = 2n. (5)

The following pattern is utilized to calculate the maximummagnitude of the blocking voltage of the power switches. Asshown in Fig. 1(b), the blocking voltage of SR,1 and SR,2 arecalculated as follows:

VSR,1 = VSR,2 = VR,1 (6)

where VSR,1 and VSR,2 indicate the maximum blocking volt-ages of SR,1 and SR,2, respectively.

The blocking voltage of SL,1 and SL,2 are as follows:

VSL,1 = VSL,2 = VL,1 (7)

where VSL,1 and VSL,2 indicate the maximum blocking voltagesof SL,1 and SL,2, respectively.

Therefore, the maximum blocking voltage of all switchesin the proposed seven-level inverter (Vblock,1) is calculated asfollows:

Vblock,1 =VSR,1 + VSR,2 + VSL,1 + VSL,2 + VSa + VSa

=4(VR,1 + VL,1). (8)

Considering Fig. 2, the maximum blocking voltage of theswitches is as follows:

VSR,1 =VSR,2 = VR,1 (9)

VSR,3 =VSR,4 = VR,2 − VR,1 (10)

VSL,1 =VSL,2 = VL,1 (11)

VSL,3 =VSL,4 = VL,2 − VL,1 (12)

VSa =VSb = VR,2 + VL,2. (13)

Therefore, the maximum blocking voltage of all switches of theproposed 31-level inverter (Vblock,2) is as follows:

Vblock,2 =VSR,1 + VSR,2 + VSR,3 + VSR,4 + VSL,1 + VSL,2

+ VSL,3 + VSL,4 + VSa + VSb

=4(VR,2 + VL,2). (14)

Similarly, the maximum blocking voltage of all switches of the127-level inverter is calculated as follows:

Vblock,3 = 4(VR,3 + VL,3). (15)

Finally, the maximum blocking voltage of all the switches ofthe general topology (Vblock,n) is calculated as follows:

Vblock,n = 4(VR,n + VL,n). (16)

III. PROPOSED ALGORITHM TO DETERMINE THE

MAGNITUDES OF DC VOLTAGE SOURCES

In this paper, the following algorithm is applied to determinethe magnitude of dc voltage sources. It is important to note thatall voltage levels (even and odd) can be generated.

A. Proposed Seven-Level Inverter

The magnitudes of the dc voltage sources of the seven-levelinverter shown in Fig. 1(b) are determined as follows:

VL,1 =Vdc (17)

VR,1 =2Vdc. (18)

Considering (17), (18), and Table I, the proposed seven-levelinverter can generate 0, ±Vdc, ±2Vdc, and ±3Vdc at output.

B. Proposed 31-Level Inverter

The magnitudes of the dc voltage sources of the proposed31-level inverter are recommended as follows:

VL,1 =Vdc (19)

VR,1 =2Vdc (20)

VL,2 =5Vdc (21)

VR,2 =10Vdc. (22)

The proposed inverter can generate all negative and positivevoltage levels from 0 to 15Vdc with steps of Vdc.

C. Proposed 127-Level Inverter

The magnitudes of the dc voltage sources of the proposed127-level inverter are calculated as follows:

VL,1 =Vdc (23)

VR,1 =2Vdc (24)

VL,2 =5Vdc (25)

VR,2 =10Vdc (26)

VL,3 =25Vdc (27)

VR,3 =50Vdc. (28)

By using this algorithm, the inverter can generate all negativeand positive voltage levels from 0 to 63Vdc with steps of Vdc.

D. Proposed General Multilevel Inverter

The magnitudes of the dc voltage sources of the proposedgeneral multilevel inverter can be obtained as follows:

VL,j =5j−1 Vdc for j = 1, 2, 3, . . . , n (29)

VR,j =2× 5j−1 Vdc for j = 1, 2, 3, . . . , n. (30)

Considering (4) and (16), the values of Vo,max and Vblock,n

of the proposed general multilevel inverter are as follows,


respectively:

Vo,max =VL,n + VR,n = 3× 5n−1Vdc (31)

Vblock,n =4(VL,n + VR,n) = 12(5n−1)Vdc. (32)

IV. CALCULATION OF LOSSES

Mainly, two kinds of losses (i.e., conduction and switchinglosses) are associated with the switches. Since the switchesinclude IGBTs and diodes, the conduction losses of an IGBT(pc,IGBT(t)) and a diode (pc,D(t)) are calculated as follows,respectively [7], [22]:

pc,IGBT(t) =[VIGBT +RIGBTi

β(t)]i(t) (33)

pc,D(t) = [VD +RDi(t)] i(t) (34)

where VIGBT and VD are the forward voltage drops of the IGBTand diode, respectively. RIGBT and RD are the equivalentresistances of the IGBT and diode, respectively, and β is aconstant related to the specification of the IGBT.

Considering that at instant t, there are NIGBT transistorsand ND diodes in the current path, the average value of theconduction power loss (Pc) of the multilevel inverter can bewritten as follows:

Pc =1

2π

2π∫0

[NIGBT(t)pc,T (t) +ND(t)pc,D(t)] dt. (35)

The switching losses are calculated based on the energyloss calculation. The switching losses occur during the turn-offand turn-on periods. For simplicity, the linear variations of thevoltage and current of the switches in the switching period areconsidered. Based on this assumption, the following relationscan be written [7], [22]:

Eoff,k =

toff∫

0

v(t)i(t)dt =1

6Vsw,kI toff (36)

Eon,k =

ton∫

0

v(t)i(t)dt =1

6Vsw,kI

′ ton (37)

where Eoff,k and Eon,k are the turn-off and turn-on losses ofthe switch k, respectively. toff and ton are the turn-off and turn-on times of the switch, respectively, I is the current through theswitch before turning off, I ′ is the current through the switchafter turning on, and Vsw,k is the OFF-state voltage on theswitch.

The switching power loss (Psw) is equal to the sum ofall turn-on and turn-off energy losses in a fundamental cy-cle of the output voltage. This can be written as follows[7], [22]:

Psw = f

Nswitch∑k=1

⎛⎝

Non,k∑i=1

Eon,ki +

Noff,k∑i=1

Eoff,ki

⎞⎠ (38)

where f is the fundamental frequency and Non,k and Noff,k

are the numbers of turn-on and turn-off of the switch k duringa fundamental cycle. Also, Eon,ki is the energy loss of theswitch k during the ith turn-on and Eoff,ki is the energy lossof the switch k during the ith turn-off.

The total loss (Ploss) of the multilevel converter is the sumof the conduction and switching losses as follows:

Ploss = Pc + Psw. (39)

Finally, the efficiency (η) of the inverter is calculated asfollows:

η =Pout

Pin=

Pout

Pout + Ploss(40)

where Pout and Pin denote the output and input powers of theinverter.

V. COMPARING THE PROPOSED GENERAL TOPOLOGY

WITH THE CONVENTIONAL TOPOLOGIES

In order to clarify the advantages and disadvantage of theproposed topology, it should be compared with the differentkinds of topologies presented in literature. In [4], the con-ventional cascaded multilevel inverter with two different algo-rithms has been presented. These algorithms are known as thesymmetric cascaded multilevel inverters and the asymmetricones with the binary method for determining the magnitudeof dc voltage sources. In the comparison, the conventionalsymmetric cascaded multilevel inverter is indicated by R1

and the conventional binary asymmetric cascaded multilevelinverter is shown by R2. Three other algorithms have beenpresented for this topology in [1], [17], and [18], which areindicated by R3–R5, respectively. Moreover, another topologywith three different algorithms for determining the value ofdc voltage sources have been introduced in [15], which areshown by R13–R15 in this comparison. In [9]–[12], four dif-ferent structures for the cascaded multilevel inverter have beenpresented, and in this paper, they are indicated by R6–R7 andR11–R12. It is important to note that the power switches in theaforementioned topologies are unidirectional. In addition, othertopologies based on bidirectional switches have been presentedin [13] and [14]. In [14], three different algorithms have beenrecommended, which are denoted as R8–R10, and the presentedtopology in [13] is indicated by R16 in this comparison. Fig. 5shows all of the aforementioned structures.

Fig. 6 compares the number of IGBTs of the proposedgeneral topology with the aforementioned cascaded multilevelinverters. It is obvious that the proposed inverter requires alesser number of IGBTs in comparison with the other men-tioned topologies to generate particular levels.

Fig. 7 compares the number of dc voltage sources of theproposed inverter with the aforementioned cascaded multilevelinverter. As shown in Fig. 7, the proposed inverter has betterperformance in comparison with the other presented topologiesexcept the topology presented in R3. However, the magnitudeof the dc voltage sources in R3 is a little more than that of theproposed topology.


Fig. 5. Cascaded multilevel inverters presented in literature: (a) Conventional cascaded multilevel inverters R1 for V1 = V2 = · · · = Vn = Vdc, R2 forV1 = 2j−1Vdc (j = 1, 2, . . . , n), R3 for V1 = 3j−1Vdc (j = 1, 2, . . . , n), R4 for V1 = 0.5V2 = 0.5V3 = · · · = 0.5Vn = Vdc, and R5 for V1 = V2/3 =V3/3 = · · · = Vn/3 = Vdc. (b) Presented topology in [12], namely, R12 for V1 = V2 = · · · = Vn = Vdc. (c) Presented topology in [10], i.e., R7 forV1 = V2 = · · · = Vn = Vdc. (d) Presented topology in [9], i.e., R6 for V1 = V2 = · · · = Vn = Vdc. (e) Presented topologies in [14], i.e., R8 for V1 = V2 =· · · = Vn = Vdc, R9 for V1 = 0.5V2 = 0.5V3 = · · · = 0.5Vn = Vdc, and R10 for V1 = 2j−1Vdc (j = 1, 2, . . . , n). (f) Presented topologies in [15], i.e.,R13 for V1 = V2 = · · · = Vn = Vdc, R14 for V1 = 2j−1Vdc (j = 1, 2, . . . , n), and R15 for V1 = 0.5V2 = 0.5V3 = · · · = 0.5Vn = Vdc. (g) Presentedtopology in [13], i.e., R16 for V1 = V2 = · · · = Vn = Vdc. (h) Presented topology in [11], i.e., R11 for V1 = V2 = · · · = Vn = Vdc.

Fig. 6. Variation of NIGBT versus Nstep.

Fig. 7. Variation of Nsource versus Nstep.

Fig. 8 compares the variety of magnitudes of the dc voltagesources of the proposed inverter with that of the aforemen-tioned cascaded multilevel inverter. Obviously, the proposed

Fig. 8. Variation of Nvariety versus Nstep.

inverter uses a wider variety of magnitudes of the dc voltagesources in comparison with those of all the aforementionedtopologies. This feature is the most important disadvantageof the proposed topology because the variety of the valuesof dc voltage sources is as one of the remarkable factors indetermining the cost of the inverter. However, this feature in theproposed topology is similar to the presented topologies of R2

and R14.Fig. 9 compares the magnitude of the blocking voltage of

the switches of the proposed inverter with that of the afore-mentioned cascaded multilevel inverter. This figure shows thereduction of the magnitude of the blocking voltage of theproposed inverter in comparison with those of all the aforemen-tioned multilevel inverters.


Fig. 9. Variation of Vblock versus Nstep.

TABLE IIOUTPUT VOLTAGES OF THE PROPOSED 31-LEVEL INVERTER

VI. SIMULATION AND EXPERIMENTAL RESULTS

In order to verify the correct performance of the proposedmultilevel inverter in generating all output voltage levels (evenand odd), a 31-level inverter based on the topology shownin Fig. 2 has been used for the simulation and experimentalprototypes. Table II shows the switching states of the 31-level

Fig. 10. Photograph of the experimental setup.

Fig. 11. Proposed 31-level inverter. (a) Output voltage waveform. (b) Outputcurrent waveform.

inverter. The simulation is done by using PSCAD software, andthe practical prototype is made in the experimental environ-ment. Fig. 10 shows the experimental setup. It is important tonote that the IGBTs used in the prototype are HGTP10N40CID(with an internal antiparallel diode) with the voltage and currentranges of 400 V and 10 A, respectively. The 89C52 micro-controller by ATMEL Company has been used to generateall switching patterns. In all processes of the simulation andexperiment, the load is assumed as R–L with R = 45Ω andL = 55 mH. Moreover, the magnitude of VL,1 is considered15 V, so based on (29) and (30), the magnitudes of the otherdc voltage sources will be 30, 75, and 150 V, which arerelated to VR,1, VL,2, and VR,2, respectively. According to (31),the maximum output voltage of this inverter will be 225 V.In this paper, the fundamental frequency switching controlmethod has been used [21]. In this method, the sinusoidalreference voltage is compared with the available dc voltagelevels and the level that is nearest to the reference voltageis chosen [22]. The main advantage of this control methodis related to its low switching frequency, which is leads toreduction of switching losses.

The simulated output voltage and current waveforms areshown in Fig. 11. As Fig. 11(a) shows, the proposed topologyis able to generate 31 levels (15 positive levels, 15 negativelevels, and 1 zero level) with the maximum voltage of 225 V.Comparing the output voltage and current waveforms indicatesthat the output current waveform is more similar to the idealsinusoidal waveform than the output voltage because the R–Lload acts as a low-pass filter. In addition, there is a phasedifference between the output voltage and current waveforms,which is caused by the inductive feature of the load. Thetotal harmonic distortions of the output voltage and currentare equal to 0.94% and 0.19%, respectively. Fig. 12(a) and (b)shows the harmonic spectrum of the output voltage and current,respectively. The figure shows that the magnitudes of harmonicsof both voltage and current waveforms are low. However, theharmonics of the current waveform are lower than the voltage


Fig. 12. Harmonic spectrum of (a) output voltage and (b) current.

waveform. It is important to note that in Fig. 12, in orderto show the magnitudes of the fundamental and high-orderharmonics, the scale of the vertical axis is considered nonlinear.In the test condition, the measured input and output powers areabout 1203 and 1112 W, respectively. Therefore, the efficiencyis about 92.4%. Based on the loss calculations given before, thepower loss is about 86 W. Therefore, the calculated loss has agood accordance with the measured efficiency.

As mentioned before, the power switches in the proposedtopology are unidirectional from the voltage viewpoint. In orderto prove this issue, the voltages on the switches of a single legof the inverter (i.e., SL,1, SL,2, SL,3, SL,4, and Sa) are shownin Fig. 13. As can be seen, the maximum blocking voltage byswitches SL,1, SL,2, SL,3, SL,4, and Sa are equal to 15, 15, 60,60, and 225 V, respectively. Obviously, the voltage values arezero or equal to the positive ones, which is well in accordanceto the unidirectional feature of the switches from the voltageviewpoint. Considering the magnitude of the blocking voltageof the switches, the relations associated to the maximum volt-age drop of the switches are well confirmed. Fig. 14 shows theexperimental results of the implemented inverter. It is importantto note that there is a good agreement between the experimentaland simulation results.

VII. CONCLUSION

In this paper, two basic topologies have been proposed formultilevel inverters to generate seven voltage levels at theoutput. The basic topologies can be developed to any number oflevels at the output where the 31-level, 127-level, and generaltopologies are consequently presented. In addition, a new algo-rithm to determine the magnitude of the dc voltage sources hasbeen proposed. The proposed general topology was comparedwith the different kinds of presented topologies in literaturefrom different points of view. According to the comparison re-sults, the proposed topology requires a lesser number of IGBTs,power diodes, driver circuits, and dc voltage sources. Moreover,the magnitude of the blocking voltage of the switches is lower

Fig. 13. Voltages of switches (a) SL,1, (b) SL,2, (c) SL,3, (d) SL,4, and(e) Sa.

Fig. 14. Experimental results: (a) Output voltage and output current voltage;(b) SL,1; (c) SL,2; (d) SL,3; (e) SL,4; and (f) Sa.

than that of conventional topologies. However, the proposedtopology has a higher number of variety of dc voltage sourcesin comparison with the others. The performance accuracy of theproposed topology was verified through the PSCAD simulationand the experimental results of a 31-level inverter.


REFERENCES

[1] E. Babaei and S. H. Hosseini, “Charge balance control methods for asym-metrical cascade multilevel converters,” in Proc. ICEMS, Seoul, Korea,2007, pp. 74–79.

[2] K. Wang, Y. Li, Z. Zheng, and L. Xu, “Voltage balancing and fluctuation-suppression methods of floating capacitors in a new modular multilevelconverter,” IEEE Trans. Ind. Electron., vol. 60, no. 5, pp. 1943–1954,May 2013.

[3] J. Ebrahimi, E. Babaei, and G. B. Gharehpetian, “A new topology ofcascaded multilevel converters with reduced number of components forhigh-voltage applications,” IEEE Trans. Power Electron., vol. 26, no. 11,pp. 3109–3118, Nov. 2011.

[4] M. Manjrekar and T. A. Lipo, “A hybrid multilevel inverter topology fordrive application,” in Proc. APEC, 1998, pp. 523–529.

[5] M. Narimani and G. Moschopoulos, “A novel single-stage multilevel typefull-bridge converter,” IEEE Trans. Ind. Electron., vol. 60, no. 1, pp. 31–42, Jan. 2013.

[6] N. Abd Rahim, M. F. Mohamad Elias, and W. P. Hew, “Transistor-clampedH-bridge based cascaded multilevel inverter with new method of capacitorvoltage balancing,” IEEE Trans. Ind. Electron., vol. 60, no. 8, pp. 2943–2956, Aug. 2013.

[7] M. Farhadi Kangarlu and E. Babaei, “A generalized cascaded multilevelinverter using series connection of submultilevel inverters,” IEEE Trans.Power Electron., vol. 28, no. 2, pp. 625–636, Feb. 2013.

[8] S. R. Pulikanti, G. Konstantinou, and V. G. Agelidis, “Hybrid seven-levelcascaded active neutral-point-clamped-based multilevel converter underSHE-PWM,” IEEE Trans. Ind. Electron., vol. 60, no. 11, pp. 4794–4804,Nov. 2013.

[9] Y. Hinago and H. Koizumi, “A single-phase multilevel inverter usingswitched series/parallel dc voltage sources,” IEEE Trans. Ind. Electron.,vol. 57, no. 8, pp. 2643–2650, Aug. 2010.

[10] G. Waltrich and I. Barbi, “Three-phase cascaded multilevel inverter usingpower cells with two inverter legs in series,” IEEE Trans. Ind. Appl.,vol. 57, no. 8, pp. 2605–2612, Aug. 2010.

[11] W. K. Choi and F. S. Kang, “H-bridge based multilevel inverter usingPWM switching function,” in Proc. INTELEC, 2009, pp. 1–5.

[12] E. Babaei, M. Farhadi Kangarlu, and F. Najaty Mazgar, “Symmetricand asymmetric multilevel inverter topologies with reduced switchingdevices,” Elect. Power Syst. Res., vol. 86, pp. 122–130, May 2012.

[13] J. Ebrahimi, E. Babaei, and G. B. Gharehpetian, “A new multilevel con-verter topology with reduced number of power electronic components,”IEEE Trans. Ind. Electron., vol. 59, no. 2, pp. 655–667, Feb. 2012.

[14] E. Babaei, S. H. Hosseini, G. B. Gharehpetian, M. Tarafdar Haque, andM. Sabahi, “Reduction of DC voltage sources and switches in asymmetri-cal multilevel converters using a novel topology,” Elect. Power Syst. Res.,vol. 77, no. 8, pp. 1073–1085, Jun. 2007.

[15] E. Babaei and S. H. Hosseini, “New cascaded multilevel inverter topologywith minimum number of switches,” Energy Convers. Manage., vol. 50,no. 11, pp. 2761–2767, Nov. 2009.

[16] S. Mekhilef and M. N. Kadir, “Voltage control of three-stage hybrid multi-level inverter using vector transformation,” IEEE Trans. Power Electron.,vol. 25, no. 10, pp. 2599–2606, Oct. 2010.

[17] A. Rufer, M. Veenstra, and K. Gopakumar, “Asymmetric multilevel con-verter for high resolution voltage phasor generation,” presented at theProc. EPE, Lausanne, Switzerland, 1999.

[18] S. Laali, K. Abbaszades, and H. Lesani, “A new algorithm to determinethe magnitudes of dc voltage sources in asymmetrical cascaded multilevelconverters capable of using charge balance control methods,” in Proc.ICEMS, Incheon, Korea, 2010, pp. 56–61.

[19] S. Alilu, E. Babaei, and S. B. Mozafari, “A new general topology formultilevel inverters based on developed H-bridge,” in Proc. PEDSTC,Tehran, Iran, 2013, pp. IR-113–IR-118.

[20] E. Babaei, “A cascade multilevel converter topology with reduced numberof switches,” IEEE Trans. Power Electron., vol. 23, no. 6, pp. 2657–2664,Nov. 2008.

[21] J. Rodriguez, L. G. Franquelo, S. Kouro, J. I. Leon, R. C. Portillo,M. A. M. Prats, and M. A. Perez, “Multilevel converters: An enablingtechnology for high power applications,” Proc. IEEE, vol. 97, no. 11,pp. 1786–1817, Nov. 2009.

[22] M. Farhadi Kangarlu and E. Babaei, “Cross-switched multilevel inverter:An innovative topology,” IET Power Electron., vol. 6, no. 4, pp. 642–651,Apr. 2013.

Ebrahim Babaei (M’10) was born in Ahar, Iran,in 1970. He received the B.S. and M.S. degrees inelectrical engineering from the Department of Engi-neering, University of Tabriz, Tabriz, Iran, in 1992and 2001, respectively, graduating with first classhonors, and the Ph.D. degree in electrical engineer-ing from the Department of Electrical and ComputerEngineering, University of Tabriz, in 2007.

In 2004, he joined the Faculty of Electrical andComputer Engineering, University of Tabriz. He wasan Assistant Professor from 2007 to 2011 and has

been an Associate Professor since 2011. He is the author of more than230 journal and conference papers. His current research interests include theanalysis and control of power electronic converters, power system transients,and power system dynamics.

Somayeh Alilu was born in Khoy, Iran, in 1983. Shereceived the B.S degree in electronics engineeringfrom Islamic Azad University, Tabriz, Iran, in 2007and the M.S degree in electrical engineering from theScience and Research Branch, Islamic Azad Univer-sity, Tehran, Iran, in 2013.

She is currently with the Faculty of Electrical andComputer Engineering, University of Tabriz, Tabriz.

Sara Laali (S’12) was born in Tehran, Iran, in 1970.She received the B.S. degree in electronics engineer-ing from Islamic Azad University, Tabriz, Iran, in2008 and the M.S. degree in electrical engineeringfrom Islamic Azad University, Tehran, Iran, in 2010.She is currently working toward the Ph.D. degree inelectrical engineering in the Faculty of Electrical andComputer Engineering, University of Tabriz, Tabriz.

In 2010, she joined the Department of Electri-cal Engineering, Adiban Higher Education Institute,Semnan, Iran. Her major fields of interest include the

analysis and control of power electronic converters.

a new general topology for cascaded multilevel inverters

Documents