56

CHAPTER 3

CASCADED MULTILEVEL INVERTERS

3.1 INTRODUCTION

To implement STATCOM at meaningful Mega Volt Ampere

(MVA) level, a high power VSC is needed. But semiconductor devices are

limited to operate in high current and voltage ratings and hence it is

difficult to connect a semiconductor switch directly to medium voltage

networks (2.3-6.9 kV). One solution to this problem is to use multilevel

VSC to increase the output voltage. Multi Level Inverters (MLI) contains

several power semiconductors and capacitor voltage sources (Tolbert et al.

1999). Output voltages of MLIs include the additions of the capacitor

voltages due to the commutation of the switches (Lai and Peng et al. 1996).

(a) Two levels, (b) Three levels and (c) n levels

Figure 3.1 One phase leg of an inverter

57

Figure 3.1 shows a schematic diagram of one phase leg of

inverters with several numbers of levels. The power semiconductor is

represented by an ideal switch. A 2-level inverter, as shown in

Figure 3.1 (a), generates an output voltage of 2-levels with respect to the

negative terminal of the capacitor, while the 3-level inverter shown in

Figure 3.1 (b) generates three voltages, and so on. Thus, the output

voltages of multilevel inverters have several levels and they can reach high

voltages with n number of levels (Tolbert et al. 1999).

MLIs have been receiving increasing attention in recent years

because they have many attractive features when compared to the

conventional bipolar inverters (Peng and Lai 1997, Peng 2001).

The features are:

The output voltage distortion is very low due to multiple levels

in the output voltages

The rate of change of voltage dv/dt of switches is low since the

switches endure reduced voltage and due to the lower voltage

swing of each switching cycle

The switches can operate at a lower switching frequency

The common-mode voltages can be eliminated using

sophisticated modulation methods (Rodriguez et al. 2004)

The voltage stress on each switch is decreased due to series

connection of the switches

The rated voltage and total power of the inverter could be safely

increased

58

The THD and filters are reduced due to more output levels

Low acoustic noise and Electro Magnetic Interference (EMI)

can be obtained

The MLI based STATCOM can be directly connected to the

grid without the bulky step-up transformer, resulting in cost and

weight reduction

The MLIs can also respond within 1 ms much faster than the

conventional PWM converters and Advanced Static Var

Compensators (ASVCs) do (Kumar et al. 2010)

The unwanted effects caused by the line frequency converter

transformer such as saturation and DC magnetization can also

be eliminated

A voltage level of three is considered to be the smallest number

in multilevel converter topologies. By switching the main power

semiconductor devices even at the line frequency, a sinusoidal output

voltage waveform with fast system response with a sufficiently high

number of voltage levels can be obtained. This naturally minimizes the

entire system losses and the output filter requirement. In addition, by

adding more H-bridge converters, the amount of var can be simply

increased without redesign of the power stage, and build-in redundancy

against individual H-bridge converter failure can be realized (Peng et al.

1996). Moreover, a three-phase Cascaded Multilevel Converter (CMC)

topology generates different output voltage waveforms and offers the

potential for AC system phase-balancing. This feature is impossible in

other VSC topologies utilizing a common DC link (Alhadidi et al. 2003,

59

Garica and Garica 2000, Lehn et al. 2002). A great combination of the

STATCOM concept and the CMC topology is a promising controller in the

modern FACTS technology (Rodriguez et al. 2002).

3.2 TOPOLOGIES OF MULTILEVEL INVERTERS

Traditional magnetic transformer coupled multipulse VSC has

been a well-known method and has been implemented in 18 and 48 pulse

converters for battery energy storage and STATic CONdenser

(STATCON) applications, respectively (Walker 1990). These converters

typically synthesize the staircase voltage wave by varying transformer

turns ratio with complicated zigzag connections (Lai and Peng 1996).

Problems of the magnetic transformer coupling method are bulky, heavy,

and lossy. The capacitor voltage synthesis method is thus preferred when

compared to the magnetic coupling method. There are three major

capacitor-voltage synthesis-based multilevel converters, listed as follows:

Diode-clamped multilevel converter

Flying-capacitor multilevel converter

Cascaded converters with separated DC sources

3.2.1 Diode-Clamped Multilevel Converter

The Diode Clamped Multi Level Inverter (DCMLI) also called

the Neutral-Point Clamped (NPC) inverter was presented in 1980

(Bhagwat and Stefanovic 1983). Because the NPC inverter effectively

doubles the device voltage level without requiring precise voltage

matching, this circuit topology prevailed in 1980s. Figure 3.2 shows the

power circuit of one phase leg of a 5-level Diode-Clamped Multilevel

60

Converter (DCMC) or NPCMC. In this topology, semiconductor devices

are connected in series and DC link is divided into smaller capacitors and

connects to switches by clamp diodes. The clamp diode connections are

used to block the current and their numbers in each leg is selected in such a

way so as to have the same block voltages. To generate M voltage levels,

M-1 capacitors are needed on the dc bus (Hosseini Aghdam et al. 2008).

The ground point shown in the Figure 3.2 is the common reference point

and is connected to the middle of DC link. For example, in a 5-level

inverter shown in Figure 3.2, DC bus voltage consists of four capacitors:

C1, C2, C3 and C4. For a DC link voltage of Vdc, the capacitors voltages will

be Vdc/4.

Figure 3.2 Power circuit of one phase leg of a 5-level DCMLI

Table 3.1 shows the phase voltage levels and their

corresponding switch states. Since all the devices are switched at the

fundamental frequency, the efficiency is high. In Table 3.1, state 1

represents that the switch is ON, and state 0 represents that the switch is

61

OFF. In each phase leg, a set of four adjacent switches is switched ON at

any given time.

Table 3.1 Diode-Clamped 5-level converter voltage levels

and their switch states

OutputSwitch state

S1 S2 S3 S4 S5 S6 S7 S8Vdc/2 1 1 1 1 0 0 0 0

Vdc/4 1 1 1 1 1 0 0 0

0 0 0 1 1 1 1 0 0

-Vdc/4 0 0 0 1 1 1 1 0

-Vdc/2 0 0 0 0 1 1 1 1

Since in DCMLI topology switches should withstand the DC

link voltage, this topology uses high voltage power electronic switches.

DCMLI generates high and steep voltage steps which may affect the life

time of the load; therefore, filters are needed to reduce the ripple in the

inverter output voltage. However these filters are usually heavy and

expensive. In this topology excessive clamping diodes are required.

Real power flow control for the individual is difficult. The main drawback

of DCMLI is the unbalanced DC link capacitor. It restricts the application

of DCMLI to 5 or less number of levels.

3.2.2 Flying-Capacitor Multilevel Converter

The Capacitor-Clamped Multi Level Inverter (CCMLI) or

Flying Capacitor Multi Level Inverter (FCMLI) emerged in the 1990s.

Figure 3.3 shows a 5-level Flying Capacitor Multilevel Converter (FCMC)

62

topology or Capacitor Clamped Multilevel Converter (CCMC).

The voltage level in the FCMC is similar to that of the DCMC. In this

topology the connecting points of the semiconductor devices connected in

series are clamped by extra capacitors. The series connections of clamped

capacitors are necessary to block the current and their numbers in each leg

are selected in such a way that all the capacitors store the same energy.

In this way large and heavy capacitors will not be needed. The output

voltage is symmetric with respect to the neutral point. There is no

interconnection in the three interior loops between balancing capacitors Ca,

Cb and Cc to the DC link sources for each phase, like the DCMC topology.

Table 3.2 shows a possible switch combination of the voltage levels and

their corresponding switch states.

Figure 3.3 Power circuit of one phase leg of a 5-level FCMC

63

Table 3.2 Flying Capacitor 5-level voltage levels and

their corresponding switch states

OutputSwitch state

S1 S2 S3 S4 S5 S6 S7 S8Vdc/2 1 1 1 1 0 0 0 0

Vdc/4 1 1 1 0 1 0 0 0

0 1 1 0 0 1 1 0 0

-Vdc/4 1 0 0 0 1 1 1 0

-Vdc/2 0 0 0 0 1 1 1 1

In FCMC there is more than one combination that can produce

output voltages. This feature of FCMC makes it more flexible than the

DCMC. By nature of this topology, however, the CMC is impossible to

apply in intertie or back-to-back applications, such as Unified Power Flow

Controller (UPFC). Connecting separate DC sources between two

converters in a back-to-back arrangement is not possible because a short

circuit will be introduced when back-to-back converters are not switching

simultaneously. For back-to-back intertie system for UPFC, DCMLI is

most suitable because other two types may require more switching per

cycle and more sophisticated control to balance the voltage.

3.2.3 Cascaded-Multilevel Converters with Separated DC Sources

The Cascade Multilevel Inverter (CMI) was first proposed in

1975 (Ooi et al. 1999, Patil et al. 1999). Separate DC sourced full-bridge

cells are placed in series to synthesize a staircase AC output voltage.

This structure uses cascaded inverters with Separate DC Sources (SDCSs).

This topology includes several H Bridge cells, i.e., Full Bridge Inverters

64

(FBI) connected in series as shown in Figure 3.4 (a). A desired voltage is

synthesized from several independent sources of DC voltages obtained

from batteries, capacitors, fuel cells or solar cells (Mathur and Seyezhai

2008). CMC configuration is increasingly used at high power area due to

its direct high voltage output with no need of a transformer (Sirisukprasert

2004).

Figure 3.4(a) Single phase leg structure of a CMC with SDCS

Figure 3.4(b) Individual H-Bridge cell of a CMC

65

The number of output phase voltage levels in a CMC is defined

by M=2s+1; where s is the number of DC sources and M is the output

phase voltage level. By controlling the conducting angles at different

converter levels minimum THD can be obtained. Compared to DCMC and

FCMC, CMC is easy to design and assemble because of the uniform circuit

structure of the converter units. The voltage level of the inverter can be

increased in multiples of two by changing the number of FBI i.e., adding

additional bridge inverter cells to each phase limb.

The proposed structure of the single phase 5-level CMC consists

of eight semiconductor switching devices and two SDCS connected to a

single phase FBI/H-bridge inverter as shown in Figure 3.5.

(a) Mode 1 (b) Mode 2

(c) Mode 3 (d) Mode 4

Figure 3.5 Switching modes of 5-level CMC

66

Table 3.3 CMC 5-level voltage levels and their corresponding

switch states

OutputSwitch state

S1 S2 S3 S4 S5 S6 S7 S8

+Vdc 1 0 0 1 1 1 0 0

-Vdc 0 1 1 0 0 0 1 1

0 0 0 0 0 0 0 0 0

+2Vdc 1 0 0 1 1 0 0 1

-2Vdc 0 1 1 0 0 1 1 0

Each inverter level can generate five different voltage outputs,

+2Vdc, +Vdc, 0, and -Vdc, -2Vdc by connecting the DC source to the AC

output by different combinations of the four switches as shown in

Table 3.3. Switches S1, S2, S3, S4, S5, S6, S7 and S8 are switched in different

modes of switching sequences to generate output voltages across AB of the

H-bridge module. Table 3.3 shows one possible switching state to produce

a 5-level output voltage (Marchesoni and Tenca 2002).

3.2.4 Comparison of Power Component Requirements among

Multilevel Converters

Among the three types of multilevel converters (DCMC, FCMC

and CMC) the CMC is easy to design and assemble. The voltage synthesis

in a FCMC has more flexibility than a DCMC. From comparison as shown

in Table 3.4, it shows that the CMC type is more advantageous when

compared to other types where additional diodes and capacitors are

required (Peng et al. 1998). The CMC uses the least number of power

components, but requires separate isolated power sources for each inverter

67

cell. This would normally entail using a large isolation transformer. But for

this only requirement, a CMC is superior to other types and hence it is best

suited for high power applications. Table 3.4 compares the main power

component requirements per phase leg among these three multilevel VSCs,

where M is the number of voltage levels.

Table 3.4 Comparison among multilevel converters based on power

component requirements for phase leg

Converter

configuration

Diode clamped

(DCMC)

Flying

capacitors

(FCMC)

Cascaded

multilevel

(CMC)

No of switching

devices 2(M-1) 2(M-1) 2(M-1)

No of Diodes 2(M-1) 2(M-1) 2(M-1)

No of clamping

diodes(M-1)(M-2) 0 0

DC bus

capacitors(M-1) (M-1) (M-1)/2

Balancing or

clamping

capacitors

0 (M-1)(M-2)/20

Total M2+2M-3 (M2+7M-8)/2 (7/2)(M-1)

In Table 3.4, the number of main switches and main diodes

needed by each converter to achieve the same number of voltage levels is

the same. But DCMC needs extra clamping diodes, FCMC needs extra

balancing capacitors and CMC needs extra DC bus capacitors. So the total

devices for each converter are different (Tolbert et al. 2002). Even though

68

the CMC needs more capacitors when compared to those needed in the

DCMC, this is not considered to be a disadvantage in STATCOM

applications.

An Ultra CAPacitor (UCAP) bank or a Superconducting

Magnetic Energy Storage (SMES) module for example, can be individually

integrated with each H-bridge converter to enable real power compensation

capability in a STATCOM system. Since each inverter can be seen as a

module with similar circuit topology, control structure and modulation,

incase of a fault in one of these modules, it is possible to replace it quickly

and easily. It is possible to bypass the faulty module without stopping the

load, bringing a continuous overall availability, using an appropriate

control strategy. The reduction in number of devices used in a 5-level

CMLI when compared to conventional inverters is shown in Table 3.5.

Table 3.5 Comparison of number of devices required per phase

Devices used

per phase

Conventional

Inverters CMLI

Main power

switches8 5

Diodes 20 8

Capacitors 4 2

For the more than three level configuration used in high voltage

var compensation application like STATCOM, the DCMC voltage-

imbalance problem cannot be overcome by utilizing control techniques

only (Peng and Lai 1997). Either oversized capacitors or complex balance

circuits are absolutely required. This makes the DCMC unsuccessful in

69

such applications. Similarly in the FCMC topology, an unacceptable

amount of capacitance is required for high voltage levels. In the 7-level

FCMC converter, 15 clamping capacitors plus six DC-link capacitors are

required per phase to achieve the same voltage rating achieved by utilizing

three capacitors in the CMC topology. This requirement makes the system

less cost-effective and they also induce a severe voltage-imbalance

problem in the transient period and at the steady state.

3.2.5 Proposed Asymmetric Cascaded Multilevel Converter

An Asymmetric CMC (ACMC) consists of unequal capacitor

voltages. Instead of using an identical DC link for every H-bridge

converter, different DC links can be used to synthesize a greater number of

output voltage levels without any additional complexity to the existing

topology. A MLI with k partial inverters connected in series is shown in

Figure 3.6. Each cell is supplied by an unequal DC voltage source.

To determine the voltage levels among different DC links, a binary system

can be effectively used, i.e., 1Vdc, 2Vdc, 4Vdc 2(N-1) Vdc, where N is the

number of H-bridge converters in one phase leg.

The proposed work focuses on ACMC with two unequal DC

sources in each phase to generate seven level equal step multilevel outputs.

This structure is favorable for high power applications since it provides

higher voltage at higher modulation frequencies with a low switching

(carrier) frequency. It means low switching loss for the same THD. It also

improves the reliability by reducing the number of DC sources. However

increased rating of the switches is required for ACMC to withstand the

whole DC bus.

70

Figure 3.6 Asymmetric cascaded-multilevel converter

3.3 MODULATION STRATEGIES

The function of a modulation strategy is to force the inverter

voltages/currents to follow the reference voltages/currents. The modulation

strategies for inverters can be divided into two categories: The voltage

modulation strategies and the current modulation strategies. The output

voltages of the inverter will follow the reference voltages. In the

applications of multilevel inverters, the voltage-mode control systems are

much more popular than the current-mode control systems. The reason is

that the current-mode control systems usually require very high switching

frequencies for smoothing currents.

Most multilevel inverters are used in high-voltage and high-

power applications where the power semiconductor switches cannot switch

at very high frequencies. With the voltage-mode control, contrarily, the

inverter can switch at lower frequencies, even at line-frequency for the

cases of multilevel inverters. Hence in this chapter, only the modulation

strategies for the voltage-mode control will be investigated. Depending on

71

their switching frequency, modulation techniques for multilevel

applications can be classified into the following main groups:

1. Fundamental Frequency Switching (FFS), where each inverter

has only one commutation per cycle.

Selective Harmonic Elimination (SHE) (Mathur and

Seyezhai 2008)

2. High Frequency Switching (HFS), where each inverter has

several commutations per cycle.

Space Vector PWM (SV-PWM) technique

Carrier-Based PWM technique (Leon et al. 1998)

Sinusoidal PWM (Multicarrier PWM)

In all these methods a reference signal is compared to a carrier

signal and output state is selected based on which signal is higher at any

moment. In selection of carrier and reference signals there are some points

which are mentioned below:

Carrier signal is usually a symmetric triangular wave, but a saw

tooth wave can be used either. An important fact is that the symmetric

signal generates fewer harmonics. The reference signal can be continuous

or sampled but synchronous with carrier signal. The second method usually

generates fewer harmonics. Since now-a-days digital controllers are used,

this method is preferred (Veenstra and Rufer 2000).

72

Advantages of FFS

Eliminates low order harmonics in order to reduce the distortion

in the output voltage (Tolbert et al. 1999, Rodrigue et al. 2007).

Disadvantages of FFS

It has no significant effect on higher order harmonics (Zhang

and Fahmi 2003, Chiasson et al. 2003)

Complex calculations are involved in calculating the switching

angles and transferring to a digital system

Results in unbalanced power distribution

With a multi-pulse transformer, this power imbalance can lead

to a distorted input current

Switching losses are high

Different absorbed active power due to different voltage levels

aggravates the DC link voltage imbalance

Advantages of Space Vector PWM Strategy

Enhanced output voltage

Reduction of harmonics

Considerable reduction in THD (Kumar et al. 2008)

73

Disadvantages of Space Vector PWM Strategies

Implementation of space vectors require DSP

High Cost and Complexity involved in implementation

3.3.1 Carrier based PWM

Among various PWM control techniques, the most popular one

is the Multi Carrier PWM (MCPWM) which shifts the harmonics to high

frequencies by using high frequency carriers (Visser et al. 2002).

As electronic devices have limited switching frequencies, high switching

carriers are limited by this constraint (McGrath and Holmes 2000).

Carrier based technique is based on the comparison of a specific sinusoidal

reference signal with high frequency modulator carrier signals as shown in

Figure 3.7 which are usually selected triangular and modified in phase or

vertical positions to reduce the output voltage harmonic content. These

methods have been used widely for switching of multilevel inverters due to

their simplicity, flexibility and reduced computational requirements

compared to FFS and SVM (Ainsworth et al. 2003). The main advantage of

PWM converters is the possibility of controlling the converter gain and

consequently the converter output voltage (Hanson et al. 2002). In the most

popular PWM method, the width of each pulse is varied in proportion to

the amplitude of a sine waveform.

This triangular carrier signal reduces noises in the system ripple

current, harmonics distortion acoustic noise. The comparison of this signal

with a triangular generates the system output (Figure 3.7). Whenever the

reference sinusoidal signal is greater than the triangular wave; the VSI is

fired to switch a positive output and vice-versa for a negative output. It can

74

be seen that the fundamental component of the resulting output voltage is

equal to the reference sinusoid (Liang and Nwankpa 1999).

The number of switching per cycle is a constant predictable

value with the voltage controlled PWM and is determined by the ratio of

triangle-wave modulation frequency to system frequency, or frequency

modulation ratio, mf. The triangular or carrier waveform has a certain

switching frequency, which establishes the frequency at which the

converter switches. The frequency of the carrier waveform determines the

fundamental frequency of the output voltage.

control

carrierf f

fm (3.1)

By varying the amplitude of the control waveform from zero to

the amplitude of the carrier waveform the pulse width can be varied from

0 to 1800. The amplitude modulation ratio ma defines the ratio between the

control and carrier waveforms:

carrier

controla A

Am (3.2)

FrequencySystemFrequency

WaveTriangular

cycleperswitchingsOFForONofNumber

(3.3)

The shortest switching time will always occur at the peaks of the

reference sinusoid. The closer the modulation index is to one, the shorter

this switching time will be, assuming over modulation does not occur

(Michael et al. 1998).

75

Figure 3.7 SPWM modulation

The modulation index can be reduced by increasing the

capacitor voltage, thereby increasing the minimum switching time

(Phoivos D. Ziogas 1981, Jeevananthan et al. 2004, Enjeti et al. 1988).

statesteadyvoltagecapacitor1indexModulation (3.4)

With CMC, the maximum modulation index for linear operation

can be high under fundamental frequency mode. For a Multilevel inverter

say a M-level inverter, (M-1) carrier waves are compared with a controlled

sinusoidal modulating signal. The cross over points is used to determine

the switching instants. For a 5-level inverter, a modulating signal and

4 carrier waves are required for each phase of the inverter (Joos et al.

1998).

The widely used MCPWM methods are Phase Shifted (PS),

Phase Disposition (PD), Phase Opposition Disposition (POD) and

Alternative Phase Opposite Disposition (APOD). The methods used for

76

diode-clamped inverter application (PD, POD and APOD) are derived from

the disposition of carriers. If all carriers are selected with the same phase,

the method is known as PD method. A sinusoidal reference waveform is

compared with vertically shifted carrier waveforms.

Figure 3.8 Multilevel SPWM with PS method

in a 7-level inverter

In POD method, the carriers above the zero line of reference

voltage are out of phase and with the carriers below this line is by 180.

Compared to the PD method, this method has better results with reference

to harmonic performances in lower modulation indices. In POD method,

there is no harmonic at the carrier frequency.

The third group is known as APOD method. Each carrier of this

method is phase shifted by 180 from its adjacent one. POD and APOD

77

methods are exactly the same for a 3-level Inverter. The major difference

in APOD is the presence of the larger amount of third order harmonics.

But the third order harmonics is not considered because it gets cancelled in

line voltages. This method results in a better THD for line voltages when

compared with the POD method.

Figure 3.8 shows PS method in a 7-level CMC. With the two

multilevel SPWM, the dominant lower order harmonics are pushed to

around (M-1)fsw, where fsw is the switching frequency of power

semiconductor devices. In other words, equivalent switching frequency of

the inverter is (M-1) fsw.

In the PS method which is being widely used in cascaded

topologies, all triangular carrier signals have the same amplitude and

frequency but they are phase shifted by 90 to each other so that the output

voltage of every H-bridge is time shifted which leads to the equivalent

switching frequency of the summed output voltage being increased, then

the output harmonic content is reduced without increasing the switching

frequency (Liang et al. 1999).

In the PS method the harmonics of the resultant STATCOM

output voltage only appear as sidebands centered around the frequency of

2Nfs (where N is the No. of H bridge inverters and fs is the frequency of

triangular carrier signals) and its multiples so that the voltage across the

DC capacitor of each inverter is the same. Hence the resultant STATCOM

output voltage has very high equivalent switching frequency even if the

switching frequency of the individual switches is not so high. It is

generally accepted that PS method results in lower distortion factors in the

inverter output voltage for all modulation indices (Calais et al. 2001).

78

PS multicarrier PWM method provides equal switching stress

and power handling for all the cascaded units. The multilevel cascaded

topology with PS carrier reduces effective switching delay due to PWM

and ripple magnitude in the current error. The H-bridge inverters share the

same modulating sinusoidal signal. Frequency ratio of the carrier and

modulating sinusoidal signal is

Kc = fc/fs (3.5)

The period of triangular carrier

c = 2 /Kc (3.6)

For n number of modules in cascaded inverters, the triangular

carrier is phase shifted by

sh = c/2n = 2 /2nKc (3.7)

The output voltage equivalent frequency ratio is

Keff = 2nKc (3.8)

If n=3, the equivalent switching frequency of the output voltage

is 6fs.

With regard to modulation, the most popular SPWM control

technique for the NPCMLI and the FCMLI is the PD method. The most

popular SPWM control technique for the CCMLI is the PS method.

However, examining the frequency spectrum of the output phase voltage of

the three types of multilevel inverters, the same value of THD can be

obtained when SPWM multi-carrier with PD carriers and SPWM with PS

carriers are used.

79

3.4 POWER FLOW SOLUTIONS

Most researchers and industries use Newton-Raphson method of

iterative solution (Saadat 1992, Juan 2006, Hieu Le Nguyen 1997, Ghadir

Radman 2007). While traditional power flow program do not include

FACTS controllers, papers have been published dealing with power flow

problem considering FACTS controllers (Ge 1999, Chung 2005, Zhang

2003). Undoubtedly, an important part of power system study is power

flow, thus for power flow control of a system, it is very important to

include this new proposed CMC based controller in power flow equations.

A power flow study will provide extensive information about

the systems state, weaknesses and possible expansion opportunities.

The most important information given by the power flow is the voltage and

phase angle at each node. Real and reactive power may also be obtained,

though the accuracy of the output depends on the system status.

Power flow solutions base themselves on system constraints and

assumptions, the single-phase representation of the voltage, phase angle,

and power are shown below :

N

1nininniini -cosVVYP (3.9)

N

1nininniini -sinVVYQ (3.10)

These polar forms of the power flow equations provide the real

and reactive net calculated values. On a theoretical basis, the equation

would work according to the conservation of energy. Since there are losses

in the systems that need to be taken into account, the theoretical equations

will have a disparity of Pi and Qi. The power flow calculation hence

80

depends on the quantities Vi, Vn, Pi, and Qi. The power flow hence,

depends on three types of nodes or buses: The load bus, in which the real

and reactive parts are known. Second is the generation or voltage control

bus, in which the voltage magnitude is maintained at a constant

predetermined value. The last bus, the reference voltage angle bus is

known as the slack bus.

0PPPN

1tlt

N

1tgi

N

1tt (3.11)

0QQQN

1tlt

N

1tgi

N

1tt (3.12)

A complexity arises in trying to simultaneously solve the

equations. Since the functions for real power Pi and reactive power Qi are

dependent on non linear functions of the state variables voltage Vi and

phase angle i, iteration methods are employed to solve for both sides of

Equation (3.11) to try to solve for the two remaining constants. Various

methods can be used to speed up the iteration process and make it converge

within a certain error margin (Chattopadhyay et al. 1994). The Newton-

Raphson (N-R) method is one of the fastest iterative methods (Fuerte

Esquivel et al. 2000). This method begins with an initial approximation and

generally converges at a zero of a given system of nonlinear equations

(Chong Han et al. 2008, Blaabjerg et al. 2004).

3.4.1 Switching Angle Calculation using Newton-Raphson

Method

Selection of switching angles can be done either by using the

SHE method or THD minimization method (Lehn and Iravani 1998).

SHE method is preferred when the number of levels is low.

81

THD minimization method is preferred when the number of levels is high,

so that solving of complex transcendental nonlinear equations can be

avoided (Chen and Spooner 2003). In the cascaded converter, the

capacitance requirement is as follows:

Cdc cascade = dc

Lrms

VfI

2(3.13)

The inverter output voltage V av is the sum of three H-bridge

output voltages in one leg, i.e.

3H2H1Hav VVVV (3.14)

The voltage V av can be varied by varying the output of each

FBI level which can be obtained by switching the devices. The harmonic

content of V av can be obtained from the Fourier series analysis as

1h 1hhhoav )thsin(b)thcos(aaV (3.15)

With odd harmonics, a o = o and a n = o

1hhav ...5,3,1hfor)thsin(bV (3.16)

For n level, the Fourier series of the quarter-wave symmetric

parallel connected multi-level waveform is given as

t1k2sin1k2cos)1K2(

V4V12

1ii

1K

dcav

n

(3.17)

82

Fundamental rms voltage

12

1ii

dca

n

cos2V4V (3.18)

Harmonic rms voltage

2/)1N,2,1ifor......3,2,1kfor

]1k2[cos)1k2(2

V4V12

1ii

dc1k2

n

(3.19)

Amplitude modulation index

7

1ii

(max)a

a )cos(71

VVm (3.20)

Va is the amplitude command of the inverter output voltage and

Va(max) is the maximum obtainable amplitude of the phase voltage when all

switching angles i are equal to zero. For releasing SPWM, a higher

frequency triangular wave is compared with the sinusoidal reference wave

of desired frequency (McGrath and Holmes 2000).

The value of individual capacitance Ci required is given as

4/T

)t(ici

ii tdtcosI2V

qC (3.21)

ciVEmI

2(3.22)

83

where qi is the deviation in the charge on the capacitor, ciV is

the average capacitor voltage, i is the switching timing angle of FBI unit.

Using amplitude modulation index m and Va in NR numerical

technique, switching angles are obtained as shown in Table 3.6 (Jiang and

Lipo 2005).

Table 3.6 Switching angles for various modulation indexes

Modulation

index (m)

Switching timing angles (rad)

1 2 3 4 5 6 7

0.45 0.357 0.903 0.804 1.158 1.227 1.424 1.603

0.51 0.445 0.697 0.612 0.902 1.091 1.174 1.208

0.64 0.207 0.558 0.393 0.849 0.807 0.910 1.167

0.78 0.069 0.243 0.206 0.641 0.651 0.818 0.852

0.81 0.107 0.172 0.181 0.273 0.341 0.506 0.828

When m is varied, the inverter either absorbs or generates

reactive power from the power system network. For low m, the inverter

voltage will be greater than the bus voltage and vice versa. For high m, the

modulation angles are less. These values are used for calculating

capacitance values. The total capacitance required for a 3-phase M level

converter is:

C = 3 ci (3.23)

84

3.5 PROPOSED MODULATION STRATEGY

VSC produce harmonics due to switching operation of power

electronic devices (Acha et al. 2001, Singh et al. 1999). The harmonics in

the output voltage of power electronic converters can be reduced using

PWM switching techniques (Mohan et al. 1995). PWM methods reduce the

harmonics by shifting frequency spectrum to the vicinity of high frequency

band of carrier signal (Yuvarajan and Abdollah Khoei 2002). The SPWM

technique, however, inhibits poor performance with regard to maximum

attainable voltage and power (Quek and Yuvarajan 1995). A novel PWM

technique called Inverted-Sine Carrier PWM (ISCPWM) is proposed for

harmonic reduction of the output voltage of ac-dc converters. The proposed

control scheme based on ISCPWM can maximize the output voltage for

each modulation index.

3.5.1 Inverted Sine Carrier PWM Strategy

The ISCPWM method uses a sinusoidal reference signal and an

inverted sine carrier as shown in Figure 3.9 which has better spectral

quality and higher output limit as compared to the conventional SPWM,

without any pulse dropping. The ISCPWM strategy reduces the THD

without losses and also enhances the fundamental output voltage

particularly at lower ma. Although solutions have been already applied

before, this proposed work is focused on adapting and improving this type

of solution to ISCPWM in STATCOM applications.

In this method the control signals have been generated by

comparing sinusoidal reference signal with a high frequency inverted sine

carrier. The carrier frequencies are selected in such a manner that the

number of switching in each band is equal. The proposed modulation

85

technique maximizes the output voltage and gives a low THD. A PI

controller is employed to enhance the performance of the asymmetric MLI

using the proposed modulation strategy.

For the ISCPWM pulse pattern, the switching angles may be

computed in the same way as PWM scheme. The equations of inverted sine

wave are given by Equations (3.24) and (3.25) for its odd and even cycles

respectively.

Figure 3.9 Generation of pulses using ISPWM

y = 1- sin {Mf x - / 2 (i-1)} (3.24)

y = 1- sin {Mf x - / 2 (i-2)} (3.25)

The switching angles for ISCPWM scheme can be obtained

from Equations (3.26) and (3.27)

Ma sinqi+ sin( Mf qi - / 2 (i-1) = 1, i = 1,3,5... (3.26)

Ma sinqi+ sin( Mf qi - / 2 (i-2) = 1, i = 2,4,6... (3.27)

86

ISCPWM technique is classified into two types based upon the

frequency of carrier waves

Unipolar ISCPWM (UISCPWM)- employ carriers of same

frequency

Variable Frequency ISCPWM (VFISCPWM)- employ carriers

of variable frequency

In the gating pulse generation of the proposed ISCPWM scheme

shown in Figure 3.9, the triangular carrier waveform of PWM is replaced

by an inverter sine waveform.

3.5.2 Proposed Variable Frequency ISPWM Technique

The proposed control strategy replaces the conventional fixed

frequency carrier waveform by variable frequency inverted sine wave.

In unipolar (fixed) ISPWM the switching scheme includes three triangular

carrier signals. The signals are time shifted by Ts/3, where Ts is the period

of these carrier signals. The 3 H-Bridges share the same modulating

sinusoidal signal V(t) and -V(t). The harmonics of the output voltage

appear as sidebands centered around the frequency of 2Nfs and its

multiples, provided that the voltage Vdc of each inverter is the same.

The current harmonics caused by DC capacitor voltage ripple is neglected.

The output voltage has very high equivalent switching frequency even if

the switching frequency of the individual switches is not so high.

The ISPWM has a better spectral quality and a higher fundamental voltage

compared to the triangular based PWM. But the main drawback in the

conventional fixed frequency ISCPWM is the marginal boost in the

magnitude of lower order harmonics and unbalanced switch utilization.

87

This is overcome by employing variable frequency inverted sine carrier

signals. The VFISPWM scheme is more favorable than the conventional

ISPWM technique for use in asymmetric multilevel inverter.

Based on the discussions in the previous sections, there are

several well known SPWM strategies for CMCs. Compared to the

conventional triangular carrier based PWM, the Inverted Sine Carrier

PWM (ISCPWM) has a better spectral quality and a higher fundamental

output voltage without any pulse drop. In the fixed frequency carrier based

PWM the switch utilization in multilevel inverters gets affected and results

in unbalanced switch utilization. In order to balance the switching duty

among the various levels in inverters, a variable frequency carrier based

PWM called as VFISPWM has been suggested. This novel method

combines the advantage of inverted sine and multi frequency carrier

signals. The VFISPWM provides an enhanced fundamental voltage, lower

THD and minimizes the switch utilization among the various levels in

inverters.

3.6 IMPLEMENTATION OF ASYMMETRIC MULTILEVEL

INVERTER

A detailed study of the technique used, as shown in Figure 3.10

is carried out for THD measurement. In order to verify the operation

behavior and examine the harmonic content of the ACMC applying

PD SPWM, the circuit is simulated using Matlab / Simulink for different

modulation factors and normalized carrier values. Furthermore, a PI

controller is used to control the MLI using the proposed PWM technique.

PD based unipolar ISPWM strategy is employed for pulse generation.

In the conventional PWM method, triangular wave is used as a carrier but

they are replaced by inverted sine carrier waves modulation strategy.

88

Figure 3.10 Asymmetric cascaded 7- level inverter

The first H-Bridge H1 in Figure 3.10 consists of a separate DC

source Vdc1, and the second H-Bridge H2 consists of a DC source Vdc2.

The output of H-Bridge-1 is v1 (t) and the output of H-Bridge-2 is v2 (t).

Hence the total output voltage is given by v(t) = v1(t) + v2(t). By alternately

opening and closing the switches S1,S4 and S2,S3 of H-Bridge-1

appropriately, output of H1 v1(t) can be made equal to +Vdc, 0 or -Vdc.

Similarly the output voltage of H-Bridge-2 v2(t) can be made equal to

-Vdc/2, 0 or +Vdc/2 by opening and closing the switches of H2. Hence v(t)

takes values -3/2Vdc, -Vdc, -1/2Vdc, 0, +1/2Vdc, +Vdc, +3/2Vdc.

An inverted sine wave of high switching frequency is taken as a

carrier wave and is compared with that of the reference sine wave.

The pulses are generated whenever the amplitude of the reference sine

wave is greater than that of the inverted sine carrier wave. The output

voltage waveform comprising of 7-levels is obtained by modulating the

inverted sine carriers. By employing this new modulation technique the

fundamental voltage can be improved throughout the working range.

For switching of these topologies, various modulation strategies have been

89

already reported in section 3.3. Among them the carrier-based PWM

method uses several triangular carrier signals, keeping only one modulating

sinusoidal signal.

Table 3.7 shows the switching sequence for a 7-level ACMC

shown in Figure 3.10. The carriers will have the same frequency and the

same peak to peak amplitude and are disposed so that the bands they

occupy are contiguous. The zero reference is placed in the middle of the

carrier set. The modulating signal is a sinusoid of frequency 50 Hz.

Table 3.7 Switching sequence for 7-level ACMC

During

Positive

Half Cycle

Switches in

Conduction

Reverse diode in

conduction

S1, S4, S8 S7S4, S5, S8 S3

S1, S4, S5, S8 -

S4, S5, S8 S3S1, S4, S8 S7

During

Negative

Half Cycle

S2, S3, S7 S8S3, S6, S7 S4

S2, S3, S6, S7 -

S3, S6, S7 S4S2, S3, S7 S8

At every instant each carrier is compared with the modulating

signal. Each comparison gives the value one if the modulating signal is

greater than the triangular carrier, zero otherwise. The results are added to

90

give the voltage level, which is required at the output terminal of the

inverter.

3.6.1 Performance Evaluation of CMC Employing Conventional

PWM

In CMC employing conventional PWM technique as shown in

Figure 3.11, triangular carrier waves are modulated with reference sine

wave for pulse generation (Jochim 1992). The pulses are generated

whenever the amplitude of the reference sine wave is greater than that of

the triangular carrier wave. Simulation circuit for the generation of

triangular wave is shown in Figure 3.12. The carrier and reference sine

waveforms for conventional PWM technique are shown in Figures 3.13

and 3.14 respectively. The generated carrier waves of frequency 4000 Hz

are modulated with reference sine wave of frequency 50 Hz for pulse

generation.

Figure 3.11 Simulation circuit of conventional cascaded MLI

91

Figure 3.12 Simulation circuit for the generation of triangular wave

Figure 3.13 Triangular carrier waves

0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.01-150

-100

-50

0

50

100

150

200

Time(seconds)

Figure 3.14 Triangular carrier and reference sine waveforms

for conventional PWM

92

0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02-300

-200

-100

0

100

200

300

Time(sec)

Figure 3.15 Output voltage of CMC (Conventional PWM)

Figure 3.16 FFT window for output voltage (Conventional PWM)

The obtained pulses are then applied to conventional 7-level

CMC and the obtained output voltage waveform of value 265.6 V is shown

in Figure 3.15. With the optimum frequency of 4000 Hz, in conventional

PWM method the obtained THD value is 30.99% as shown in Figure 3.16.

3.6.2 Performance Evaluation of CMC Employing Unipolar

ISCPWM

The proposed unipolar control strategy replaces the triangular

based carrier waveform by inverted sine wave. The application of unipolar

93

PWM to inverted sine carrier results in the reduction of carrier frequencies

or its multiples. So, the advantage of inverted sine and unipolar PWM are

combined to improve the performance of the CMC. The ISCPWM method

uses the sine wave as a reference signal while the carrier signal is an

inverted high frequency sine carrier that helps to maximize the output

voltage for a given modulation index.

Figure 3.17 Simulation circuit for the generation of unipolar inverted

sine carrier waves

Figure 3.18 Waves employed for generating inverted sine waves

Time (secs)

94

Figure 3.17 shows the simulation circuit for the generation of

inverter sinewaves. Figure 3.18 and Figure 3.19 shows the waves

employed for the generation of unipolar (fixed) ISCPWM signals. Inverted

sine waves of frequency 4000 Hz is generated using the simulation circuit

shown in Figure 3.17. This circuit involves the generation of six inverted

sine waves (Figure 3.20) each of amplitude 50 V among which three

inverted sine waves are compared with positive half of reference sine wave

of amplitude 150 V for pulse generation.

Figure 3.19 Unipolar inverted sine carrier waves

Figure 3.20 Inverted sine carrier waves (7-level)

Time (secs)

95

Figure 3.21 Reference and inverted sine waveforms

for unipolar ISPWM

0 0 .0 02 0.0 04 0.0 06 0.0 08 0 .01 0.012 0 .014 0 .016 0 .018 0.02-30 0

-20 0

-10 0

0

100

200

300

Time(sec)

Figure 3.22 Output voltage of conventional 7-level CMC

employing unipolar ISCPWM

Figure 3.21 shows the inverted sine carrier waveforms along

with the reference sine waveform for unipolar ISPWM.

Time (secs)

96

Figure 3.23 FT window for output voltage (Unipolar ISPWM)

With the proposed Unipolar ISCPWM technique, the obtained

fundamental component and THD values are shown in Figure 3.22 and

Figure 3.23 respectively. Table 3.8 gives a comparision of voltage output

levels and THD values of both conventional and unipolar ISCPWM

inverters.

Table 3.8 Comparison of unipolar ISCPWM with conventional

PWM

PWM Technique

Fundamental Output Voltage

(in volts)

Total Harmonic Distortion

(%)Conventional PWM 266.6 30.97

Unipolar ISPWM 278 21.82

On implementing Unipolar ISPWM technique for conventional

CMC, THD is reduced considerably by a factor of around 9%.

Hence Unipolar ISCPWM technique is extended for the proposed ACMC,

in order to overcome the disadvantages of conventional CMC.

The generated pulses are then applied to asymmetric cascaded MLI.

97

Output voltage waveform of single phase and 3 phase 7-level ACMC

employing Unipolar ISCPWM technique is shown in Figure 3.24 and

Figure 3.25 respectively.

Figure 3.24 Output voltage waveform of single phase 7-level ACMC

Figure 3.25 Output voltage waveform of three phase 7-level ACMC

(Unipolar ISCPWM)

Vol

tage

ampl

itude

Vol

tage

ampl

itude

Time (secs)

Time (secs)

98

3.6.3 Performance Evaluation of CMC Employing VFISCPWM

The proposed control strategy replaces the conventional fixed

frequency carrier waveform by variable frequency inverted sine wave.

Simulation circuit for Variable Frequency Inverted Sine Carrier (VFISC)

generation is shown in Figure 3.26. Pulses for the asymmetric cascaded

MLI are generated by modulating carrier waves with reference to sine

wave of frequency 50 Hz. The obtained pulses from VFISPWM strategy

are then applied to the ACMC. The proposed PWM strategy is also

extended for a three phase asymmetric cascaded MLI by introducing a

phase displacement of 120 between each phase.

Figure 3.26 Simulation circuit for the generation of variable

frequency inverted sine carrier waves

99

Figure 3.27 Carrier and inverted sine waveforms

for VFISCPWM technique

Figure 3.28 Variable frequency inverted sine carrier waves

The variable frequency inverted sine carrier waves shown in

Figure 3.28 is compared with sine waveforms as shown in Figure 3.27.

Time (secs)

Time (secs)

100

Figure 3.29 Output voltage waveform of single phase 7-level ACMC

employing VFISCPWM

Figure 3.30 Output voltage waveform of three phase 7-level ACMC

employing VFISCPWM

Output voltage waveforms of single phase and three phase

7-level ACMC employing VFISCPWM technique are shown in

Figure 3.29 and Figure 3.30 respectively.

Time (secs)

Time (secs)

Vol

tage

ampl

itude

Vol

tage

ampl

itude

Vol

tage

ampl

itude

101

Figure 3.31 Output voltages waveform of three phase 7-level ACMC

Figure 3.32 FFT window for output voltage (Unipolar ISPWM)

Time (secs)

Vol

tage

ampl

itude

102

The three individual single phase output voltage waveforms of a

three phase 7-level ACMC is shown in Figure 3.31. On implementing

VFISPWM technique for asymmetric cascaded MLI, THD is reduced by a

factor of around 2% as shown in Figure 3.33 when compared to unipolar

ISCPWM strategy as shown in Figure 3.32. The VFISPWM provides an

enhanced fundamental voltage, THD and minimizes the switch utilization

among the various levels in inverters. In this method the control signals

have been generated by comparing sinusoidal reference signal with a high

frequency inverted sine carrier. The carrier frequencies are selected in such

a manner that the number of switching in each band is equal.

Figure 3.33 FFT Window for output voltage (VFISPWM)

The proposed modulation technique for the proposed inverter

topology maximizes the output voltage and gives a low THD of 5.80%.

The FFT window for the output voltage waveform of ACMC employing

fixed frequency ISCPWM is shown in Figure 3.32 and that of ACMC

employing VFISPWM is shown in Figure 3.33.

103

Table 3.9 gives the comparison of THD values obtained for

unipolar ISPWM and VFISPWM control strategies.

Table 3.9 Comparison of THD values - VFISPWM

with unipolar ISPWM technique

PWM

Technique

Total Harmonic

Distortion

(%)

Unipolar ISPWM 7.01

Variable freqency ISPWM 5.80

Some inferences made from the above waveforms are

VFISCPWM technique provides better spectral quality and

reduced THD when compared to Unipolar ISCPWM technique

ISPWM technique provides better spectral quality and a higher

fundamental component when compared to conventional PWM

technique

Harmonics of carrier frequencies and its multiples are not

produced in ISPWM technique

With ISPWM technique the THD is also reduced compared to

conventional PWM technique

The THD decreases with increase in switching frequency and

the fundamental component of voltage increases with increase in switching

104

frequency and is higher for inverted sine carrier when compared to the

conventional triangular carrier.

3.7 NEURAL NETWORK CONTROL OF ACMC

The SPWM technique, however, exhibits poor performance with

regard to maximum attainable voltage and power. The fundamental

amplitude in the SPWM output waveform is smaller than the rectangular

waveform. Among various PWM control techniques the most popular one

is the Multi Carrier PWM (MCPWM) which shifts the harmonics to high

frequencies by using high frequency carriers. But electronic devices have

limited switching frequencies. Hence high switching carriers are limited by

the power electronic devices having limited switching frequencies.

Harmonic Elimination Method (HEM) can be applied for ACMCs to

eliminate harmonics with the use of low switching frequency devices

(Kumar et al. 2008). However this method requires complex calculations of

switching angles.

To overcome this constraint, a HEM based on Artificial Neural

Network (ANN) is proposed to control the ACMC. The proposed work is

based on Multi-Layer Perceptron (MLP) method. The performance is

evaluated with a 7-level ACMC ANN controller.

A multiport system in ANN as shown in Figure 3.34 consists of

a triggering system which consists of eight switches S1-S8. The outputs of

these switches rely upon the output of the neural network connected to it.

The output of this multiport system is given to the H-bridge inverter.

The sum of the voltages of the two driver circuits gives the output voltage

at the scope.

105

Figure 3.34 Multiport system

Figure 3.35 ACMC simulation circuit using ANN controller

Figure 3.35 shows the ACMC simulation circuit of a 7-level

ACMC using ANN controller based on Matlab / Simulink.

106

Figure 3.36 ACMC simulation circuit using conventional

SPWM controller

Figure 3.37 Output voltage of the 7-level ACMC

using ANN controller

Figure 3.36 shows the ACMC simulation circuit using

conventional SPWM controller based on Matlab / Simulink. The output

voltage of ACMC is shown in Figure 3.37 using the simulation circuit

shown in Figure 3.35.

107

Table 3.10 gives the switching sequence of a 7-level ACMC

with ANN.

Table 3.10 Switching sequence

INPUT

VOLTAGE

SWITCHING

LEVELSS1 S2 S3 S4 S5 S6 S7 S8

0 1 0 0 0 0 0 0 0 0

12 2 1 0 0 1 0 1 0 1

24 3 0 0 0 0 1 0 0 1

36 4 1 0 0 1 1 0 0 1

24 5 0 0 0 0 1 0 0 1

12 6 1 0 0 1 0 1 0 1

0 7 0 0 0 0 0 0 0 0

-12 8 0 1 1 0 0 0 1 1

-24 9 0 0 0 0 0 1 1 0

-36 10 0 1 1 0 0 1 1 0

-24 11 0 0 0 0 0 1 1 0

-12 12 0 1 1 0 0 0 1 1

The H-Bridge enables the voltage to be applied across a load in

either direction. The switching table shows the instances at which the

switches S1-S8 are triggered when various voltages are applied. Such a

continuous switching by giving high (1) and low (0) input signals gives rise

to a multilevel output.

Table 3.11 displays the comparison of THD values obtained for

HEM and SPWM control techniques.

108

Table 3.11 Comparison of HEM with conventional SPWM

Modulation strategy THD (%)

Conventional SPWM 18.43

Neural implementation of HEM 9.11

3.8 FPGA BASED HARDWARE IMPLEMENTATION

In the proposed system, Field Programmable Gate Array

(FPGA) based gate signal generation is used. Complex control algorithms

required by MLIs can be implemented in FPGA but not in real time using

standard low cost microcontrollers or DSP. FPGA allows simultaneous

execution of all control procedures, enabling high performance in repetitive

and massive computation, high computation speed and dynamic response.

However microcontrollers and DSP controllers cannot satisfy the demand.

Figure 3.38 Block diagram of Spartan 3E-Xilinx (Xc3s500-Fg320)

109

Figure 3.39 FPGA kit programmed with Xilinx ISE tool

Figure 3.40 FPGA kit (Spartan 3E-[Xc3s500-Fg320])

and two stage cascaded inverter

The proposed modulator has been implemented in FPGA-Xilinx

Spartan 3E (Figure 3.38) and tested with the prototype inverter.

The experimental verification of multilevel modulation and control is

110

obtained through the laboratory model of a single phase, 5-level inverter

based STATCOM. A FPGA based digital processor is used for the

modulation of a multilevel inverter.

The proposed work presents the design, implementation and test

of a novel real-time controller for a 5-level multilevel converter based on a

FPGA. The main advantages of FPGAs are that they provide higher

performances in repetitive and massive computations. Multilevel

converters, moreover, often require complex control algorithms which

cannot be implemented in real-time using standard low cost

microcontrollers or DSP, but can be successfully implemented using

hardware description languages and FPGA. FPGA includes on-chip PWM

controllers making implementation easy. Hence the real time

implementation of the proposed inverter using FPGA is carried out in the

proposed work. The hardware implementation of a two stage CMC

(Figure 3.40) in FPGA kit programmed with Xilinx ISE tool is shown in

Figure 3.39.

Xilinx Spartan 3E FPGA IC is used for controlling the width of

the pulses from PWM generator, by fixing either the frequency or the

voltage so that the MOSFETs are turned ON and OFF in the desired

sequence.

Ability to re-program in the field to fix bugs

Small size and increased speed

Offer easy, fast and flexible design and implementation

111

The inherent parallelism of the logic resources on an FPGA

allows for considerable computational output even at a low

MHz clock rates

3.8.1 Generation of gating pulses for the proposed PWM

The gating signals for the 5-level inverter employing the

ISPWM technique is generated using FPGA processor as shown in

Figure 3.41 and tested with the proto-type inverter. Figure 3.42 shows the

VLSI Simulation: Model SIM PWM Pulses. The performance evaluation

of an ISPWM multilevel inverter is done using Matlab/Simulink

environment and minimized THD is determined.

Figure 3.41 Generation of PWM pulses from FPGA

112

Figure 3.42 VLSI simulation : model SIM PWM pulses

The Spartan 3E (Xc3s500-Fg320) is programmed through

Xilinx ISE tool via PC through IMPACT port. With this programme, the

inverter is switched ON and then the waveforms are obtained as shown in

Figure 3.43.

Figure 3.43 5-level output voltage waveform for ISCPWM inverter

113

As per the program in the Spartan 3E-(Xc3s500-Fg320), it

creates the gate signals for the MOSFETs used in the two stage cascaded

inverter. If the gate pulses are given, the respective output is obtained as

shown in the Figure 3.43.

After verifying the design by simulation, synthesis is carried

out. Finally placement, routing and timing optimizations are performed.

The additional advantage in the ISCPWM is that it does not require any

mode changing as required in conventional PWM. Regrettably, the

ISCPWM causes marginal increase in the lower order harmonics, but

except third harmonics all other harmonics are at an acceptable level. It is

worth noting that for three-phase applications, the heightened third

harmonics need not be bothered.

Figure 3.44 Generated pulses using ISPWM technique in CRO

114

Figure 3.45 Cascaded 7-level inverter output waveform in CRO

The hardware implementation of ISCPWM technique for a

7-level CMC done using microcontrollers and the waveforms of the

generated pulses and voltage output measured using a CRO are shown in

Figures 3.44 and 3.55 respectively.

3.9 CONCLUSION

For transmission and distribution voltage levels, the multilevel

VSC offers various advantages over its counterparts. Among the various

multilevel converter topologies, the CMC is the most promising alternative

for the STATCOM application. Analytical, simulated and experimental

results show the superiority of the proposed system. Using MLI, the

switching frequency increases while the ripple magnitude reduces.

The proposed modulation and control scheme is validated through the

experimental results that are obtained using the prototype model of a single

phase, 5-level inverter. To achieve the same number of output voltage

levels, the CMC requires the least total number of components. With its

115

modular structure, the CMC can flexibly expand the output power

capability that corresponds to the requirements of the connected power

system networks. Additionally, its modularity is favorable to

manufacturing. Moreover, redundancy can be easily applied in the CMC to

enhance reliability for the entire system. This chapter mainly focused on

the ISPWM technique for CMC. Based on the proposed CMC model, the

ISPWM technique was first presented for the 5-level and then for the

7-level CMC and its performance and stability were verified by both

computer simulations and experiments. The experimental results are very

consistent with the simulation results. Moreover, the results demonstrate

the accuracy of the model and the superior performance of the ISPWM

control technique.