cascaded h- bridge multilevel inverter modulation ... · by conventional multilevel inverters, (ii)...

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International Journal of Electrical Engineering & Technology (IJEET)

Volume 6, Issue 8, September – October 2015, pp. 108-126, Article ID: IJEET_06_08_011

Available online at http://www.iaeme.com/IJEET/issues.asp?JType=IJEET&VType=6&IType=08

ISSN Print: 0976-6545 and ISSN Online: 0976-6553

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CASCADED H- BRIDGE MULTILEVEL

INVERTER MODULATION TOPOLOGIES AND

ITS SIMULATION

A.S. Mane

Ph.D. Student, Department of EE,

Sant Gadge Baba Amravati University, Amravati, India

Dr. V. S. Bandal

Associate Professor, Department of EE,

Government College of Engineering Pune, India

ABSTRACT

This paper aims to extend the knowledge about the performance of different

cascaded multilevel inverter induction motor drives through harmonic analysis. Large

electric drives and utility applications require advanced power electronics converter

to meet the high power demands. As a result, multilevel power converter structure has

been introduced as an alternative in high power and medium voltage situations. A

multilevel converter not only achieves high power ratings, but also improves the

performance of the whole system in terms of harmonics, dv/dt stresses, and stresses in

the bearings of a motor. Several multilevel converter topologies have been developed;

i) diode clamped, ii) flying capacitors, and iii) cascaded or H-bridge. Referring to the

literature reviews, the cascaded multilevel inverter (CMLI) with separated DC

sources is clearly the most feasible topology for use as a power converter for medium

& high power applications due to their modularization and extensibility. The H-bridge

inverter eliminates the excessively large number of (i) bulky transformers required

by conventional multilevel inverters, (ii) clamping diodes required by multilevel

diode-clamped inverters, , and (iii) flying capacitors required by multilevel flying-

capacitor inverter. As a preliminary study the thesis examined and compared the most

common multilevel topologies found in the published literature. Starting from the

essential requirements, the different approaches to the construction of multilevel

inverter are explained and compared. In particular, aspects of total harmonic

distortion (THD) and modulation which are required or desirable for multilevel

converters are discussed. Sine-triangle carrier modulation is identified as the most

promising technique to pursue for both technical and pedagogical reasons. Since

cascaded multilevel inverter is considered to be suitable for medium & high power

applications, the thesis examined & compared the harmonic analysis of 5-level

cascaded multilevel inverter induction motor drives through analysis, simulation &

experiment. In order to balance the DC capacitor voltages, sine triangle pulse width

modulation (SPWM) technique, which is suitable for any number of H-bridge

converters, is applied.

Cascaded H- Bridge Multilevel Inverter Modulation Topologies and Its Simulation


Keywords: Multilevel Inverter, Diode Clamped, Cascaded H-Bridge Multi level

Inverter, Flying Capacitor Multi level Inverter, H-bridge ,Total Harmonic Distortion

(THD), SPWM

Cite this Article: A.S. Mane and Dr. V.S. Bandal, Cascaded H- Bridge Multilevel

Inverter Modulation Topologies and Its Simulation, International Journal of Electrical

Engineering & Technology, 6(8), 2015, pp. 108-126.

http://www.iaeme.com/IJEET/issues.asp?JType=IJEET&VType=6&IType=8

1. INTRODUCTION

Power electronic converters, especially dc/ac PWM inverters have been extending their range

of use in industry because they provide reduced energy consumption, better system efficiency,

improved quality of product, good maintenance, and so on. For a medium voltage grid, it is

troublesome to connect only one power semiconductor switches directly [1, 2, 3]. As a result,

a multilevel power converter structure has been introduced as an alternative in high power and

medium voltage situations such as laminators, mills, conveyors, pumps, fans, blowers,

compressors, and so on. As a cost effective solution, multilevel converter not only achieves

high power ratings, but also enables the use of low power application in renewable energy

sources such as photovoltaic, wind, and fuel cells which can be easily interfaced to a

multilevel converter system for a high power application. The most common initial

application of multilevel converters has been in traction, both in locomotives and track-side

static converters [4]. More recent applications have been for power system converters for

VAR compensation and stability enhancement [5], active filtering [6], high-voltage motor

drive [3], high-voltage dc transmission [7], and most recently for medium voltage induction

motor variable speed drives [8]. Many multilevel converter applications focus on industrial

medium-voltage motor drives [3, 9], utility interface for renewable energy systems [10],

flexible AC transmission system (FACTS) [11], and traction drive systems [12]. The inverters

in such application areas as stated above should be able to handle high voltage and large

power. For this reason, two-level high-voltage and large-power inverters have been designed

with series connection of switching power devices such as gate-turn-off thyristors (GTOs),

integrated gate commutated transistors (IGCTs), and integrated gate bipolar transistors

(IGBTs), because the series connection allows reaching much higher voltages. However, the

series connection of switching power devices has big problems [13], namely, non-equal

distribution of applied device voltage across series-connected devices that may make the

applied voltage of individual devices much higher than blocking voltage of the devices during

transient and steady-state switching operation of devices. As alternatives to effectively solve

the above-mentioned problems, several circuit topologies of multilevel inverter and converter

have been researched and utilized. The output voltage of the multilevel inverter has many

levels synthesized from several DC voltage sources. The quality of the output voltage is

improved as the number of voltage levels increases, so the quantity of output filters can be

decreased. The concept of multilevel converters has been introduced since 1975. The cascade

Multilevel inverter was first proposed in 1975 [14]. Separate DC-sourced full-bridge cells

are placed in series to synthesize a staircase AC output voltage. The term multilevel began

with the three-level converter [15]. Subsequently, several multilevel converter topologies

have been developed [16]. In 1981, diode-clamped multilevel inverter also called the Neutral-

Point Clamped (NPC) inverter schemes were proposed [17]. In 1992, capacitor-clamped (or

flying capacitor) multilevel inverters, [18] and in 1996, cascaded multilevel inverters were

proposed [1], [19]. Although the cascade multilevel inverter was invented earlier, its

application did not prevail until the mid-1990s. The advantages of cascade multilevel

inverters were prominent for motor drives and utility applications. The cascade inverter has

A.S. Mane and Dr. V.S. Bandal


drawn great interest due to the great demand of medium-voltage high-power inverters. The

cascade inverter is also used in regenerative-type motor drive applications [20, 21]. Recently,

some new topologies of multilevel inverters have emerged. This includes generalized

multilevel inverters [22], mixed multilevel inverter [23], hybrid multilevel inverters [24, 25]

and soft-switched multilevel inverters [26]. These multilevel inverters can extend rated

inverter voltage and power by increasing the number of voltage levels. They can also increase

equivalent switching frequency without the increase of actual switching frequency, thus

reducing ripple component of inverter output voltage and electromagnetic interference effects.

A multilevel converter can be implemented in many different ways. The simplest techniques

involve the parallel or series connection of conventional converters to form the multilevel

waveforms [27]. More complex structures effectively insert converters within converters [28].

The voltage or current rating of the multilevel converter becomes a multiple of the individual

switches, and so the power rating of the converter can exceed the limit imposed by the

individual switching devices.

The elementary concept of a multilevel converter to achieve higher power is to use a

series of power semiconductor switches with several lower voltage dc sources to perform the

power conversion by synthesizing a staircase voltage waveform. Capacitors, batteries, and

renewable energy voltage sources can be used as the multiple dc voltage sources. The

commutation of the power switches aggregate these multiple dc sources in order to achieve

high voltage at the output; however, the rated voltage of the power semiconductor switches

depends only upon the rating of the dc voltage sources to which they are connected. A

multilevel converter has several advantages over a conventional two-level converter that uses

high switching frequency pulse width modulation (PWM).

The attractive features of a multilevel converter can be briefly summarized as follows.

1. Staircase waveform quality: Multilevel converters not only can generate the output voltages

with very low distortion, but also can reduce the dv/dt stresses; therefore electromagnetic

compatibility (EMC) problems can be reduced.

2. Common-mode (CM) voltage: Multilevel converters produce smaller CM voltage;

therefore, the stress in the bearings of a motor connected to a multilevel motor drive can be

reduced. Furthermore, CM voltage can be eliminated by using advanced modulation strategies

such as that proposed in [29].

3. Input current: Multilevel converters can draw input current with low distortion.

4. Switching frequency: Multilevel converters can operate at both fundamental switching

frequency and high switching frequency PWM. It should be noted that lower switching

frequency usually means lower switching loss and higher efficiency.

Multilevel converters do have some disadvantages. One particular disadvantage is the

greater number of power semiconductor switches needed. Although lower voltage rated

switches can be utilized in a multilevel converter, each switch requires a related gate drive

circuit. This may cause the overall system to be more expensive and complex. Abundant

modulation techniques and control paradigms have been developed for multilevel converters

such as sinusoidal pulse width modulation (SPWM), selective harmonic elimination (SHE-

PWM), space vector modulation (SVM), and others. In this thesis sinusoidal pulse width

modulation (SPWM) is used.



2. SINGLE PHASE FIVE LEVEL CASCADED MULTILEVEL

INVERTER: (CMLI) [30], [31], [32]

The concept of this inverter is based on connecting H-bridge inverters in series to get a

sinusoidal voltage output. The output voltage is the sum of the voltages that are generated by

each cell. The number of output voltage levels are (2n+1), where n is the number of cells. The

switching angles can be chosen in such a way that total harmonics distortion is minimized.

One of the advantage of this type of multilevel inverter is that it needs less number of

components in comparison to the Diode clamped or the flying capacitor, which results in

reduction of weight as well as cost.

A. Operation of Cascaded H-bridge multilevel inverter

The converter topology is based on the series connection of single-phase inverters with

separate dc sources. Fig.2 shows the power circuit for one phase leg of five level cascaded

inverter. The resulting phase voltage is synthesized by the addition of the voltages generated

by the different cells. In a 3-level cascaded inverter each single-phase full-bridge inverter

generates three voltages at the output: +Vdc, 0, -Vdc (zero, positive dc voltage, and negative

dc voltage). This is made possible by connecting the capacitors sequentially to the ac side via

the power switches. The resulting output ac voltage swings from -Vdc to +Vdc with three

levels, -2Vdc to +2Vdc with five-level. The staircase wave form is nearly sinusoidal, even

without filtering. Fig.1shows single phase five-level cascaded multilevel inverter.

Fig.1. Circuit Diagram of single phase five level Cascaded H-Bridge Multilevel Inverter.

For an output voltage level Vo = Vdc, S11, S41 and S12, S42 are turned ON

For an output voltage level Vo = Vdc/2, S11, S41 are turned ON

For an output voltage level Vo = 0, all switches are turn OFF

For an output voltage level Vo = -Vdc, S21, S31 and S22, S32 are turned ON

For an output voltage level Vo = -Vdc/2, S21, S31are turned OFF.



Table-1 Switching State of the Five-Level Cascaded H-Bridge Multilevel Inverter.

Voltage

Vo

Switching sequence

S11 S21 S31 S41 S12 S22 S32 S42

Vao 1 0 0 1 1 0 0 1

Vdc 0 0 1 0 0 0 0 0

Vdc/2 0 0 0 0 0 0 0 0

o 0 0 0 0 0 0 0 0

-Vdc 0 1 1 0 0 0 0 0

-Vdc/2 0 1 1 0 0 1 1 0

Note- 1- means ON State, 0 - means OFF State

Cascaded H-Bridge (CHB) configuration has recently become very popular in high power

AC supplies and adjustable-speed drive applications. A cascade multilevel inverter consists of

a series of H-bridge (single-phase full bridge) inverter units in each of its three phases. Each

H-bridge unit has its own dc source, which for an induction motor would be a battery unit,

fuel cell or solar cell. Each SDC (separate D.C. source) is associated with a single phase full-

bridge inverter. The ac terminal voltages of different level inverters are connected in series.

Through different combinations of the four switches, S1-S4, each converter level can generate

three different voltage outputs, +Vdc, -Vdc and zero. The AC outputs of different full bridge

converters in the same phase are connected in series such that the synthesized voltage

waveform is the sum of the individual converter outputs. Note that the number of output-

phase voltage levels is defined in a different way from those of the two converters (i.e. diode

Clamped and flying capacitor). In this topology, the number of output-phase voltage levels is

defined by m=2N+1, where N is the number of DC sources. A seven-level cascaded

converter, for example, consists of three DC sources and three full bridge converters.

Minimum harmonic distortion can be obtained by controlling the conducting angles at

different converter levels. Each H- bridge unit generates a quasi-square waveform by phase

shifting its positive and negative phase legs‟ switching timings. Each switching device always

conducts for 180° (or half cycle) regardless of the pulse width of the quasi-square wave. This

switching method makes all of the switching devices current stress equal. In the motoring

mode, power flows from the batteries through the cascade inverters to the motor. In the

charging mode, the cascade converters act as rectifiers, and power flows from the charger (ac

source) to the batteries. The cascade converters can also act as rectifiers to help recover the

kinetic energy of the vehicle if regenerative braking is used. The cascade inverter can also be

used in parallel HEV configurations. This new converter can avoid extra clamping diodes or

voltage balancing capacitors. The combination of the 180° conducting method and the

pattern-swapping scheme make the cascade inverters voltage and current stresses the same

and battery voltage balanced. Identical H-bridge inverter units can be utilized, thus improving

modularity and manufacturability and greatly reducing production costs. Battery-fed cascade

inverter prototype driving an induction motor at 50% and 80% rated speed both the voltage

and current are almost sinusoidal. Electromagnetic interference (EMI) and common mode

voltage are also much less than what would result from a PWM inverter because of the

inherently low dv/dt and sinusoidal voltage output.

Cascade inverters are ideal for an induction motor that has many separate dc sources

(batteries) available for the individual H-bridges, these inverters are not an option for series

hybrid induction motors because cascade inverters cannot be easily connected back-to-back.

For series-configured induction motors where an onboard combustion engine generates ac

power via an alternator or generator, a multilevel back-to-back diode clamped converter drive



can best interface with the source of ac power and yet still easily meet the high power and/or

high voltage requirements of the induction motor.[33], [34]

Induction motors generally have an ac voltage source from an alternator or combustion-

engine generator. A rectifier converts this ac voltage to dc for the electric energy storage

devices on board – batteries or ultra-capacitors. An inverter converts the dc voltage to variable

voltage variable frequency ac in order to drive the main induction motor.

The multilevel converter can act as an inverter in drive mode when energy is being sent to

the motor that drives the wheels and as a rectifier during regenerative braking or during

charge mode when the vehicle is plugged into an external ac source.

The reduction in dv/dt can prevent motor windings and bearings from failure. The

staircase output voltage waveform approaches a sine wave, thus having no common-mode

voltage and no voltage surge to the motor windings.

A cascaded multilevel inverter is discussed to eliminate the excessively large number of

(1) Bulky transformers required by conventional multi pulse inverters,

(2) Clamping diodes required by multilevel diode-clamped inverters, and

(3) Flying capacitors required by multilevel flying-capacitor inverters. [35], [37]

3. MODULATION TOPOLOGIES OF MULTI LEVEL INVERTERS

The multilevel topology involves several modulation techniques. Each technique involves

different modulation methods. The well-known modulation topologies for multilevel inverters

as follows:

Sinusoidal or “Sub harmonic” Natural Pulse Width Modulation (SPWM).

Selective Harmonic Eliminated Pulse Width Modulation (SHE PWM) or

Programmed-Waveform Pulse Width Modulation (PWPWM).

Optimized Harmonic Stepped-Waveform Technique (OHSW).

The advent of the transformer less multilevel inverter topology has brought for various

pulse width modulation (PWM) schemes as a means to control the switching of the active

devices in each of the multiple voltage levels in the inverter. The most efficient method of

controlling the output voltage is to incorporate pulse width modulation control (PWM control)

within the inverters. In this method, a fixed d.c. input voltage is supplied to the inverter and a

controlled A.C. output voltage is obtained by adjusting the on and–off periods of the inverter

devices. Voltage-type PWM inverters have been applied widely to such fields as power

supplies and motor drivers. This is because such inverters are well adapted to high-speed self-

turn-off switching devices that, as solid-state power converters, are provided with recently

developed advanced circuits; and they are operated stably and can be controlled well.

Fig. 2: Multilevel Modulation Techniques



From the above all mentioned PWM control methods, the Sinusoidal pulse width

modulation (SPWM) is applied in the proposed inverter since it has various advantages over

other techniques. Sinusoidal PWM inverters provide an easy way to control amplitude,

frequency and harmonics contents of the output voltage. Sinusoidal pulse width modulation

(SPWM) is one of the primitive techniques, which are used to suppress harmonics presented

in the quasi-square wave. In the modulation techniques, there are two important defined

parameters:

1) The ratio P = fc/fm known as frequency ratio, and

2) The ratio Ma = Am/Ac known as modulation index, where fc is the reference frequency,

fm is the carrier frequency, Am is reference signal amplitude and Ac is carrier signal

amplitude.

For NPC multilevel inverters, most carrier based modulation strategies derive from

disposition techniques developed by Carrara et al, where for an M level inverter, M-1 carriers

of identical frequency and amplitude are arranged to occupy contiguous bands between +Vdc

and -Vdc. These carriers can be arranged in:

Alternative Phase Opposition Disposition (APOD), where each carrier is phase shifted by 1800

from its adjacent carriers.

Phase Opposition Disposition (POD) where the carriers above the reference zero point is out

of phase with those below the zero point by 1800 .

Phase Disposition (PD) where all carriers are in phase.

In Phase Disposition (IPD)

In this paper I have discuss using In Phase Disposition (IPD). the present work, in the

carrier-based implementation the phase disposition PWM scheme is used. Figure 3

demonstrates the sine-triangle method for a three-level inverter. Therein, the a-phase

modulation signal is compared with two (n-1 in general) triangle waveforms. The rules for the

in phase disposition method, when the number of level N = 3, are

The N –1 = 3-1=2 carrier waveforms are arranged so that every carrier is in phase.

The converter is switched to +Vdc/ 2 when the reference is greater than both carrier

waveforms.

The converter is switched to zero when the reference is greater than the lower carrier

waveform but less than the upper carrier waveform.

The converter is switched to - Vdc/ 2 when the reference is less than both carrier

waveforms.

In the carrier-based implementation, at every instant of time the modulation signals are

compared with the carrier and depending on which is greater, the switching pulses are

generated. As seen from Figure 3.4, the figure illustrates the switching pattern produced by

the carrier-based PWM scheme. In the PWM scheme there are two triangles, the upper

triangle ranges from 1 to 0 and the lower triangle ranges from 0 to –1. In the similar way for

an N –level inverter, the (N-1) triangles are used and each has a peak-to-peak value of 2/ (N-

1). Hence the upper most triangle magnitude varies from 1 to (1-2/ (N-1)), second carrier

waveform from (1-4/ (N-1)), and the bottom most triangle varies from (2-2/ (N-1)) to –1. In

Figure 3.5, simulation of carrier-based Modulation Techniques 40 PWM scheme using the in

phase disposition (IPD) can be seen. The switching function for the devices is given by

Ha > Triangle -1 & Triangle -2; Ha3 =1, otherwise Ha3 =0.

Ha < Triangle -1 & Ha > Triangle -2; Ha2 =1, otherwise Ha2 =0.

Ha < Triangle -1 & Triangle -2; Ha1 =1, otherwise Ha1 =0.



It is clear from the figure that during the positive cycle of the modulation signal, when the

modulation is greater than Triangle 1 and Triangle 2, then S1ap and S2ap are turned on and

also during the positive cycle S2ap is completely turned on. When S1ap and S2ap are turned

on, the converter switches to the + Vdc / 2.When S1an and S2ap are on, the converter

switches to zero and hence during the positive cycle S2ap is completely turned on and S1ap

and S1an will be turning on and off and hence the converter switches from + Vdc / 2 to

0.During the negative half cycle of the modulation signal the converter switches from 0 to -

Vdc / 2.

Fig.3. Switching pattern produced using the IPD carrier-based PWM scheme: (a) two triangles and the

modulation signal (b) S1ap (c) S2ap (d) S1an (e) S2an

Fig. 4. Simulation of carrier-based PWM scheme using the in phase disposition (IPD). (a). Modulation

signal and in-phase carrier waveforms (b) Phase “a” output voltage.



For Cascaded Inverters, the common modulation strategy is to use continuous three levels

PWM within each individual inverter, with phase shifted carriers between the cascaded

inverters of each phase leg to achieve optimum harmonic cancellation within the phase leg.

Recent work has shown that this modulation strategy achieves the same harmonic

performance as the APOD technique for NPC inverters when the switching frequencies are

normalized so as to achieve the same overall number of switching transitions per fundamental

cycle. From this understanding, an improved modulation strategy for Cascaded inverters has

been developed using a discontinuous three level PWM strategy with 1800 phase shifted

carriers within each full bridge inverter, which achieves the same harmonic performance on a

line- to-line basis as does PD modulation for a NPC inverter. Since the Hybrid inverter

topology is derived from the Cascaded structure it is reasonable to expect that a similar

situation exists for the Hybrid inverter.

4. THE SIMULATION OF 5 LEVEL CASCADED INVERTER IS

CARRIED OUT IN MATLAB-SIMULINK. INDUCTION MOTOR (IM)

IS CONNECTED AS LOAD. THE SWITCHING SIGNALS ARE

GENERATED BY USING PID CONTROLLER. THE PARAMETER

USED ARE GIVEN BY SINGLE PHASE FIVE LEVEL CMLI

SIMULATION RESULTS

4.1. PID controller results

Model Parameters:

Vdc1 = 120V;

Vdc2 = 120V;

Motor – single phase 1hp CSCR motor;

Simulation Tool: Matlab/Simulink 2017a

PID Parameters:

Kp = 0.0015688

Ki = 0.022212

Kd = 0.00001

Controller type : Discrete Parallel form PID

Sampling Time : 5x10-5 s

Tuning : Tuned by using matlab PID tuner app

It can be seen that four switches (IGBT) with antiparallel diode are connected to form

single bridge and such two bridges are connected in cascaded i.e. output of one is connected

to input of next as shown in fig. 5 below. Single phase IM is connected as load as shown.

Simulation is solved in discrete with sample time of 5e-5 sec. Capacitor start run IM is used

as load. Rated torque is given as load and winding current, electromagnetic torque and Speed

is measured and plotted by using scope.



Fig.5. Simulink diagram of cascaded H-bridge five level inverter connected to single phase 1-HP

motor

The switching signal given to IGBT are given by signals S1, S2, S3 and S4 for upper

bridge and t1, t2, t3 and t4 for lower bridge. Inphase deposition is used for generating

switching signals. The details of switching signal generation are given in fig. 6. Required

speed is compared with actual one and controlled by PID controller. The control signal is then

used as modulating wave to control pulses generated. Two triangular waves are generated for

half cycle and compared with corresponding positive and negative cycle of sine wave to

generated switching signals as shown in fig. 6 and 7.



Fig.6. Simulink scketch for PWM generation using in-phase disposition and PID controller for speed

control.



Fig.7. Simulink sketch of connections of generated PWM pulses to the switches in the inverter

4.2. Simulation Result

The detail self-explanatory simulation results for parameters mentioned above are shown in

following figures. Triangular waves and sine wave signals used for IPD SPWM generation

method is shown in fig. 8. Here 4 triangle generators are used for 4 levels (zero level not

considered). Switches corresponding to the level are triggered when sine amplitude greater

than triangular wave.

Fig.8. Triangular waves and sine wave signals used for IPD SPWM generation method. Here 4

triangle generators are used for 4 level (zero level not considered). Switches corresponding to the level

are triggered when sine amplitude is greater than triangle.



PID controller graphs. (i) Represents the output control signal generated by the PID

controller in order to reach set point. (ii) Error signal given to the PID input, which is

difference between set point and actual speed. (Iii) Graph of the actual motor speed in RPM,

here RPM is varied in two steps are shown in fig. 9 Variation First at t=0 set point = 800 and

then at t = 4 set point is 1400; hence the reference tracking can be seen with step change in set

point.

Fig.9. PID controller graphs. (i) Represents the output control signal generated by the PID controller

in order to reach set point. (ii) Is the error signal given to the PID input, which is difference between

setpoint and actual speed. (iii) Graph of the actual motor speed in RPM, here RPM is varied in two

steps. First at t=0 setpoint = 800 and then at t = 4 setpoint is 1400, hence the reference tracking can be

seen with step change in setpoint

The corresponding values of Motor current taken by stator winding in amperes, rotor

speed of the motor in RPM and electromagnetic torque generated on the rotor in Nm is shown

in fig. 10

Fig.10. Motor data from measurement bus of motor block. (i) Graph of the current taken by stator

winding of the motor in Amperes (ii) Rotor speed of the motor in RPM (iii) Electromagnetic torque

generated on the rotor in Nm

The Voltage waveform of the five level inverter at the input of LC filter is shown in figure

11. It is observed that the waveform is distorted from its original five level shape.



Fig.11. Voltage waveform of the five level inverter at the input of LC filter. The waveform is distorted

from is original five level shape.

The Voltage waveform of the five level inverter at the output of LC filter is shown in fig. 12

Fig.12. Voltage waveform of the five level inverter at the output of LC filter. Next two figures show

expanded view of the waveforms for different RPM‟s of motor

Fig.13. Expanded view of the motor voltage at 800RPM



Fig.14. Expanded view of the motor voltage at 1400RPM As seen from the above figures, motor

voltage distortion reduces as the motor RPM reaches to its maximum level as motor gets every input

as per its rated values. Same effect is observed in next simulation conditions where motor speed is

varied in three steps 800RPM, 1000RPM and 1200RPM.

Fig.15. RPM Voltage of the five level inverter at the output of LC filter.

Fig.16. PID controller graphs. (i) represents the output control signal generated by the PID controller

in order to reach set point. (ii) Is the error signal given to the PID input, which is difference between

sepoint and actual speed. (iii) Graph of the actual motor speed in RPM, here RPM is varied in two

steps. First at t=0 setpoint = 800 and then at t = 4 setpoint is 1000, and at t= 6, setoint is 1200



Fig.17. Motor data from measurement bus of motor block. (i) Graph of the current taken by stator

winding of the motor in Amperes (ii)Rotor speed of the motor in RPM (iii) Electromagnetic torque

generated on the rotor in Nm

Fig.18. Voltage waveform of the five level inverter at the output of LC filter. Next two figures show

expanded view of the waveforms for different RPM‟s of motor (1000RPM and 1200RPM)





5. CONCLUSION

Multi-level converters can achieve an effective increase in overall switch frequency through

the cancellation of the lowest order switch frequency terms. This chapter has explained

different types of carrier based PWM modulation techniques. PWM method are advantageous

in controlling the output voltage and reducing the harmonics. There are many

modulation techniques for multi-level inverters. But carrier based modulation technique is

easy and efficient. The PWM output spectra were calculated from basic operation

explained above in phase disposition method and simulated using MATLAB (SIMULINK).

Future Scope

In future the performance analysis of 1-Phase five level cascaded multilevel inverter by using

sliding mode control (SMC) strategies hardware structure and compare the results with

Matlab simulation.

ACKNOWLEDGMENT

With great pleasure, I wish to express my deep sense of gratitude to my guide Dr. V. S.

Bandal for useful guidance, keen interest and valuable encouragement through the entire

preparation of paper.

I would like to thanks Principal, Head of Electrical Engineering Department of Sant. Gajanan

Maharaj College of Engineering, Shegaon for providing me a laboratory for my research

work.

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cascaded h- bridge multilevel inverter modulation ... · by conventional multilevel inverters, (ii)...

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