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SpaceWire BFM SpaceWire BFM for Test, Verification and for Test, Verification and Certification Certification Yuriy Sheynin St. Petersburg State University of Aerospace Instrumentation St.Petersburg, RUSSIA [email protected]

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Page 1: SpaceWire Test, Verification and Certification …spacewire.esa.int/WG/SpaceWire/SpW-SnP-WG-Mtg13...SpaceWire BFM for Test, Verification and Certification Yuriy Sheynin St. Petersburg

SpaceWire BFM SpaceWire BFM for Test, Verification and for Test, Verification and

CertificationCertification

Yuriy SheyninSt. Petersburg State University of Aerospace Instrumentation

St.Petersburg, [email protected]

Page 2: SpaceWire Test, Verification and Certification …spacewire.esa.int/WG/SpaceWire/SpW-SnP-WG-Mtg13...SpaceWire BFM for Test, Verification and Certification Yuriy Sheynin St. Petersburg

13th SpW WG Meeting, ESTEC 2009 2

Testing, Verification and Certification

Device Interoperability testing (DI);demonstrates interoperability with a limited set of reference devices.

Specification compliance testing (SC);demonstrates that a standard implementation complies the standard itself

Page 3: SpaceWire Test, Verification and Certification …spacewire.esa.int/WG/SpaceWire/SpW-SnP-WG-Mtg13...SpaceWire BFM for Test, Verification and Certification Yuriy Sheynin St. Petersburg

13th SpW WG Meeting, ESTEC 2009 3

What to Test, Verify and Certify (TVC)

SpaceWire Test and Verification:

Devices that implement SpaceWireSpaceWire links, link controller chips

SpaceWire nodes

SpaceWire routers

IP-blocks that implement SpaceWireRTL-models

Post-synthesis models

System-level models

Page 4: SpaceWire Test, Verification and Certification …spacewire.esa.int/WG/SpaceWire/SpW-SnP-WG-Mtg13...SpaceWire BFM for Test, Verification and Certification Yuriy Sheynin St. Petersburg

13th SpW WG Meeting, ESTEC 2009 4

Support for IP-blocks testing and verification

BFM (Base Formal Model)hierarchical model of a protocol stack

BFM levels correspond to the standard’s protocol stack layers.

BFM are programmed in a high-level languages (e.g. SystemC for RapidIO BFM, VHDL, Verilog)

Page 5: SpaceWire Test, Verification and Certification …spacewire.esa.int/WG/SpaceWire/SpW-SnP-WG-Mtg13...SpaceWire BFM for Test, Verification and Certification Yuriy Sheynin St. Petersburg

13th SpW WG Meeting, ESTEC 2009 5

Basic TVC package with a BFM

BFM (base formal model) of the protocol stackTest generator, test monitor and results controllerBFM wrapper (to connect BFM to an RTL or netlist)Test generator wrapper (to connect test generator to an RTL or netlist)

BFMUUT

(RTL or netlist)

BFM wrapper

Test generator

wrapper

Test generator

Test generatorTest monitor

Results controller

Signal based interfaces

Page 6: SpaceWire Test, Verification and Certification …spacewire.esa.int/WG/SpaceWire/SpW-SnP-WG-Mtg13...SpaceWire BFM for Test, Verification and Certification Yuriy Sheynin St. Petersburg

13th SpW WG Meeting, ESTEC 2009 6

SpaceWireSpaceWireBFM Structure

•Multilayered structure

•Simulation of all correct situations

•Simulation of errors

•SystemC(VHDL, Verilog could be used)

•Works in ncSim, ModelSim, etc.

Page 7: SpaceWire Test, Verification and Certification …spacewire.esa.int/WG/SpaceWire/SpW-SnP-WG-Mtg13...SpaceWire BFM for Test, Verification and Certification Yuriy Sheynin St. Petersburg

13th SpW WG Meeting, ESTEC 2009 7

BFM. Logical ports

Example of interface structure (logical ports):

int send_Ccode(t_code Ccode_);bool ready_to_send_Ccode();

t_code receive_Ccode();bool received_Ccode();

Page 8: SpaceWire Test, Verification and Certification …spacewire.esa.int/WG/SpaceWire/SpW-SnP-WG-Mtg13...SpaceWire BFM for Test, Verification and Certification Yuriy Sheynin St. Petersburg

13th SpW WG Meeting, ESTEC 2009 8

BFM wrappers. Working with separate layers

UUTUUT

Signal based interface

Logical ports interface

Page 9: SpaceWire Test, Verification and Certification …spacewire.esa.int/WG/SpaceWire/SpW-SnP-WG-Mtg13...SpaceWire BFM for Test, Verification and Certification Yuriy Sheynin St. Petersburg

13th SpW WG Meeting, ESTEC 2009 9

Testing with the BFM

IP-block (or chip) designer includes BFM modules in his testing environment , with the ready-made component models, test sequences and prescribed testing procedures

Complement the standard test set by specific for particular UUT settings

Runs the testing environment with his design for a sequence of standardized TVC procedures

Page 10: SpaceWire Test, Verification and Certification …spacewire.esa.int/WG/SpaceWire/SpW-SnP-WG-Mtg13...SpaceWire BFM for Test, Verification and Certification Yuriy Sheynin St. Petersburg

13th SpW WG Meeting, ESTEC 2009 10

BFM Integration with a user application

An application integrates BFM layer classes and methods with which the testing application needs to work(Transport layer at the figure)

The application can test sequences, send them through BFM to a UUT, receive reactions and analyse them

To/from the UUT

Page 11: SpaceWire Test, Verification and Certification …spacewire.esa.int/WG/SpaceWire/SpW-SnP-WG-Mtg13...SpaceWire BFM for Test, Verification and Certification Yuriy Sheynin St. Petersburg

13th SpW WG Meeting, ESTEC 2009 11

Open problems in TVC

To be provided with the SpaceWire standard :Methodology for Test and Verification(informative)

Methodology for Certification (normative)

Test sets that support the methodology

Instruments for Test, Verification and Certificationsupport in development,

an open recommended list of instruments

Page 12: SpaceWire Test, Verification and Certification …spacewire.esa.int/WG/SpaceWire/SpW-SnP-WG-Mtg13...SpaceWire BFM for Test, Verification and Certification Yuriy Sheynin St. Petersburg

Thank you !