sd 5.12 312278514120

Published by Liu BZH 0367 Service BPAVC Printed in the Netherlands Subject to modification EN 3122 785 14120

©Copyright 2002 Philips consumer Electronics B.V. Eindhoven, The Netherlands,All rights reserved. No part of this publication may be reproduced, stored in aretrieval system or transmitted, in any form or by any means, electronic,mechanical, photocopying, or otherwise without the prior permission of Philips.

DVD-Video Player Module MSD-512S

Contents Page

1 Technical Specs and Connection Facilities 22 Safety Instructions, Warnings, Notes,

and Service Hints 123 Directions for Use (Not Applicable) 144 Mechanical and Dismantling Instructions 145 Diagnostic Software, Trouble Shooting and Test

Instructions 156 Wiring, Block Diagrams

Block Diagram 25Wiring Diagram 26

7 Electrical Diagrams and Print-Layouts Diagram PWBMPEG Board: Decoder & Peripheral Circuits 27 33-34MPEG Board: Memory Part 28 33-34MPEG Board: Audio Part 29 33-34MPEG Board: Video Part 30 33-34MPEG Board: Power and Scart port 31 33-34

8 Alignments (Not Applicable) 359 Circuit Descriptions (Not Applicable) 3510 Spare Parts List

Spare Parts List MSD-512S/00 41Spare Parts List MSD-512S/69 41Spare Parts List MSD-512S/78 44Spare Parts List MSD-512S/ARG 44

Appendix: Datasheet ZiVA-5+

EN 44 2 MSD-512S Technical specifications

1.1. Technical Specifications MSD-512S/ 00/69/78/ARG

1.11.1 Specifications Overview

PLAYBACK SYSTEM

Specifications subject to change without prior notice

AUDIO PERFORMANCE

DA Converter 24bit/192kHz Signal-Noise (1KHz) 100dBDynamic range(1KHz) >90dBDVD fs 96 kHz 4Hz- 44kHz

fs 48 kHz 4Hz- 22kHzSVCD fs 48 kHz 4Hz- 22kHz

fs 44.1kHz 4Hz- 20kHzCD/VCD fs 44.1kHz 4Hz- 20kHz

TV STANDARD (PAL/50Hz) (NTSC/60Hz)

Number of lines 625 525Playback Multistandard (PAL/NTSC)

CONNECTIONS

Video Output (Y/C) EH connector (4pin Black)Audio Output(L+R) EH connector (3pin Black)Digital Output EH connector (3pin White)

IEC958 for CDDA / LPCM/ MPEG1IEC1937 for MPEG 2, DolbyDigital and DTS

I2C Bus EH connector (4pin White)Service Connector EH connector (7pin White)Power SupplyPower to Mpeg PWB can be applied via connector1615 +5VDC 1100 mA +/-5%+12VDC 60 mA +/-10%-12VDC 105 mA +/-10%

Power to Loader (A97ST)+5VDC 530 mA +/-5%+12VDC 200 mA +/-10%

DVD VideoVideo CD & SVCDCDPICTURE CDMP3-CDCD-R, CD-RWDVD+R, DVD+RW

VIDEO PERFORMANCE* CVBS 1Vpp --- 75* S-VIDEO Y: 1.00Vpp --- 75

C: 0.30Vpp --- 75*Component video Y: 1.00Vpp --- 75

Pr : 0.7Vpp --- 75Pb: 0.7Vpp --- 75

AUDIO FORMAT

Digital Mpeg/ AC-3/ DTS compressed DigitalPCM 16, 20, 24 bits

fs, 44.1, 48, 96 kHzMP3(ISO 9660) 24, 32, 56, 64, 96, 128,

256 kbps & variablebit rate fs, 16, 22.05,24, 32, 44.1, 48 kHz

Analog Sound Stereo

EN 443MSD-512STechnical specifications

1.2 Technical Specifications

1.2.1 Introduction

MSD-512S use the same mpeg board for differenceslash version, with A97S loader for DVD set and with A97ST loader for TV combi, both of them have the same technical specification.

The SD5.12 module shall contain:1. LSI Logic ZiVA5M+ DVD decoder / host

processor.

2. Basic Audio/Video circuits and the outputconnectors.

3. ATAPI interface, both for A97S and A97ST.4. Diagnostic interface.5. Connectors for TV and DVD set used. 6. JTAG interface.

1.2.2 Mechanical construction

When the mpeg board is placed beside the loader,all mpeg board interfaces are located on the topside of the board, as shown below:


1.2.3 Key components for SD5.12

DVD back-end

Part No Manufacturer Description Remark

ZiVA-5M+ LSI Logic DVD back-end processor Basic function

MT48LC2M32B2TG-7 Micron 64Mbit SDRAM 32bit

M29W160DT/

M29W160ETST Microelectronics 2Mbyte flash memory

Top level, TSOP48 package, for UI2002 s/w

74LVT573DB Philips Semiconductor D-type transparent latch 3.3V, SOT339-1 package

M24C64 ST Microelectronics 64Kbit I2C bus EEPROM --

AK4382A AKM 2-ch Audio DAC 2 channel, Diff output

Miscellaneous

Part No Manufacturer Description Remark

LD1117ADT18 ST Microelectronics 1.8V voltage regulator Adjust from 3.3V to 1.8V

LD1086D2T33 ST Microelectronics 3.3V voltage regulator Adjust from 5V to 3.3V

MC78L05ACD Motorola 5V voltage regulator Adjust from 12V to 5V

Note: This key component list should only be used as a rough indication to the content of the SD5.12 module. For actual component used, always refer to the module’s official bomlist.

1.2.4 PCB specifications

The PCB of SD5.12 should be according to Lightning Stroke. Refer to the PCB’s Sheet 110. The PCB size is 150x100mm, double layer, FR4 material.

1.2.5 Power supply and grounding concept

1.2.5.1 Power supply

To improve performance, multiple power supply and grounding are adopted. Additionally, the supply voltages to the mpeg board are channeled through fusible resistors to comply with PCE safety requirements.

Power to Mpeg PWB can be applied via connector 1615.

Power name Rating Description Used by

+5VD +/-5% 1100 mA Digital power supply Digital circuits

+12VA +/-10% 60 mA Analog power supply Analog circuits

-12VA +/-10% 105 mA Analog power supply Analog circuits

Power to Loader (A97ST):

Power name Rating Description Used by

+5VL +/-5% 530 mA Digital power supply Loader

+12VL +/-10% 200 mA Spindle power supply Loader

To achieve good power supply isolation among analog and digital, the power supply to all sub-sections are originated from different voltage regulators, supply lines or decoupled using ferrite beads.

1.2.5.2 Grounding

Ground name Description Used by

GNDD Digital parts ground Digital circuitry

GNDA Analog parts ground Analog circuitry (including audio and video)

In order to control EMC radiation:

• Bypass capacitors and ferrite beads or jumpers are placed at strategic locations.

• An uninterrupted ground strip is placed at every layer around the edges of the PCB, to reduce EMC leakage from the edges.

• Screw mounting points to chassis are available at three corners of the PCB, with optional series capacitors or jumpers to ground.


1.2.6 Interface pin assignments

Connector Pin Assignment Description

1603 M_I2C_DA Master I2C data, for master control, TV used

EH connector

1

L_I2C_DA Slave I2C data, for slave control, TV used

Straight/vertical M_I2C_CL Master I2C clock, for master control, TV used 2

L_I2C_CL Slave I2C clock, for slave control, TV used

3 GNDD Digital ground, for TV used

4 S_I2C_RDY I2C interrupt, for TV used

Note:This connector is used for I2C control signal for TV used, the configuration refer to the model mode slash version.


1619 1 Y_VID Y luma video

EH connector 2 GNDA Analog ground

Straight/vertical 3 C_VID C chroma video

4 GNDA Analog ground

Note: This connector is for Y/C for TV and DVD set used.


1620 1 GNDD Digital ground, for TV and DVD set used

EH connector 2 SPDIF SPDIF output, for TV and DVD set used

5VD Digital power supply, for DVD set used

Straight/vertical3

GNDD Digital ground, for TV used

Note: This connector is for SPDIF output, TV and DVD set used.


1621 1 R_OUT Right channel analog output

EH connector 2 GNDA SPDIF output

Straight/vertical 3 L_OUT Left channel analog output

Note: This connector is for analog 2-ch audio output, TV used.


1601 1 /LDRST ATAPI interface reset

Header 2.54mm 2 ATAPI_GND Ground

Straight / vertical 3 DD15 ATAPI bus bit 15

4 DD0 ATAPI bus bit 0






1601 10 DD3 ATAPI bus bit 3

Header 2.54mm 11 DD11 ATAPI bus bit 11

Straight / vertical 12 DD4 ATAPI bus bit 4







19 ATAPI_GND Ground

20 NC Not connected

21 DMARQ DMA request (not used)

22 ATAPI_GND Ground

23 LDS Data IO write


24 ATAPI_GND Ground

25 DUS Data IO read

26 ATAPI_GND Ground

27 /DTACK Data acknowledge

28 NC Not connected

29 DMACK DMA acknowledge (not used)

30 ATAPI_GND Ground

31 HIRQ1 Interrupt request

32 NC Not connected

33 UPA2 ATAPI address bus bit 1

34 NC Not connected



37 /IDE_CS0 IDE0 device select

38 /IDE_CS1 IDE1 device select

39 NC Not connected

40 ATAPI_GND Ground

Note: This is the ATAPI connector that connect to A97S and A97ST loader.


1600 1 TXD_SER TXD service UART

PH connector 2 SERVICE Service or normal mode select

Straight/vertical 3 RXD_SER RXD service UART

4 RTS_SER Not used (RTS service UART)

5 GNDD Digital ground

6 CTS_SER Not used (CTS service UART)

7 5VD Positive 5V (isolated from internal +5V by ferrite bead)

Note: This connector is contributed to Diagnostic purpose.


1605 1 STDY_CTRL Standby switch

EH connector 2 VFD_DATA VFD driver control signal (data, bi-direction)

Straight/vertical 3 VFD_CLK VFD driver control signal (clock, output)

4 VFD_CS VFD driver control signal

5 GNDD Digital ground

6 IR IR signal (optional)

Note: This connector is contributed to VFD driver purpose, for DVD used only.


1618 1 R_VID Red (V chroma) video

EH connector 2 GNDA Analog ground

Straight/vertical 3 B_VID Blue (U chroma) video

4 GNDA Analog ground

5 G_VID Green (Y luma) video

Note: This connector is for YUV or RGB output for TV and DVD set used. YUV and RGB share the same signals, can’t output YUV and RGB at the same time.


1610 1 5VD 5V power supply for DVD used

EH connector 2 GNDD Digital ground

Straight/vertical 3 -12VA -12VA power supply for DVD used

Note: This connector is only for DVD used for video buffer purpose, it is optional.



1606 1 SCART-R Audio Out Right

SCART connector 2 N/u Audio In Right

3 SCART-L Audio Out Left + Right

4 GNDA Audio Ground

5 GNDA RGB Blue Ground

6 N/u Audio In Left + Mono1

7 BLUE RGB Blue

8 0/6/12 Audio/RGB switch/16:9

9 GNDA RGB Green Ground

10 N/u Clock Out

11 GREEN RGB Green

12 N/u Data Out

13 GNDA RGB Red Ground

14 GNDA Data Out

15 RED RGB Red/Chrominance

16 FBOUT Blanking Signal

17 GNDA Composite Video Ground

18 GNDA Blanking Signal Ground

19 CVBS Composite Video Out

20 N/u Composite Video In/Luminance

21 GNDA Ground/Shield (connected to chassis)

1.2.7 Signal specifications

This section defines the specifications of the signals at the module interface. The audio and video signal specifications are only partially covered in this section. For the complete audio and video signal specifications, refer to 0 1.2.13 Audio performance and 0 1.2.14 Analog video performance. The signal specifications can be classified into the followings:

Signal type Description Definition

Absolute maximum rating:

VIN = -0.5V to 5.5V

VOUT = -0.5V to 5.5V

Parameter

VIH (V)

VIL (V)

VOH (V)

VOL (V)

TTL

Transistor-transistor logic (5V logic)

Caution:

Exceeding the absolute maximum rating will cause damage to the module.

Absolute maximum rating:

VIN = -0.5V to 3.8V

VOUT = -0.5V to 3.8V

Maximum current drive: 4mA

Parameter

VIH (V)

LVTTL

Low voltage transistor-transistor logic (3.3V logic)

Caution:


VIL (V)


VOH (V)

VOL (V)

Signal type Description Definition

I2C

Inter-IC

All I2C signals at the module’s connectors are 5V levels.

[I2C_SPEC]

I2S

Inter-IC sound

All I2S signals at the module’s connectors are at LVTTL levels.

Caution:


[I2S_SPEC]

RS232_COMP RS232 compatible specifications

VIN approximately 3V threshold, 6kohm resistance

VOUT = 0 to 5V, 1kohm output resistance

H/L 5V logic states H = +5V ± 0.5V

L = 0V ± 0.5V

h/l 3.3V logic states h = +3.3V ± 0.3V

l = 0V ± 0.3V

1.2.7.1 SPDIF out

Function: Digital audio output Signal: SPDIFOUT Type: TTL output (22ohm output resistor, in series) See 0. 1.2.13 Audio performance.

1.2.7.2 Analog audio

Function: Analog audio output Signal: L_OUT, R_OUT See 0. 1.2.13 Audio performance.

1.2.7.3 Audio mute

Function: Audio mute control Signal: MUTEC Type: TTL output

Function MUTE (TTL output)

Mute off LOW

Mute on HIGH

1.2.7.4 Analog video

Function1: Analog video output without buffer (to connector for TV and DVD set, 75ohm resistors in series) Signal: C_VID, YVID, G_VID, B_VID, R_VID

Function2: Analog video output with buffer (CVBS and RGB to SCART output) Signal: CVBS_OUT, R_OUT, G_OUT, V_OUT

See 0. 1.2.14 Analog video performance.

1.2.7.5 Slow blanking SCART

Function: Slow blanking SCART Signal: 0/6/12 Type: the output level refer to the last column.


Function SCART0 (LVTTL output) SCART1 (LVTTL output) 0/6/12(V)

TV display HIGH HIGH 0

TV display LOW HIGH 0

16:9 aspect ratio HIGH LOW 6

4:3 aspect ratio LOW LOW 12

0/6/12 signal is produced by SCART0 and SCART1, the related circuits refer to electrical diagrams.

1.2.7.6 I2C

Function: I2C bus Signal: I2CSCL, I2CSDA Type: I2C

1.2.7.7 DAC control bus

Function: DAC control bus Signal: DAC_CLK, DAC_DATA, DAC_CS Type: DAC_CLK output DAC_DATA bi-directional DAC-CS output

1.2.7.8 VFD bus ( for DVD set only)

Function: VFD bus Signal: VFD_CLK, VFD_DATA, VFD_CS Type: VFD_CLK output VFD_DATA bi-directional VFD_CS output

1.2.7.9 Service bus

Function: Service and diagnostic bus Signal: TXD_SER, RXD_SER, Type: RS232_COMP (TXD_SER output, RXD_SER input)

1.2.7.10 Service activation

Function: To activate service mode Signal: SERVICE Type: LVTTL input

Function SERVICE (LVTTL)

Service mode LOW (or short to ground)

Normal mode HIGH (or unconnected)

Note: This line is pulled to HIGH via 10kohm resistor. A module reset is required to activate service mode.

1.2.7.11 Service +5V

Function: Positive 5V line in the Service connector Signal: +5V_SER Type: Power supply; this line is connected to 5VD through a ferrite bead

1.2.8 Software

The MPEG board software (also known as the application software) exist in flash memory, and it is dependent on the module versions.

For flash memory versions, the software can be programmed via the DCU interface (JTAG interface). This interface is exposed as 6 test points at the bottom of the module. The DCU interface method can be used even when the existing content of the flash memory is undefined. Additionally, the software can be upgraded / reprogrammed via a “download disc”. The download disc method requires that the flash memory already contain valid software.

1.2.9 Module control

Communication with the module in normal mode is via I2C bus. For service and diagnostic of the module, the Service mode can be activated (using the Service interface).


1.2.10 Power supply requirements

Output voltage Output current Voltage name

Min(V)

Typ (V)

Max(V)

Vrip(Mvpp)

Off (V)

Play min Play-Typ Play- max

+5VD 4.75 5.00 5.25 50 <0.2 600 1200 1400

*2+12VA 10.80 12.00 13.20 100 <0.5 10. 60 70

-12VA -10.80 -12.00 -13.20 100 >0.5 -90*1

-140*1

-160*1

Notes :1.

*1This current has already include the extra current request from test centre (FNAC).

2.*2

The 12VA switch will be shifted to MPEG board due to the architecture issue. So please reserve the switch in the layout

3. Audible noise is not allowed at normal or standby mode. 4. A ceramic SMD capacitor of 22nF is required at the output of +/-12VA to reduce the impedance of output. 5. +5VD is for digital parts, +12VA/-12VA is for analog circuit of DVD player(TV need +12VA only).

1.2.11 Playability

Media Data type Remark

DVD-Video (SL, DL, SS, DS) DVD video

DVD-R (3.95 and 4.7GB) DVD video

DVD+RW DVD video

DVD+R DVD video

CDDA CD audio

CD-Bridge (CDROM data) VCD

CDR / CDRW CD audio, VCD

CDR / CDRW MP3 (ISO9660, Joliet) Finalized and unfinalized

CDR/CDRW CD-ROM data Software download disc

VCD VCD versions 1.0, 1.1 and 2.0

DVCD VCD

SVCD CVD, ChaoJi and Shinco SVCD Normally SVCD

Hybrid SACD CD audio and SACD CD layer

Disc diameter Remark

12cm

8cm

1.2.12 Access time

No Type Parameter Specification Test disc

17.01 No disc Standby state no disc 2.0 s None

17.02 No disc No disc open tray 2.0 s None

17.03 No disc Open tray closed tray 2.0 s None

17.11 CDDA Tray open play state 7.0 s SBC442 (7104 087 04861)

17.12 CDDA Stop state play state 2.5 s SBC442 (7104 087 04861)

17.13 CDDA Access (track 1 – track 20) 2.0 s SBC442 (7104 087 04861)

17.21 VCD Tray open play state (PBC) 8.0 s Philips Production VCD2.0 test disc (7104 099 36471)

17.22 VCD Stop state play state (PBC) 3.0 s Philips Production VCD2.0 test disc (7104 099 36471)

17.31 DVD SL Tray open play state 8.0 s MPTD CVP02.18A (7104 099 91691)

17.32 DVD SL Stop state play state 3.0 s MPTD CVP02.18A (7104 099 91691)

17.33 DVD SL Access (title 1 – title 40) 2.5 s MPTD CVP02.18A (7104 099 91691)

17.34 DVD SL Play state standby state 4.0 s MPTD CVP02.18A (7104 099 91691)

17.35 DVD SL Play state open tray 3.0 s MPTD CVP02.18A (7104 099 91691)

17.41 DVD DL Tray open play state 10.0 s Burn-in disc, LVP04.15 (7104 099 91141)

Note:1. Open tray – tray fully open 2. No disc – when front panel display shows NO DISC 3. Play state – when sound/video starts, or when front panel display shows 0:00 4. Stop state – when disc not spinning (disc already in loader and TOC has been read) 5. Track/title change – from end of key press to next track/title play state


6. Standby state – when player is in standby mode (the module is actually power-off)

1.2.13 Audio performance

1.2.13.1 SPDIF out

Function: Digital audio output Signal: SPDIFOUT Type: Output according to IEC60958 or IEC61937, except at TTL levels (22ohm output resistor, in series)

Note: To meet the complete SPDIF specification, an external decoupling/drive circuit is necessary.

1.2.13.2 Analog audio

Function: Analog audio output Signal: L_OUT, R_OUT

Performance: Reference is made to the [PQR-IMS]. All performance complies fully with PQR class III.

1.2.13.3 Audio connector

The audio connector for DVD used including Lt/Rt, Coaxial and SCART output.

1.2.14 Analog video performance

The video output standard follows the source material. The OSD can be switched between PAL and NTSC by the application software.

The module has 5 analog video outputs in 4 format: CVBS, Y/C, and RGB (YUV).

For DVD set used, the output format including: CVBS, Y/C, YUV

Signal name Video format Remark

CVBS_OUT CVBS CVBS on mpeg board

Y_VID, C_VID Y/C For a/v board

Y_VID, B_VID, R_VID YUV(RGB) For a/v board

For TV used, the output format including: Y/C and YUV(RGB)

Signal name Video format

Y_VID, C_VID Y/C

R_VID, B_VID, G_VID YUV(RGB)

Note:There are a 75ohm output resistor in series for Y/C and YUV (RGB) signals, RGB and YUV component video signals shared the same lines. Therefore, the module is not able to output both RGB and YUV at the same time.

The video outputs comply fully with [PQR_IMS]. Although not mentioned in [PQR_IMS], RGB and YUV have similar specifications.

Superimposed DC level: 1.2V Output impedance: 75ohm

Note:The video performance complies fully with PQR class III. But the following specifications are better than [PQR_IMS]: Signal-to-noise ratio: better than 65dB. Video bandwidth: 8MHz +/-3dB

Copy Protection: CSS WSS,Closed Caption Macro-vision Version 7.1.L.1 for NTSC/PAL interlaced video outputs

The analog video output connector including CVBS and SCART.

EN 44 12 MSD-512S Warnings, lasersafety instructions and notes

2. Safety Instructions, Warnings, Notes, and Service Hints

2.1 Safety Instructions

2.1.1 General Safety

Safety regulations require that during a repair: Connect the unit to the mains via an isolation transformer. Replace safety components, indicated by the symbol ,

only by components identical to the original ones. Any other component substitution (other than original type) may increase risk of fire or electrical shock hazard.

Safety regulations require that after a repair, you must return the unit in its original condition. Pay, in particular, attention to the following points: Route the wires/cables correctly, and fix them with the

mounted cable clamps. Check the insulation of the mains lead for external

damage. Check the electrical DC resistance between the mains plug

and the secondary side:1. Unplug the mains cord, and connect a wire between

the two pins of the mains plug.2. Set the mains switch to the 'on' position (keep the

mains cord unplugged!).3. Measure the resistance value between the mains plug

and the front panel, controls, and chassis bottom. 4. Repair or correct unit when the resistance

measurement is less than 1 Mohm.5. Verify this, before you return the unit to the customer/

user (ref. UL-standard no. 1492).6. Switch the unit ‘off’, and remove the wire between the

two pins of the mains plug.

2.1.2 Laser Safety

This unit employs a laser. Only qualified service personnel may remove the cover, or attempt to service this device (due to possible eye injury).

Laser Device UnitType : Semiconductor laser

GaAlAsWavelength : 650 nm (DVD)

: 780 nm (VCD/CD)Output Power : 20 mW

(DVD+RW writing)

(DVD reading): 0.3mW

(VCD/CD reading)Beam divergence : 60 degree

Figure 2-1

Note: Use of controls or adjustments or performance of procedure other than those specified herein, may result in hazardous radiation exposure. Avoid direct exposure to beam.

2.2 Warnings

2.2.1 General

All ICs and many other semiconductors are susceptible to electrostatic discharges (ESD, ). Careless handling during repair can reduce life drastically. Make sure that, during repair, you are at the same potential as the mass of the set by a wristband with resistance. Keep components and tools at this same potential.Available ESD protection equipment:– Complete kit ESD3 (small tablemat, wristband,

connection box, extension cable and earth cable) 4822 310 10671.

– Wristband tester 4822 344 13999. Be careful during measurements in the live voltage section.

The primary side of the power supply (pos. 1005), including the heatsink, carries live mains voltage when you connect the player to the mains (even when the player is 'off'!). It is possible to touch copper tracks and/or components in this unshielded primary area, when you service the player. Service personnel must take precautions to prevent touching this area or components in this area. A 'lightning stroke' and a stripe-marked printing on the printed wiring board, indicate the primary side of the power supply.

Never replace modules, or components, while the unit is ‘on’.

2.2.2 Laser

The use of optical instruments with this product, will increase eye hazard.

Only qualified service personnel may remove the cover or attempt to service this device, due to possible eye injury.

Repair handling should take place as much as possible with a disc loaded inside the player.

Text below is placed inside the unit, on the laser cover shield:

Figure 2-2

2.2.3 Notes

DolbyManufactered under licence from Dolby Laboratories. “Dolby”, “Pro Logic” and the double-D symbol are trademarks of Dolby Laboratories. Confidential Unpublished Works.©1992-1997 Dolby Laboratories, Inc. All rights reserved.

Figure 2-3

TrusurroundTRUSURROUND, SRS and symbol (fig 2-4) are trademarks of SRS Labs, Inc. TRUSURROUND technology is manufactured under licence frm SRS labs, Inc.

Figure 2-4

CAUTION VISIBLE AND INVISIBLE LASER RADIATION WHEN OPEN AVOID EXPOSURE TO BEAM ADVARSEL SYNLIG OG USYNLIG LASERSTRÅLING VED ÅBNING UNDGÅ UDSÆTTELSE FOR STRÅLING ADVARSEL SYNLIG OG USYNLIG LASERSTRÅLING NÅR DEKSEL ÅPNES UNNGÅ EKSPONERING FOR STRÅLEN VARNING SYNLIG OCH OSYNLIG LASERSTRÅLNING NÄR DENNA DEL ÄR ÖPPNAD BETRAKTA EJ STRÅLEN VARO! AVATT AESSA OLET ALTTIINA NÄKYVÄLLE JA NÄKYMÄTTÖMÄLLE LASER SÄTEILYLLE. ÄLÄ KATSO SÄTEESEEN VORSICHT SICHTBARE UND UNSICHTBARE LASERSTRAHLUNG WENN ABDECKUNG GEÖFFNET NICHT DEM STRAHL AUSSETSEN DANGER VISIBLE AND INVISIBLE LASER RADIATION WHEN OPEN AVOID DIRECT EXPOSURE TO BEAM ATTENTION RAYO NNEMENT LASER VISIBLE ET INVISIBLE EN CAS D'OUVERTURE EXPOSITION DANGEREUSE AU FAISCEAU

0.8 mW:

EN 4413MSD-512SWarnings, lasersafety instructions and notes

2.3 Service Hints

2.3.1 Handling Chip Components

Figure 2-5 Handling Chip Components

CL 26532047_002.eps050402

2.4 Service Tools

Test discs– Audio signals disc 4822 397 30184

Torx screwdrivers– Set (straight, T2 to T20 4822 395 50145– Set (square, T10, T15, T20to T20 4822 395 50132

2.5 Revision Information

Service Manual Version : 1.0

Issue Date : Jun, 2003

Revision Information : N/A

2.3.2 ComPair

There is no ComPair available.

EN 44 14 MSD-512S Dismantling instructions and exploded view

1. Uncover the top shield

2. Remove the two screws

Bottom shield

3. Unsolder the three joints

3. Directions for use

Not Applicable

4.1 Exploded view - Loader Assy

4.2 Dismantling instructions and exploded view -MPEG Assy

EN 4415MSD-512SDiagnostic Software descriptions and troubleshooting

5. Diagnostic software descriptions and troubleshooting

5.1 Introduction

5.1.1 PurposeThis chapter describes all interfaces from the outside world to the diagnostic software, what is needed to use these interfaces and how to accessthem. This chapter will specify the softwarerequirements of the Diagnostic Software for the SD5.12, SD5.2, and SD5.31 Modules (using LSI Logic’s ZiVa5 backend processor). This alsoincludes support for players/sets that use the said modules, whether I2C master or I2C slave.

5.1.2 ScopeThis chapter has been realized within the frameworkof the product development of the DVD (or combi) player based on the SD5.12, SD5.2 or SD5.31 module. It will only containinformation relevant to the version 7.xx (Y) of the Diagnostic software.

5.1.3 Definitions and abbreviations

5.1.3.1 DefinitionsControl PC:Automatic test equipment, part of the productioncontrol system in the factory, to control the execution of Diagnostic Nuclei in the DVD player.Diagnostic Nucleus:Part of the Diagnostic Software. Each nucleuscontains an atomic and software independentdiagnostic test, testing a functional part of the DVD player hardware on component level. Script:Part of the Diagnostic Software. Each script contains a sequence of Diagnostic Nuclei to be executed.Service PC:PC used by a service- or repair-person to communicate with the Diagnostic Software in the DVD player.

5.1.3.2 AbbreviationsFDS: Full Diagnostic Software

5.2 Overview of Interfaces

The table below shows an overview of the user interfaces of the Diagnostic Software. The table is based on logical interface, interfaces as seen from user perspective. A logical interface can use one or more physical interface components.The DVD has only a single RS232 port, implyingthat all interfaces using this port are mutuallyexclusive.

In the next chapters the logical user interfaces are described in more detail including the exact use of the physical interface components.

Front Panel Key Usage:Some of the nuclei used in the diagnostic softwarerequire user intervention through the front panelkeys. The keys used are defined according to the model and what is indicated in the [MRS_DSS] and [SDD_DN].

5.3 Description Of Interfaces

5.3.1 Menu InterfaceThe menu interface is part of the Level 2 / SecondLine diagnostic mode. It is possible to control theexecution of the Diagnostic Nuclei via the menuinterface.

5.3.1.1 Set-up physical interface components Hardware required:

• Service PC

• One free COM port on the Service PC

• Special cable to connect DVD player to ServicePC

The service PC must have a terminal emulationprogram (e.g. OS2 WarpTerminal or Procomm / Windows Hyperterminal) installed and must have a free COM port (e.g. COM1). Activate the terminal emulation program and check that the port settings for the free COM port are 19200 bps, 8 data bits, no parity, 1 stop bit and no flow control. The free COM port must be connected via a special cable to the RS232 port of the DVD player. This special cablewill also connect the test pin, which is available onthe connector, to ground (i.e. activate test pin).

5.3.1.2 ActivationSwitch AC power of the player to ON and the following text will appear on the screen of theterminal (program):

Note: for SD5.xx modules, the operating systemoutputs startup messages prior to starting the DSWat a baud rate equal to 38400. Because the terminalemulation program running in the PC is set to 19200baud, such startup messages may (or may not) be seen as invalid characters on the terminal screen. This is not considered as a problem in the software.

DVDv6 Diagnostic Software version 7.00 A

Front Panel Processor: SLAVE 2

(M)enu, or (C)ommand ? [M]:@

EN 44 16 MSD-512S Diagnostic Software descriptions and troubleshooting

The first line indicates that the Diagnostic softwarehas been activated and contains the versionnumber of the diagnostic. This is also an indicationthat the first basic nucleus (nucleus number 1) has been executed successfully. The term “DVDv6”implies that the DSW is running in the ZiVA5platform (6th generation). Interpretation of the DSWversion is done as follows:

The next line displays the result of the subsequentbasic tests (the detection of the display type usedby the panel). See [SDD_DN] for an explanation of this nuclei. If not all these messages appear on the terminal screen, then the related nucleus found an error. The last line is the prompt asking the user to choose the interface format. If the Menu Interface is chosen (enter ‘m’), the main menu will then appear.For the layout of the menus, see appendix B.

To switch between interfaces, the DVD playerneeds to be switched off and on again.

Note1: Some DVD players have no power-ON key, but can beturned on by connecting the power-cable.

5.3.1.3 UsageTo select, type the number of the chosen menu-itemat the prompt. Each entry must be terminated with a <return>. Invalid selections will cause an errormessage by the Menu Handler. Example:

Select> 99Invalid menu choice, number out of range ER @Press RETURN to continue...@

Result and output of an activated (and terminated) nucleus willbe sent back to the service terminal according to the standardlayout as defined in Appendix C. Example:

Select> 3 1300 OK @Press RETURN to continue...@

After the user presses a key, the current menu is rebuilt on screen.Pressing <return> at the prompt without any furtherinput at the terminal will return the user the parentmenu in the menu hierarchy.

5.3.1.4 TerminationThe menu interface can only be terminated byswitching off AC power to the DVD player/module.

5.3.2 Command Line InterfaceThe command line interface is part of the level 1 diagnostic mode. The execution of DiagnosticNuclei can be controlled via a command lineinterface.(YY) Minor revision number, a two-digit number

incremented for every release of a DSW variant.

5.3.2.1 Set-up physical interface components Hardware required:

(X) Major revision number, always fixed to 7• Control PC

• One free COM port on the Control PC

version X.YY Z • Special cable to connect DVD player to the Control PC

The control PC must use the following port settingsfor the used COM port: 19200 bps, 8 data bits, no parity, 1 stop bit and no flow control. The control PC is connected with a special cable to the RS232 port of the DVD player. Via the same connection the test pin will be connected to ground.

(Z) DSW variant ID letter, identifies the module/player wherethis DSW was targeted to run:A – SD5.11, I2C Master module-based playersB – SD5.2, I2C Master module, used in DVD760 playersC – SD5.2, I2C Master module, used in high-end SACD2003playersD – SD5.12, I2C Slave module, used in MTV combiapplicationsS – SD5.31, I2C Slave module, used in MTV combiapplications

5.3.2.2 ActivationAfter power on the following text will be sent to the control PC

After switching ON the set with the special cableconnected to the PC, the diagnostic software willask the user for the mode of operation. Enter “C” to select Command mode. The last line is the prompt(“DD:>”). The diagnostic software is now ready to receive commands.

Note: Some DVD players have no power-ON key, but can be turned on by connecting the power-cable.

DVDv6 Diagnostic Software version 7.00 A

Front Panel Processor: SLAVE 2

(M)enu, or (C)ommand ? [M]:@ C Enter

DD:>

5.3.2.3 UsageThe commands that can be given are the referenceIDs of the test nuclei. A command must be terminated with a <return> character from the control PC. When typing commands, the backspacekey can be used to make corrections.In case of typing errors in the command, an error message is returned. Example:

DD:>CompSdramWrR¿ (Nuclei name cannot be accepted) 0001 Unknown command ER @

DD:>

If the command (the nucleus ID) is recognized, the nucleus is executed. Results and outputs of an activated (and terminated) nucleus will be sent back to the control PC according to the standard layoutas defined in Appendix C.

Example for a command without error:

DD:>13¿ (Execute PapAtapiEcho nuclei)1300 OK @DD:>


Example for a command with error:DD:>13¿1304 No response from ATAPI drive ER @ DD:>

5.3.2.4 TerminationThe command line interface is terminated byswitching off AC power from the DVD player/module.

5.3.3 UDE Interface (not available yet, applies only toSD5.2 modules)

5.3.3.1 Set-up physical interface components Hardware needed:

• Control PC

• One free COM port on the Control PC

• Special cable to connect DVD player to ControlPC

• UDE monitor tool running on the Control PC

5.3.3.2 ActivationTo start the UDE interface, connect the RS232cable to the Control PC in the correct manner. Thenstart the PC, start the monitor tool and start the DVD player. Select the UDE-interface by typing ‘u’at the first command prompt. Next, turn off the monitor tool and turn on UDE monitor tool. The UDE monitor tool now takes-over all communication.The UDE interface can also be activated by sendinga character with the ASCII bit pattern <TBD> at the first command prompt, when the user is asked to choose an interface type. The command handler willthen activate the UDE pass-through nucleus. Thecharacter sent will be passed to this nucleus withoutloss.

Note: Some DVD players have no power-ON key, but can be turned on by connecting thepower-cable.

5.3.3.3 TerminationTo terminate UDE pass-through mode, switch off AC power to the DVD player/module

5.3.4 Script Interfaces (for I2C Master mode modulesonly)This interface is used during execution of the PlayerScript and the Dealer Script to display output and error messages. The local display will be used to display the output and the error messages.

5.3.4.1 Local KeyboardThe following keys on the local keyboard can be used as user input to control the execution of the Diagnostic Software Scripts.

• PLAY key

• STOP key

• OPEN/CLOSE (EJECT) key

Unless otherwise specified, all references to keysmentioned in this document will be referring to the LOCAL FRONT PANEL keyboard.

5.3.4.2 Dealer Script

5.3.4.2.1 Set-up physical interface componentsHardware required:

• DVD playerThe DVD player is tested stand-alone: no otherequipment than the DVD player is needed.

5.3.4.2.2 ActivationThe dealer script is activated by pressing andholding dealer script activation keys on the localkeyboard of the DVD player simultaneously duringpower-on. The key used differs according to the model used. Refer to the [MRS_DSS] for details onthe keys used.

5.3.4.2.3 UsageThe test requires no user interaction. A number of nuclei will be run before a message is returnedindicating if there is a failure in the DVD player.During the execution of a script, a progress indicatoris displayed on the local display of the DVD player.

Busy_0 7

The counter at the right side of the display countsdown from the number of nuclei to be run to zero. A full description of the contents of the dealer script is given in document [SDD_DSS].At zero all nuclei from the script have been run andthe result (PASS/Error) is displayed on the localdisplay of the DVD player.

When the dealer script has been completed, the results are displayed in the following manner:

_PASS__

_ERROR_

5.3.4.2.4 TerminationTo turn off the dealer test, the DVD player must be powered down.

5.3.4.3 Player Script

5.3.4.3.1 Set-up physical interface componentsHardware needed:

• DVD player

• television set, connected to the DVD player

• 6 audio speakers

• an external video source

5.3.4.3.2 ActivationThe player script is activated by pressing andholding the player script activation keys on the localkeyboard of the DVD player simultaneously duringpower-on. The key used differs according to the model used. Refer to the [MRS_DSS] for details onthe keys used.

5.3.4.3.3 UsageThe player test requires human interaction to decidewhether the nuclei give correct output, e.g. the user needs to confirm the results of the display test. This


needs to be given through the local keyboard on the DVD player. The keys used for this purpose are described with each test.

Module test (with user interaction)During the first phase of the dealer test, the three main modules (Digital PWB, Display PWB and Basic Engine) are tested; some interaction from the user is required.

1. Testing the Display PWBThis not only involves testing the local display andkeyboard, but also testing the remote control and the leds. The display and local keyboard test are described here, for a description of the other testssee documents [SDD_DN] and [SDD_DSS].

At the beginning of the tests for the player script, the DSW version number will be indicated on the localdisplay of the DVD. The display will look like

Pressing the PLAY key will proceed to the front panel S/W version display which is shown on the local display of the DVD player. The display will looklike:

Press the PLAY key to proceed to the next test.

5.3.4.3.3.1 The Display TestDuring the display test, different patterns will be shown on the local display of the DVD player. For a specification of the patterns that will be shown on display, see document [SDD_DN] or [SDD_DSS].The user needs to step through these patternsusing the OPEN/CLOSE (EJECT) key on the localkeyboard. If any of the displayed patterns is incorrect, the user should press the STOP key toindicate that a fault was detected during this test. The test patterns on display will be repeated in a loop (stepped through using OPEN/CLOSE(EJECT) key) until the user presses PLAY key onthe local keyboard to proceed to the next test.

5.3.4.3.3.2 The LED TestNext is the LED test where the LEDs on the DVD player are lit. The LED test of a changer model is different from the LED test of a single disc model.

For a single disc model (non-changer):To indicate that a LED did not light up, the usermust press the STOP key. Pressing PLAY key willlet the user proceed to the next test.

For a changer model:Three test patterns on the LEDs will be repeated in a loop (stepped through using OPEN/CLOSE

(EJECT) key) until the user presses PLAY key onthe local keyboard to proceed to the next test. Toindicate that a LED did not light up, the user mustpress the STOP key.

During LED test the local display looks somethinglike this:

Ledtest

5.3.4.3.3.3 The Keyboard TestDuring the keyboard test, the user needs to pressall the keys on the local keyboard one by one. On the local display each key is represented by its scan code (a hexadecimal 2-digit code identifying the keyto the DVD player).Pressing a key will show its scan code on the local display of the DVD player. The first hexadecimaldigit identifies the key pressed. The second indicates how many times this particular key wasdetected. In case the key is pressed more than once, the scan code is displayed on each key press, with the second digit of its code increased eachtime. The display of scan codes scrolls from right to left, with the most recent scan code at the right. Thefollowing example gives a possible layout of the local display during the keyboard test:

D-7 :12:B Example for DVD760 model

D-7 :00:C Example for Q75 model

KB_:__:__K02:21:A3

SLV__2 :22To terminate the keyboard test, press the PLAY key on the local keyboard of the DVD player and hold it for 1 (one) full second. The keyboard test willterminate with a message on the local display. If the keyboard test was successful, you will see the following message:

KB-PASS

If the keyboard test was not successful, the following message will be displayed:

KB-FAIL

If the “KB-FAIL”- message is displayed, the playertest has failed. This is the end of the keyboard test. Press PLAY key on the local keyboard of the DVDplayer to proceed to the next test.

5.3.4.3.3.4 The remote control test For the remote control test, the user must press a key (any key) on the DVD’s remote control. The display at the start of the test looks as follows:

RC : :


When a remote control code has been received, its scan code is displayed as follows:

The PLAY key can be pressed to exit this test. However, if the user is required to test all keys on the remote control, (s)he can continue to press the remote control keys and these will all be displayedon the local display. With a code table at hand this test can be used to test the full functionality of the DVD’s remote control.

When the user has pressed PLAY key on the local keyboard (NOT on the remote control!), the result of the remote control test is shown on the local displayas follows:if successful,

if the test fails.

Pressing PLAY key on the local keyboard again willlet us proceed to the next test.

The P50 loop-back test (applies to models withdouble SCART connection)

For the P50 loop-back test, the user must first press a key to decide if he wants to perform the test. Thedisplay at the start of the test looks as follows:

If the user presses STOP key, then the P50 test willbe skipped. If the user presses OPEN/CLOSE(EJECT) key, the P50 test is performed and the result is displayed as follows:if successful,

if test fails.

Press PLAY key to continue.

2. Testing the Digital PWB moduleThe digital PWB is tested with a number of tests (for description of the tests, see [SDD_DSS]), among which are picture and sound tests. The picture tests involve putting a predefinedpicture on the connected television set, and asking

the user for confirmation. For a specification of the pictures, see document [SDD_DSS]. When the picture has been put on screen, the local displayasks for confirmation from the user by displaying the following message:R10:01 :23

APP :PIC1

If the user presses PLAY key, he confirms the test; pressing STOP key will indicate a fault in the test.The user can proceed to the next test by pressingPLAY key on the local keyboard of the DVD player.

Pressing the PLAY key on the local keyboard willstart the next test. A predefined sound will begenerated, and again the user is asked to confirmthis. At the same time, a colour bar pattern isgenerated at the video outputs to test the SCARToutputs. For a specification of the sounds, see document [SDD_DSS]. The local display looks as follows:RC-PASS

SCR :DVD_

RC-FAIL Pressing the PLAY key and OPEN/CLOSE (EJECT) key switches between [SCART DVD] and [SCARTLOOP]. Pressing the STOP key indicates test failure. For the 1st sound test, the scart loop-through [SCART LOOP] will be tested at the same time. Subsequent sound tests will be numbered in ascending order. Pressing and holding the PLAYkey for more than one second will start the next test. We have 2 sound test nuclei available now.

SCR:LOOP

P50-TEST The next nuclei tests the audio functionality of the module by generating a 1Khz sinusoidal signal andpassing it to the audio outputs. The display looks as follows:

APP:SND2

Pressing the STOP key on the local keyboard willstop and mute the audio output.P50-PASSPressing PLAY key on the local keyboard of the DVD player will take the user to the next test.

P50-FAIL 3. Testing the Basic EngineMost tests on the basic engine require userinteraction. When the basic engine tests are started, the version of the basic engine present in the DVD player is shown on the local display, as follows:

B07:09:00

The version number is displayed in decimalrepresentation (the colon ‘:’ replacing the dot). If the


version query fails on the basic engine, it will beshown as:

When the user presses PLAY key on the localkeyboard, the tests on the basic engine are started.

First, the tray operation is tested. The user can move the tray in and out by pressing the OPEN/CLOSE (EJECT) key on the local keyboard.The results need to be checked visually by the user, the software cannot detect any faults. The local display looks as follows:

For changer mechanisms (DVD795, YamahaC740/C940), when a tray OPEN operation is done, the DSW first rotates the carousel by one slot in the counterclockwise direction before opening the tray.This allows the user to conveniently load andunload discs from the tray. When loading discs,always place the disc at the upper left most slot in the tray.

Besides testing the tray, this test is also meant to give the user the opportunity to put a disc into the DVD player for subsequent basic engine tests.Some of the following tests need a DVD disc in the DVD player to operate properly. Always put a DVD disc into the DVD player during this test! At the end of the basic engine tests, there is an opportunity to remove it (before the loop tests start). Press the PLAY key on the local keyboard toproceed to the next test.

The second test is the sledge test. The user isasked to move the sledge by using the keysOPEN/CLOSE (EJECT) key on the local keyboard.This test needs to be checked visually by the user.The software cannot detect any faults. The localdisplay during this test looks as follows:

After pressing PLAY key on the local keyboard, the disc motor will be tested next. The local displaylooks as follows:

The user is required to listen if the disc motor is running. This must be confirmed by pressingOPEN/CLOSE (EJECT) key on the local keyboard.The STOP key is used to indicate that the discmotor is not running.

Pressing PLAY key on the local keyboard starts the focus test. The local display looks as follows duringthis test:

BE-FOCSBV-FAIL

By pressing OPEN/CLOSE (EJECT) key the user confirms successful focusing by the basic engine;pressing STOP key indicates a fault in the focusfunction.Pressing PLAY key on the local keyboard starts the radial function; the local display looks as follows:

BE-RADI

Again, pressing OPEN/CLOSE (EJECT) key confirms the result. STOP key indicates an error.After pressing PLAY key on the local keyboard, the grooves/jump test is started. As this is also a test that cannot be checked by the software, the user needs to perform a visual test. The local displaylooks as follows:

BE-TRAY

BE-GROO

By pressing OPEN/CLOSE (EJECT) key the nextgrooves/jump position is taken. Switching throughthe different positions is done in a cyclic manner.Press the PLAY key on the local keyboard toproceed to the last basic engine test, the tray test. This has been done at the beginning of the basic engine test but is repeated to enable the user to remove the disc in the tray before proceeding. Thelocal display will look as follows:

BE-TRAY

Press OPEN/CLOSE (EJECT) key to open the tray.Remove the disc in the tray.The tray will be closed automatically (if needed)before proceeding to the next tests (by pressingPLAY key on the local keyboard).

Read Error Log BE-SLED The contents of the error log will be displayed on

the local display, as follows1 :

E15:01:0A1

Note that this is an example only; no actualerrorcode is intendedBE-DISCThe first two characters on the local display (“E”)indicate that the read-out mode of the error log is activated. After the hyphen, 6 hexadecimal digits(one fault code) are displayed. To step through the different fault codes, the OPEN/CLOSE (EJECT) key on the local keyboard can be used. The displayof fault codes is cyclic. If the error log does notcontain any fault codes, all displayed error codeswill be “E00:00:00”.


Note: Fault codes are usually 8 hex digits in length.However, due to limitations in some of the displays,only the last 6 hex digits are displayed. This is still acceptable since all fault codes known so far have a value “00” in the first two digits.

To switch off the display of the error log, the PLAYkey must be pressed on the local keyboard.

Read Error BitsThe error bits are used to indicate that an erroroccurred once or more times. If an error has occurred, the bit representing the error is set. Toread out this field of error bits, the local display is used. Only the numbers of the errors where the bit is set will be displayed on the local display. The layout on the local display is as follows

2:

2 Note that this is an example only; no actual

errorbit is intended

The number of the set bits is displayed in a cyclicmanner. Scrolling through the set error bits can be done with the OPEN/CLOSE (EJECT) key. Pressing the PLAY key at the last bit number will display thefirst bit number again while pressing the STOP key button at the first bit number will display the last bit number in the list. The representation of bit numbers is decimal.If no error bits are set, the number on the right side of the display will be “00”

Module LooptestThe module loop test is an infinite loop in which a number of nuclei are executed over and over again.The nuclei run are the same as in the dealer test;user interaction is not required. During this loop test, the display looks as follows

3:

3Note that this is an example only; no actual

display-layout is intended.

The leftmost three digits indicate which of the DVD player’s modules is faulty; the explanation is in the following table:

Indication for each moduleModule Bit' Displayed

value Basic Engine Digital PWB Display PWB

000 OK OK OK

001 OK OK

010 OK OK

011 OK

OK OK

OK

OK

After the hyphen the (decimal) number indicates the number of times the loop test was performed.The right side of the display shows an error codeDNER (in decimal representation), which is built from a nucleus number (DN) and an error number(ER). This code indicates the last nucleus thatreturned an error code. For explanation of thisDNER code, see document [SDD_DN].

The loop test will run indefinitely until it is terminated, which is done by switching off the powerto the DVD player.End result of the player test is equal to the lastdisplay shown above. It shows which module is faulty and which nucleus caused the last error, as well as how many loops were performed.

EB-___0A

5.3.4.3.4 TerminationTo terminate the player test, switch off AC power to the DVD player/module.

5.3.5 External ScriptsA script is a sequence of nucleus calls. Internal scripts (e.g. scripts built into the diagnostic softwareitself) are in the form of a C-language module.However the customer cannot be expected to writeC-modules in order to create new scripts.The scripts that can be made externally are therefore in one of the following two forms:

1. A Procomm or Telex scriptProcomm or Telex can be used to write diagnosticscripts. The script language of both communicationpackages contains possibilities for construction of loops and branches in the scripts. Commands sent will be exactly the same as described in the chapter“Command Interface”. The diagnostic software (the engine) will receive normal RS232 commands and processes these as defined, sending results ofthese nuclei back over the RS232 line. In theTerminal the Procomm or Telex script determineswhich command sequence is followed

Display the 3-digit modulebits together with thecurrent loop count.010 23After one loop cycle: Displaythe 3-digit module bitstogether with the last errorcode which occurred in the loop test for 1sec.

010:54032. An Asterix-script

Asterix-scripts are C-programs in which commandsare sent to the diagnostic software (the engine). Theconstruction of branches and loops is again locatedin the remote machine, i.e. the Asterix machine.Commands sent will be exactly the same as described in the chapter “Command Interface”. Thediagnostic software (the engine) will receive normal RS232 commands and processes these as defined,sending results of the called nuclei back over the RS232 line. In the Asterix PC the C-programdetermines which command sequence is followed.

5.3.6 Layout of menus and submenus for the ServiceTerminalNOTE: a symbol “...” in the next menu layoutsindicates that that specific menu choice will invokethe display of a submenu. This symbol will also be used in the implementation of the menus (i.e. the “...” will also appear in the user interface). The list is


exhaustive and is accurate as of version 7.00 S. Actual versions encountered could be slightlydifferent.

5.3.6.1 Main Menu

5.3.6.2 First Level Submenus

For single-disc, I2C master modules only

For disc changer, I2C master modules only

For SACD players/modules only

MAIN > FURORE MENU

1. SDRAM Write/Read [63]2. SDRAM Write/Read Fast [64]3. Chip Revision ID [65]4. Set Output High [84a]5. Set Output Low [84b]4. Reset Furore IC [83]

MAIN MENU 1. Audio... 2. Video... 3. Front Panel...4. Basic Engine... 5. Processor Peripherals...6. Error Log... 7. Miscellaneous...

MAIN > MISCELLANEOUS MENU

1. Statistics Info...2. Read DVD Application version [46]

5.3.6.3 Second level submenus

MAIN > AUDIO MENU1. Mute... 2. Pink Noise... 3. Sine Wave... 4. Digital Ports... 5. Ext. DAC Board...

MAIN > AUDIO > MUTE MENU

1. Mute On [19a]2. Mute Off [19b]

MAIN > VIDEO MENU1. Colourbar...

2. Scart... 3. Digital Port...

MAIN > AUDIO > PINK NOISE MENU

1. Pink Noise On [20a]2. Pink Noise Off [20b]

MAIN > FRONT PANEL MENU 1. Slave Processor... 2. VFT Display [30a]3. LCD Display [30b]4. LCD BkLight [30c]5. Keyboard [27]6. LEDs [29] 7. Remote Control [28] 8. P50 Check [60]

MAIN > AUDIO > SINE WAVE MENU

1. Audio Sine On [21a]2. Audio Burst On [21b]

For SACD modules/players only

MAIN > AUDIO > EXT DAC BOARD MENU

1. DAC Reset [79] 2. I2C Test... 3. Clock... 4. Audio... 5. Low Power Standby...6. DAC Mode...

MAIN > FRONT PANEL MENU 1. Slave Processor... 2. VFT Display [30a]3. LCD Display [30b]4. LCD BkLight [30c]5. Keyboard [27]6. LEDs... 7. Remote Control [28] 8. P50 Check [60]

MAIN > VIDEO > COLOURBAR MENU

1. Colourbar DENC On (PAL) [23a]2. Colourbar DENC On (NTSC) [23c]3. Colourbar DENC/MPEG Off [23b]4. Progressive Scan [24c]5. Set Video Out To RGB [61a]6. Set Video Out To YUV [61b]

MAIN > BASIC ENGINE MENU1. Reset [44] 2. Version [37] 3. Communications... 4. Loader Mechanism...5. Special Diagnostics...

MAIN > PROCESSOR PERIPHERALS MENU

1. Clock... 2. Flash... 3. NVRAM... 4. Processor Info [5] 5. Slave IIC Loopback Test [90]

MAIN > VIDEO > SCART MENU

1. I2C Scart IC Check [54]2. Scart To DVD [55a]3. Scart Pass Through [55b]4. Scart Pin 8 Low (0 to 2)V [25a]5. Scart Pin 8 Mid (4.5 to 7)V [25b]6. Scart Pin 8 Hi (9.5 to 12)V [25c]

MAIN > ERROR LOG MENU

1. Read Last Errors [31]2. Read Error Bits [32]3. Reset Error Log [33]For SACD players/modules only

MAIN > VIDEO > DIGITAL PORT MENU

1. Video Port Out 0xAA [17a] 2. Video Port Out 0x55 [17b]


For I2C master modules only


For single-disc modules only



For NON-SACD players/modules only

MAIN > PROCESSOR PERIPHERALS > NVRAM MENU

1. I2C NVRAM access [11]2. NVRAM Config [34]3. NVRAM Reset [35]4. NVRAM Modify [36]5. NVRAM Read/Wr Test [15]

MAIN > FRONT PANEL > SLAVE PROCESSOR MENU

1. Bus Comms Check [12] 2. S/W Version [26]

MAIN > MISCELLANEOUS > STATISTICS INFO MENU

1. Total Nr Of Times Tray Open [47a]2. Total Time Power On [47b]3. Total Play-Time CDDA & VCD [47c]4. Total Play-Time DVD [47d]

MAIN > FRONT PANEL > LEDS MENU

1. Test Front Panel LEDs [29] 2. I2C comm check IO Expander [29a]

MAIN > BASIC ENGINE > COMMUNICATIONS MENU

1. ATAPI/UDE Echo [13] 2. UDE Pass-Through [14] 3.6.4 Third level submenus


MAIN > AUDIO > EXT DAC BOARD > I2C TEST MENU

1. I2C Test [66a]2. I2C Enable Pin On [66b]3. I2C Enable Pin Off [66c]

MAIN > BASIC ENGINE > MECHANISM MENU

1. Disc Motor... 2. Laser... 3. Tray...4. Focus... 5. Radial... 6. Sledge... 7. Grooves...


MAIN > AUDIO > EXT DAC BOARD > CLOCK MENU

1. Clock Internal [67a]2. Clock External [67b]3. Clock Upsampling 192k (963 only) [82a] 4. Clock Upsampling 96k (963 only) [82b]5. Clock Upsampling On (963 only) [82c]6. Clock Upsampling Off (963 only) [82d]

MAIN > BASIC ENGINE > MECHANISM MENU

1. Disc Motor... 2. Laser... 3. Changer Mechanism...4. Focus... 5. Radial... 6. Sledge... 7. Grooves...


MAIN > AUDIO > EXT DAC BOARD > AUDIO

1. Audio Pre-Mute On [68a]2. Audio Pre-Mute Off [68b]3. Audio Center On [69a]4. Audio Center Off [69b

MAIN > BASIC ENGINE > SPECIAL DIAGNOSTICS MENU

1. Read FlashID [70]2. ROM Checksum [71]3. Scratch Detector Test [72]


MAIN > AUDIO > EXT DAC BOARD > LOW POWERSTANDBY

1. Low Power Standby On [81a]2 Low Power Standby Off [81b]

MAIN > PROCESSOR PERIPHERALS > PCM CLOCK MENU

1. Ext PCM_CLK In CDDA Mode (11.3MHz) [7a]2. Ext PCM_CLK In DVD Mode (12.3MHz) [7b]3. Ext PCM_CLK In DVD96kHz Mode (24.6MHz) [7c] For SACD players/modules only

MAIN > AUDIO > EXT DAC BOARD > DAC MODE MENU

1. DAC CDDA Mode [80a]2. DAC DVD48 Mode [80b] 3. DAC DVD96 Mode [80c] 4. DAC DSD Mode [80d]

MAIN > PROCESSOR PERIPHERALS > PCM CLOCK MENU

1. Int PCM_CLK In CDDA Mode (11.3MHz) [8a]2. Int PCM_CLK In DVD Mode (12.3MHz) [8b]3. Int PCM_CLK In DVD96kHz Mode (24.6MHz) [8c]

MAIN > BASIC ENGINE > MECHANISM > DISC MOTOR MENU

1. Disc Motor On [39a]2. Disc Motor Off [39b]

MAIN > PROCESSOR PERIPHERALS > FLASH MENU 1. Verify FLASH Checksum [6]2. Show FLASH Checksum [62]3. Flash Write Access [10]


For single-disc players/modules only

For disc changer players/modules only

5.3.6.5 Screen layout with menusWhen menus are used, no specific screen layoutcan be given. Menu information will not be in a special format, except for the layout as mentioned in the previous paragraphs.A typical menu session can look as follows for a changer player’s diagnostics:

---------------<top of screen>---------------------------------

MAIN > BASIC ENGINE > MECHANISM > LASER MENU

1. CD Laser On [58a]2. CD Laser Off [58b]3. DVD Laser On [58c]4 DVD Laser Off [58d]

3. Front Panel...4. Basic Engine...5. Processor Peripherals...6. Error Log...7. Miscellaneous...

Select> 4 <enter>

MAIN > BASIC ENGINE MENU

1. Reset [44]2. Version [37]3. Communications...4. Loader Mechanism...5. Special Diagnostics...

Press Enter to go to Main Menu.

Select> 5 <enter>

MAIN > BASIC ENGINE > SPECIAL DIAGNOSTICS MENU

1. Read FlashID [70]2. ROM Checksum [71]3. Scratch Circuit [72]

Press Enter to go to Main Menu.

Select> 1 <enter>

MAIN > BASIC ENGINE > MECHANISM > TRAY MENU

1. Tray Open [43b]2. Tray Close [43a]

MAIN > BASIC ENGINE > MECHANISM > CHANGER MENU

1. Initialize [91a]2. Tray Open [91b]3. Tray Close [91c]4. Disc Clamp Down [91d]5. Disc Clamp Up [91e]6. Rotate CW <n> times [92a]7. Rotate CCW <n> times [92b]8. IO Expander I2C Comm [92c]

------------------<bottom of screen>-------------------------MAIN > BASIC ENGINE > MECHANISM > FOCUS MENU

1. Focus On [38a] (load DVD first)2. Focus Off [38b]

Depending on the height of the screen, the text willstart scrolling off the top of the screen.

MAIN > BASIC ENGINE > MECHANISM > RADIAL MENU

1. Radial Control On [40a] (load DVD first)2. Radial Control Off [40b]

5.3.6.6 Layout of Results diagnostic nuclei on control/service PC Results returned from a Diagnostic Nucleus to the control/service PC will have a maximum length of 300 characters and are terminated by a ‘@’ and CR character (included in the string length)MAIN > BASIC ENGINE > MECHANISM > SLEDGE MENU

1. Sledge Inwards [41a] 2. Sledge Outwards [41b] The result has the following layout:

<additional information><CR><number><string> [OK | ER] @<CR>

MAIN > BASIC ENGINE > MECHANISM > GROOVES (UsesDVD) MENU 1. Jump To Inside Grooves [42a]2. Jump To Middle Grooves [42b]3. Jump To Outside Grooves [42c]

The use of the “@” enables the Asterix system on the Control PC to parse the output string of each nucleus into a database.

<additional information> are strings which contain a number information which was produced during the execution of the test nuclei. These includechecksum values, progress indicators, etc.

<number> is a 4-digit decimal number padded withleading zeros if its value is less than 4 digits. Thefirst two digits identify the generating nucleus (or group of nuclei) while the latter two digits indicatethe error number.

<string> is a text string containing information aboutthe result of the Diagnostic Nucleus.DVDv6 Diagnostic Software version 7.00 B

Slave Processor: SLAVE2

(M)enu, or (C)ommand? [M]:@ <enter>

Press ENTER to go to main menu.

CC:> <enter>

MAIN MENU

1. Audio...2. Video...

<number> and <string> are defined in [SDD_DN] in the output sections of each Nucleus.

Examples:1. 0001 Unknown command ER @2. 3100 OK @ 3. 0901 Data line X is not connected to the DRAM ER @4. Device ID: 0x01Manufac ID: 0xC27000 OK @

EN 4325MSD-512SBlock and wiring diagrams

6. Block and wring diagram 6. Block and wring diagram 6.1 BLock diagram MSD-512S

ELINK connectorGND 1 2 +5VMEDUSACSn 3 4 +5VALE 5 6 SYSRSTnUPA2 7 8 UPA3UPD15 9 10 UPA1UPD13 11 12 UPD14UPD11 13 14 UPD12UPD9 15 16 UPD10UPD8 17 18 GNDUPD6 19 20 UPD7UPD4 21 22 UPD5UPD2 23 24 UPD3

UPA [1:3 ] UPD0 25 26 UPD1UPD [0:15 ] MEDUSAINTn 27 28 DTACKn

ALE LDS 29 30 UDSLDS R/W 31 32 GNDUDS

SYSRSTnDTACKn

MEDUSAINTnMEDUSACSn

R/W

ClockCircuitMA [0:11 ]

BA [0:1 ] SDRAM interfaceMD [0:31 ]MCS0nMRASnMCASn MCS1nMWEnMCLK

MDQM [0:3 ] SYSRSTn

MT48LC2M32B2TG-7-TR

512K x 32 x 4

MT48LC4M32B2TG-7

1M x 32 x 4

GPIO I2C I2C A nalo g Di g ital A udio I2S Service and JTAG bus(misc ) Master Slave video audio XCLK dia g nostic p ort RSTGPIO SCL SCL VDAC [0:4 ] SPDIF BCLK RTS1 TDOIR SD A SD A LRCLK RXD1 TDI

ADATA0 TXD1 TMSCTS1 TCKModule interface bus

SCLSD A

NVRAM64K bits

SDRAM DECODER IC

LSI LogicZiva5

1M x 16 M29W160

Flash

2M x 16 M29W320TSOP48

UPA [1:22 ]UPD [0:15 ]SYSRSTnUDS

FLASHCSn

Trans parent latch74HCT57374HCT57374HCT573

UPA [1:3 ]UPD [0:15 ]

ALE

Host interface

ATAPI connectorHRST 1 2 GNDHD (15 ) 3 4 HD(0)HD (14 ) 5 6 HD(1)HD (13 ) 7 8 HD(2)HD (12 ) 9 1 0 HD(3)HD (11 ) 11 12 HD (4)HD (10 ) 13 14 HD (5)HD (9) 15 16 HD (6)HD (8) 17 18 HD (7)GND 19 20DMARQ 21 22 GNDLDS 23 24 GND

UPA [1:3 ] UDS 25 26 GNDUPD [0:15 ] DTACKn 27 28DTACKn DMACK 29 30 GNDLDS HIRQ1 31 32UDS UPA2 33 34

HDMAC K UPA1 35 36 UPA3HDMARQ IDECS0 37 38 IDECS1LDRST 39 40 GND

IDECS [0:1 ]HCSn [3:4 ]HIRQ1

ATAPI

LOADERA97ST

ATAPIConnector

ELINKConnector

ResetCircuit

Audio DACAK4382

Analog Audio output

MPEG BOARD

EN 4326MSD-512SBlock and wiring diagrams

6. Block and wring diagram 6. Block and wring diagram 6.2 Wiring diagram MSD-512S

1601 1620E-link

1600 VFD driver 1615

1611

1603

1610 Power

1620

1621

1608Lt/Rt/CVBS/COAX con

1606SCART connector

1618

8001

8003

8004

8002

Lt/Rt

SPDIF

I2C

ATAPI

ServicePSU

1615

RGBY/C

1619

For /00 stroke version:8001 3104 311 06311 CBLE HR 3P4/340/3P HR WH8002 3104 311 06301 CBLE HR 7P/340+220/3P+4P HR BK8003 3139 131 01841 CBLE HR-BK 3P/140/3P HR-BK8004 3139 131 03151 CBLE HR 03P/180/03P HR (BRAIDED) 8005 3139 131 02841 CBLE HR-BK 06P/600/08P HR-BK8006 3141 010 21592 CWAS 40RK/40RK 400 SHIELD 28S

For /69 stroke version:8001 3139 131 02691 CBLE HR 04P/400/03P HR 8002 3139 131 02612 CBLE HR 06P/480/04P HR FERR 8003 3139 131 02321 CBLE HR-BK 3P/400/3P HR-BK 26OS BK 8004 3139 131 03151 CBLE HR 03P/180/03P HR (BRAIDED) 8005 3139 131 02841 CBLE HR-BK 06P/600/08P HR-BK8006 3141 010 21592 CWAS 40RK/40RK 400 SHIELD 28SFor /78 stroke version:8006 3141 010 21901 CWAS 40RK/40RK 400 28SFor /ARG stroke version:8006 3141 010 21901 CWAS 40RK/40RK 400 28S

LOADERA97ST

8006

From Power Supply

JTAG

MPEG SD5.12

8005

EN 4427MSD-512SElectrical Diagrams and Print-layouts

Electrical Diagrams MPEG Board SD5.12

M 1 Decoder & Peripheral Circuits

1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 8

A

B

C

F

E

D

F

E

D

C

B

A

DAI_DATA157

DAI_BCK/SYSCLKBP158

DAI_LRCK/IEC958BP159

12C_CL160

12C_DA161

RTS1162

RXD1163

TXD1164

CTS1165

GNDP166

VDDP167

SDDATA7168

SDDATA6169

SDDATA5170

SDDATA4171

GND172

VDD173

SDDATA3174

SDDATA2175

SDDATA1176

SDDATA0177

SDREQ178

SDEN179

GNDP180

VDDP181

SDERROR182

SDCLK183

VSYNC/HIRQ1184

RTS2185

RXD2186

TXD2187

CTS2188

VNW189

ALE190

HCS4191

HCS3192

HCS2193

HCS1194

HCS0195

VDDP196

TRST197TDO198TDI199

TMS200

TCK201

RESET202

BUSCLK203

GND204

VDD205

HA3206

HA2207

GNDP208

VDD25 55MCLK 56MD0 57MD1 58MD2 59MD3 60GND25 61MDQM0 62VDD25 63MD4 64MD5 65MD6 66MD7 67MD8 68MD9 69MD10 70MD11 71GND25 72MDQM1 73VDD25 74MD12 75MD13 76MD14 77MD15 78GND 79VDD 80MD16 81MD17 82MD18 83MD19 84GND25 85MDQM2 86VDD25 87MD20 88MD21 89MD22 90MD23 91MD24 92MD25 93MD26 94MD27 95GND25 96MDQM3 97VDD25 98MD28 99MD29 100MD30 101MD31 102GND25 103VDD25 104

VCLK

105

VDATA7

106

VDATA6

107

VDATA5

108

VDATA4

109

VDATA3

110

VDDP

111

GNDP

112

VDATA2

113

VDATA1

114

VDATA0

115

HSYNC/IRQ2

116

VDAC_4B

117

VDAC_VDD4

118

VDAC_4

119

VDAC_3B

120

VDAC_VDD3

121

VDAC_3

122

VDAC_2B

123

VDAV_VDD2

124

VDAC_2

125

VDAC_1B

126

VDAC_VDD1

127

VDAC_1

128

VDAC_0B

129

VDAC_VDD0

130

VDAC_0

131

VDAC_DVSS

132

VDAC_DVDD

133

VDAC_RefVDD

134

VDAC_Ref

135

VDAC_RefVSS

136

XVSS

137

XOUT

138

XIN/VCLK216BP

139

XVDD

140

AVSS2

141

AVDD2

142

AVDD1

143

AVSS1

144

VDD

145

GND

146

XCK

147

LRCK

148

BCK

149

ADATA0

150

ADATA1

151

VDDP

152

GNDP

153

ADATA2

154

ADATA3

155

IEC958

156

GND25 54

MWE 53

VDDP

1

HA1

2

HD14

4HD15

3

HD13

5

HD12

6

HD11

7

HD10

8

HD9

9

HD8

10

HD7

11

VDDP

12

GNDP

13

HD6

14

HD5

15

HD4

16

HD3

17

HD2

18

HD1

19

VDDP

20

GNDP

21

HD0

22

HDTACK

23

HIRQ0

24

HUDS

25

HREAD

27HLDS

26

IRRX1

28

GND

29

VDD

30

GND25

31

VDD25

32

MA9

33

MA7

35

MA6

36

MA8

34

MA5

37

MA4

38

MA3

39

MA2

40

MA1

41

MA0

42

GND25

43

VDD25

44

MA10

45

MA11

46

BA1

47

BA0

48

MCS0

49

MCS1

50

MRAS

51

MCAS

52

7600

ZIVA5

OC 1CLK 11

1D 2

2D 3

3D 4

4D 5

5D 6

6D 7

7D 8

8D 9

1Q19

2Q18

3Q17

4Q16

5Q15

6Q14

7Q13

8Q12

GND 10

VCC207607

74LVT573DB

OC 1CLK 11

1D 2

2D 3

3D 4

4D 5

5D 6

6D 7

7D 8

8D 9

1Q19

2Q18

3Q17

4Q16

5Q15

6Q14

7Q13

8Q12

GND 10

VCC207606

74LVT573DB

UPA4UPA5UPA6UPA7UPA8UPA9UPA10UPA11

UPD0UPD1UPD2UPD3UPD4UPD5UPD6UPD7

UPA12UPA13UPA14UPA15UPA16UPA17UPA18UPA19


UPA3

UPA2

UPA1

UPD15

UPD14

UPD13

UPD12

UPD11

UPD10

UPD9

UPD8

UPD7

UPD6

UPD5

UPD4

UPD3

UPD2

UPD1

UPD0

/DTACK

/MEDINT

UDS

LDS

R/W

IR

3658 33R3659 33R

3653 33R

MADDR9

MADDR8

MADDR7

MADDR6

MADDR5

MADDR4

MADDR3

MADDR2

MADDR1

MADDR0

MADDR10

BA1BA0/MCS0/MRAS/MCAS

/MWE

/SD_CLKMDATA0MDATA1MDATA2MDATA3

MDATA4MDATA5MDATA6MDATA7MDATA8MDATA9MDATA10MDATA11

MDATA12MDATA13MDATA14MDATA15




MDQM3

MDQM2

MDQM1

MDQM0

VID_COMP

VID_C

VID_Y

VID_U

VID_V

GNDA

V3V3

3650

1K/1%

REF_3V3

PLL_3V3DA_XCKDA_LRCKDA_BCKDA_DATA0

IEC958

SCART0

/SYS_RST

/MEDUSA_CS

/FLASH_CS

/IDE_CS1

5VD

GNDD

ALE

ALE

3652 4.7K3651 4.7KF3V3

UPA[21..1]

HIRQ1

/IDE_CS0

SCART1

OC 1CLK 11

1D 22D 3

3D 4

4D 5

5D 6

6D 7

7D 8

8D 9

1Q192Q18

3Q17

4Q16

5Q15

6Q14

7Q13

8Q12

GND 10

VCC207605

74LVT573DB

UPA20 UPA1

3724

33R

3725

33R

MADDR11

/LDRSTRxD_SERTxD_SER

S_I2C_RDY

UPA2UPA21

F3V3

2602

100n

2603

100n

2604

100nGNDD

GNDD

GNDD

3630

4k7

3629

4k7

3628

4k7

3627

4k7

3626

4k7

3615 33R3616 33R3617 33R3618 33R

2608

22p

2607

22p

2606

22p

2605

22p

GNDDGNDD

SERVICE

36334k7

2614100n

GNDD

REF_GND

5601

13.5MHz

PLL_GND

2617 3p

26183p

1V83V3

GNDD

D3V3

DGND

3V3

3V3

3V3

3V3 3V3 3V3

3V3

3V3

3V3

3V3

3V3

3V3

3V3

1V8

1V8

1V8

1V8 3V3

GNDD

GNDD

GNDD

GNDD

GNDD

GNDD

GNDD

GNDD

GNDD

GNDD

GNDD

GNDD

GNDD

E01

E12

E23

VSS4 SDA 5

SCL 6

/WC 7

VCC 8

7602M24C64-WMN6T

3611

4k7

3613

4k7

3603

0R

3604

0R5VD3V3

2613

100n

GNDD

M_I2C_CL

M_I2C_DA

1234567

1600

PH-7P

7603BC847B

7604

BC847B

3640

100R

3638

4k7

3679 1k

3635

4k7

3642

10k3644

10k

3643

6k8

2601

1n5

GNDD

GNDDGNDD

5VD

3V3SERVICE

5600

FB

5VD

TxD_SER

RxD_SER3641

10k

GNDD

HIRQ1

364510k

5VD

GNDD

DMARQ

DMACK

3634

4k7

5VD

3V3

3631 68R

363268R

363710k

5VD

3649 33R

2625100n

2626100n

2627100n

2628100n

2629100n

2630100n

2631100n

2632100n

2633100n

2634100n

2635100n

2636100n

2637100n

2638100n

2639100n

2640100n

3V3

GNDD

2619100n

2620100n

2621100n

2622100n

2623100n

2624100n

2641100n

2642100n

2643100n

2644100n

GNDA

V3V3 PLL_3V3

PLL_GND

GNDD

1V8

2612

22p

/LDRST

36854k7

3686

4k7

5VD

GNDD

VFD_DATA

VFD_CLK

VFD_CS

DAC_CS

DAC_CLK

DAC_DATA

2645100n

5VD

TRSTTDO

TMSTCK

3881

33R

3882

33R

3883

33R MUTE

3636A 33R

3636B 33R

3636C 33R

3660A

33R

3660B

33R

3660C

33R

3660D

33R

3661A

33R

3661B

33R

3661C

33R

3661D

33R

3662A

33R

3662B

33R

3662C

33R

3662D

33R

3663A

33R

3663B

33R

3663C

33R

3663D

33R

3664A

33R

3664B

33R

3664C

33R

3664D

33R

3665A

33R

3665B

33R

3665C

33R

3665D

33R

3666A

33R

3666B

33R

3666C

33R

3666D

33R

3667A

33R

3667B

33R

3667C

33R

3667D

33R

3668A

33R

3668B 33R3668C 33R3668D 33R

123456

1611

PH-6P GNDD

3648 33R

TP1

TP3

TP4

TP5

TP6

TP7

TP8TP9TP10TP11TP12TP13

TP14TP15

TP16

TP19

TP24

3669

180R/1%

M_I2C_CLM_I2C_DA

S_I2C_CLS_I2C_DA

3911

0R

3912

0R

39134k7

3914

4k75VD

16001611260126022603260426052606260726082612261326142617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264536033604361136133615361636173618362636273628362936303631363236333634363536363637363836403641364236433644364536483649365036513652365336583659366036613662366336643665

3666366736683669367936853686372437253881388238833911391239133914560056017600760276037604760576067607

B1B1

B1

B1B1

B1

B1

C1

C1

C1

C1C1C1C1

C1

D1

D1E1

E1F1

F1

A2

A2A2A2A2

B2B2

B2B2B2B2B2

B2

C2

C2

C2

C2C2C2

D2

D2

E2

F2F2

B3B3B3B3B3B3B3

C3C3C3D3

D4

E3

F3F3F3F3A4A4A4A4A4

A4A4

A4

F4F4

F4F4F4F4

A5A5A5A5A5A5

A5

A5

F5F5

F5F5

F5

A6A6A6

A6A6A6A6A6A6A6A7A7A7

C5

F6E6

E6E6

E7



M 2 Memory Part

1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 8

A

B

C

F

E

D

F

E

D

C

B

AUPA1UPA2UPA3UPA4UPA5UPA6UPA7UPA8UPA9UPA10UPA11UPA12UPA13UPA14UPA15UPA16UPA17UPA18UPA19UPA20

UPA213694 0R

3692 47R

3696 0R

F3V3

12V

GNDD

UPD0UPD1UPD2UPD3UPD4UPD5UPD6UPD7UPD8UPD9UPD10UPD11UPD12UPD13UPD14UPD15

/FLASH_CSR/WUDS/SYS_RST

GNDD

GNDD

F3V3

3701

10k

3700

10k

36984k7

3699

1k

3V3

/SYS_RST

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

1601

HEADER 20X2

/LDRST


UPD0UPD1UPD2UPD3UPD4UPD5UPD6

LDSUDS/DTACK

HIRQ1

UPA1/IDE_CS0

UPD7

UPA3UPA2

/IDE_CS1

1

2

3

4

5

6

1605

EH-6P

STDY_CTRL

VFD_DATA

VFD_CLK

VFD_CS

IR

MADDR0MADDR1MADDR2MADDR3MADDR4MADDR5MADDR6MADDR7MADDR8MADDR9MADDR10MADDR11

BA0BA1

MDQM0

MDQM1MDQM2

MDQM3

/MCS0

/MWE

/MRAS/MCAS

/SD_CLK

GNDD

3704

10k

SD3V3


MDATA8MDATA9MDATA10MDATA11MDATA12MDATA13MDATA14MDATA15MDATA16MDATA17MDATA18MDATA19MDATA20MDATA21MDATA22MDATA23


GNDD GNDD

SD3V3

GNDD

/MCS0

GNDD

6604

BAS316

GNDD

GNDD

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 32

1602

HEADER-32P

/MEDUSA_CSALE

UPA1UPA2 UPA3

UPD0 UPD1UPD2 UPD3UPD4 UPD5UPD6 UPD7UPD8UPD9 UPD10UPD11 UPD12UPD13 UPD14UPD15

/MEDINTLDSR/W

UDS/DTACK

GNDD

5VD

GNDD

GNDD

/SYS_RST

GNDD

A025

A126

A227

A360

A461

A562

A663

A764

A865

A966

A1024

A1121

BA022

BA123

DQM016

DQM171

DQM228

DQM359

/CS20

/WE17

/CAS18

/RAS19

CKE67

CLK68

NC14

NC30

NC57

NC69

NC70

NC73

VSS

86

VSS

72

VSS

58

VSS

44

VSSQ

84

VSSQ

6

VSSQ

78

VSSQ

12

VSSQ

32

VSSQ

52

VSSQ

38

VSSQ

46

DQ0 2

DQ1 4

DQ2 5

DQ3 7

DQ4 8

DQ5 10

DQ6 11

DQ7 13

DQ8 74

DQ9 76

DQ10 77

DQ11 79

DQ12 80

DQ13 82

DQ14 83

DQ15 85

DQ16 31

DQ17 33

DQ18 34

DQ19 36

DQ20 37

DQ21 39

DQ22 40

DQ23 42

DQ24 45

DQ25 47

DQ26 48

DQ27 50

DQ28 51

DQ29 53

DQ30 54

DQ31 56

VDD

1

VDD

15

VDD

29

VDD

43

VDDQ

3

VDDQ

81

VDDQ

9

VDDQ

75

VDDQ

55

VDDQ

35

VDDQ

49

VDDQ

41

7611

MT48LC2M32B2TG-7

A025

A124

A223A322A421

A520

A619

A718

A88

A97

A106

A115

A124

A133

A142

A151

A1648

A1717

A1816

A199

/CE26

/OE28

/WE11

/RST12

/BYTE47

VSS1

27

VSS2

46

DQ0 29

DQ1 31

DQ2 33DQ3 35DQ4 38

DQ5 40

DQ6 42

DQ7 44

DQ8 30

DQ9 32

DQ10 34

DQ11 36

DQ12 39

DQ13 41

DQ14 43

DQ15/A-1 45

RY/BY 15

NC/A20 10

NC3 13

NC4 14

VCC

37

7610

M29W160DT-70N1

5660 FB

5661 FB

5662 FB

5663 FB

5664 FB

2661

100n

2665

100n

2662

100n

2664100n

2669 100n

2670 100n

2671 100n

2672 100n

2673 100n 2676 100n

2677 100n

2678 100n

2679 100n

2680 100n

2690100p

2694100p

2681 22p

268322p

269122p

269222p

269322p

266710p

266810p

266347U/10V

7612

BC847B

5621 FB5622 FB5623 FB5624 FB5625 FB5626 FB5627 FB5628 FB5629 FB

5631 FB5632 FB5633 FB

5635 FB5636 FB5637 FB5638 FB

5648 FB5647 FB5646 FB5645 FB5644 FB5643 FB5642 FB5641 FB

5640 FB5651 FB

5711 FBM_I2C_CLS_CL_O

S_DA_OM_I2C_DA

S_I2C_RDY

5712 FB

5713 FB5714 FB

2833 22p

5772 FB

1

2

3

4

1603

EH-4P

TP25

TP26

TP27

TP28

TP29

TP30

TP31

TP32

TP33

TP34

5630 FB

5634 FB

DMARQ

DMACK

2609

100n

3902

39030R

3904

3905

GNDD

5VD

3906100R

3907100R

3606

3608

S_I2C_CL

S_I2C_DA

3799

5k6

38005k6

7608 BSN20

7609 BSN20

3915

0R3916 3917

5VD

3V3

GNDD

3918

3919

2002-07-12Lt

Rt

2849 22p

2839 22p

5617 0R

5618 0R

GNDA

1

2

3

1621

EH-3P

1

2

3

1610

EH-3P

3654

0R2895 22p

2896 22p

5VD

GNDD

TP57

TP58

TP59

TP60

TP61

TP62

3655

0R-12VA

160116021603160516101621260926612662266326642665266726682669267026712672267326762677267826792680268126832690269126922693269428332839284928952896360636083654365536923694369636983699370037013704379938003902390339043905390639073915391639173918391956175618562156225623562456255626562756285629563056315632563356345635563656375638

5640564156425643564456455646564756485651566056615662566356645711571257135714

76087609761076117612

A2

A2

A4A4A4A4A4A4A4A4A4A4

A6

A6

B1B2B2

B2

B5

B5

B6

B6B6B6B6

B6B6B6B6B6

C1C1C1

C1

C2

C3C3

C3

C1

C5C5

C5

C5

C6

C6C6C6C6

5772 C66604

C7C7

C7

C7

D1

D1D1

D1

D2

D2

D3

D3

D6D6D6

D6

D6

D7

E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1

E2E3E3E3E3E3E3E3E3

E4

E4

E6E6

E6

E6E6

E6

E7

F1F1

F3

F3F5

B4



M 3 Audio Part

1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 8

A

B

C

F

E

D

F

E

D

C

B

A

DAC_CSDAC_CLKDAC_DATA

DA_XCKDA_LRCKDA_BCKDA_DATA0

2723

47u

3737

4k7 GNDA

GNDA

5VA

5VA

3

21

84

7626A

LM833D

5

67

7626BLM833D

27703n3

3734

4k7 1%

3776

4k7 1%

37775k1 1%

3780

200R 1%

3778

200R 1% 3779

5k1 1%

3766 470R

3763 470R

2769470p

2767

100n2766

390p

2768

100n

GNDAGNDA-12VA

+12VA_1

GNDA

2760

100u

2761

100u

37652k7

3764

2k7

3767100k

3762100k

2756680p

GNDA

GNDA

3741

4k7

3752

4k7

37531k

37576k8

3754

1k

277147u

GNDA

7630BC857B

3758

2k2

37590R

2762100u

GNDA

7629BC857B

GNDA

5VA

+12VA

MUTE

MUTEC

3750

330R

3748

100R

3747

22R5VD

GNDD

375191R

IEC958

SPDIF

27653n3

3771

4k7 1%

3775

4k7 1%

37745k1 1%

3773

200R 1%

3772

200R 1% 3770

5k1 1%

2764470p

2763

390p

GNDA

Lt_OUT

MUTEC

GNDA

GNDA

3784

5k1 1%

2752

100n

2757

100n

2755680p

2 4

5

1

3

7624

74HCT1G125

CSN6

CCLK7

CDTI8

MCLK1

LRCK4

BICK2

SDTI3

DZFL 16

DZFR 15

AOUTL+ 12

AOUTL- 11

AOUTR+ 10

AOUTR- 9PDN

5

VSS

13VDD

14

7620

AK4382A

6601BAS316

6629

BAS316

6603

BAS316

7628BC817-25

7633BC817-25

7631

BC847B

7632

BC847B

388410k

388510k

5602FB

2841100n

284047u

GNDA

+12VA_11

2 1608A

R

1

3 1608B

L

4

5 1608C

COAX

GNDD

GNDA

TP35

TP36

TP40

TP42

TP43

TP44

GNDA

GNDA

Rt_OUT

Lt

Rt

361268k

3614220k

-12VA

3

21

84

7627A

LM833

5

67

7627B

LM833

3910

5k1 1%

REF_1

REF_2

REF_1

REF_2

2915

100n

16082723275227552756275727602761276227632764276527662767276827692770277128402841291536123614373437373741374737483750375137523753375437573758375937623763376437653766376737703771377237733774377537763777377837793780378438843885391056026601660366297620762476267627762876297630763176327633

A3

A3

A3

A4

B2

B2

B2

B3

B3

B3

B3

B3

B3

B3B3

B3

B3

B4

B4

B4B4

B4

B4

B5B5

B5

B6

B6

B7

C2C2

C2

C2

C2

C2C2

C3

C3

C3

C3C3

C4

C4

C4

C4

C4

C4C4

C5

C5

C5

C5C5

C5

C6

C6

D3

D3

D3D3

D4

D4D4

E2

E2

E2

E2

E2

E3E3

C4



M 4 Video Part

1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 8

A

B

C

F

E

D

F

E

D

C

B

A

380275R 1%

3801

0R380375R 1%

380547k3809

220R

3808

220R

3807

100R

3810

68R

3806470R

380468k

5702

2u2

2787

2u2

+5V_VID

GNDA

VID_COMP

VID_C

VID_Y

VID_U

VID_V

Y_VID

C_VID

G_VID

B_VID

R_VID

SPDIF

3870680R

3871

68R

C_VID

R_VID

B_VID

G_VID

Y_VID

GNDD

+5V_VID -12VA

38642k2

3865

68R

GNDA

+5V_VID -12VA

3874680R

3875

68R

+5V_VID -12VA

38662k2

3867

68R

+5V_VID -12VA

3861100R

CVBS_OUT_AV

CVBS_OUT

B_OUT

G_OUT

3876680R

3877

68R

+5V_VID -12VA

R_OUT

3860100R

7640A

BC847BPN

7640BBC847BPN

G_VID

R_VID

B_VID

Y_VID

GNDA

384275R 1%

3841

0R384375R 1%

384547k3849

220R

3848

220R

3847

100R

3850

68R

3846470R

384468k

5704

2u2

2818

2u2

GNDA

7644A

BC847BPN

7644BBC847BPN

381275R 1%

3811

0R381375R 1%

381547k3819

220R

3818

220R

3817

100R

3820

68R

3816470R

381468k

5706

2u2

2794

2u2

GNDA

7641A

BC847BPN

7641BBC847BPN

382275R 1%

3821

0R382375R 1%

382547k3829

220R

3828

220R

3827

100R

3830

68R

3826470R

382468k

5708

2u2

2802

2u2

GNDA

7642A

BC847BPN

7642BBC847BPN

383275R 1%

3831

0R383375R 1%

383547k3839

220R

3838

220R

3837

100R

3840

68R

3836470R

383468k

5710

2u2

2810

2u2

GNDA

7643A

BC847BPN

7643BBC847BPN

+5V_VID

+5V_VID

+5V_VID

+5V_VID

2803

100n

2811

100n

2848

100n

2795

100n

2819

100n

2814

10p

2783

10p

2798

10p

2806

10p

2790

10p

2821220p

2838 22p

2786390p

2817390p

2793390p

2801390p

2809390p

2808820p

2800820p

2792820p

2816820p

2785470p

7652

BC847B

7653

BC847B

7655

BC847B

7657

BC847B

7658

BC847B

5615 0R

CVBS

6621BZX284-C15

1

2

3

4

5

1618 EH-5P

1

2

3

4

1619

EH-4P

1

2

3

1620

EH-3P

3723

0R

3715

0R

3714

0R

3713

0R

3712

0R

4

6 1608D

CVBS

3646

0R3647

0R5VD

GNDA

TP45

TP46

TP47

TP48

TP49

TP50

TP51

TP52

TP53

TP54TP55

TP56

TP63

2914390p

5719

2u2

2913

10p

2912

470p

5718

2u2

2911390p

2910

10p

2909

10p

2908390p

5717

2u2

2907

10p

2906

470p

5716

2u2

2904

10p

2903

470p

2905390p

5715

2u2

2901

10p

2900

470p

2902390p

2853

470u

2857

470u

2825

470u

378575R 1%

378675R 1%

378775R 1%

378875R 1%

378175R 1%

GNDA

GNDA

GNDA

GNDA

GNDA

5667

0R

5666

0R

5665

0R

16181619162027832785278627872790279227932794279527982800280128022803280628082809281028112814281628172818281928212825283828482853285729002901290229032904290529062907290829092910291129122913291436463647371237133714371537233781378537863787378838013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826

3827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503860386138643865386638673870387138743875387638775615566556665667570257045706570857105715571657175718571966217640764176427643764476527653765576577658

A1

A1A1

A2A2

A2A2A2A2

A2

A2

A2

A3

A3A3A3A3A3A3

A3

A4

A4

A4A4

A5

A5

A5A5A5

B1

B1B1

B2B2

B2B2B2B2

B2

B2

B2

B3

B3B3B3B3B3B3

B3B3

B4

B4 B4

B4B4

B5

B5

B5

B5

B5

B5

C1

C1C1

C1C2C2

C2C2C2C2

C2

C2

C2

C3

C3

C3C3C3C3C3

C3C3

C4

C4

C4

C5C5C5

C5C5

D1

D1D1

D1

D2D2

D2D2D2D2

D2

D2

D2

D3

D3D3D3

D3D3D3

D3D3

D4

D4

D5D5

E1

E1E1

E1

E2E2

E2E2E2E2

E2

E2

E2

E3

E3E3E3E3E3E3

E3E3

E3E4

E4

E5

E5

E5E5

E5



M 5 Power & Scart port

1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 8

A

B

C

F

E

D

F

E

D

C

B

A

+5VD

+12V

2867100u

2862100u

GNDD

GNDD

GNDD

3.3V

+5V_VID

5VD

GNDA

GNDD

GNDA

5770 FB

2893220u

2881220u/6.3V

GNDD

1V8

5747 FB

5748 FB

5749 FB

F3V3

SD3V3

3V3

V3V3

REF_3V3

PLL_3V3

D3V3

2884100u

2886100U

2888100u

289047u

GNDD

GNDD

GNDD

GNDA

REF_GND

PLL_GND

DGND

-12VA

STDY_CTRL 3717

10K

3719

1K371856K

3721

10k

37201k 3722

10k

+12VA

2873220u

GNDD GNDDGNDD

GNDA

5VA

287047u

GNDA

GNDD

289247u

1206

1206

1206

1206

1206

GNDAGNDD

GNDD

GNDA

REF_GND

PLL_GND

DGND

2861100n

2866100n

2864100n

2871100n

2868100n

2869100n

2883100n

2889100n

2891100n

2880100n

2874100n

2877100n

2878100n

2879100n

7670BC847B

7671BC847B

1

2

3

4

5

6

7

8

1615

EH-8P

5755

FB

5756

FB

5757

FB

5758

FB

5742

FB

5744

FB

5745

FB 1206

5751

FB

5752

FB

5753

FB

5771 FB

5741 FB

5750FB

1

23

7622LD1086D2T33

1

23

7673LD1117ADT18TR

7675BC327-25

3880

0R

0603

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

1606

SCART

3769100k

GNDA

2759680p

7614BC817-25

7615BC817-25

3760100k

GNDA

2754680p

3678

470R

3680

470R

3682

2k7

3681

2k7

MUTEC

Rt_OUT

Lt_OUT

FBOUT

0/6/12

SCART-R

SCART-L

3673 220R

6609PDZ15B

2856

220p

GNDA

367747k

7616ABC847BPN

7616BBC847BPN

3676

1k

367522k

3674

75RGNDA

GNDA

+5V_VID

6608

PDZ15B

6607

PDZ15B

6606

PDZ15B

6605

PDZ15B

GNDA

CVBS_OUT

R_OUT

G_OUT

B_OUT0612

MUTEC

3857

470R

3852 10k

3856 10K

385510k

385110k

3854470R 3858

220R

GNDD

GNDD

5VD

5VD

SCART1

SCART0

3853 18k

3859 18k

7650BC847B

7651BC847B

2850

220p

2854 220p

2855 220p

2859 220p

2852100n

2822

100n2823

100n2824

100nGNDA

GNDD

GND1

GND2GND3

38880R

3889

0R3890

0R3891

0R

3893

0R

GNDD GNDA

3894

0R 3895

0R3896

0R 3897

0R3898

0R 3899

0R

3901

0R

TP64

TP65

TP66

TP67

TP68

TP69

TP70

TP71

TP72

TP73

TP74

TP75

TP76

TP77

TP78

TP79

TP80

TP81

TP82

GNDA

3716

0R

6610

PDZ15B

IN8

NC14

2

GND

3 6

OUT 1

7

NC2 5

7674MC78L05ACD

12V

3862

3908

0R 3909

0R

3920

33R

3921

33R

6611

BAS316

7676

BC807-25

+12VA

+12VA_1

291610u

160616152754275928222823282428502852285428552856285928612862286428662867286828692870287128732874287728782879288028812883288428862888288928902891289228932916367336743675367636773678368036813682371637173718371937203721372237603769385138523853385438553856385738583859386238803888388938903891389338943895389638973898389939013908

390939203921574157425744574557475748574957505751575257535755575657575758577057716605660666076608660966106611761476157616762276507651767076717673767476757676

A1

A2A2A2

A2

A2

A2

A2

A3

A3

A3

A3A3

A4A4A4

A4

B1B1

B1

B1

B2

B2

B2

B2

B3B3B3B3B3

B3B3B3

B4B4

B4

B4

B4

B4B4

C1

C1C1

C1C1

C2C2C2

C2

C2C2C2

C3C3

C3C3

C4

C4

C4

C4

C4

C5C5

C5

D1

D1D1D1

D1

D1

D1

D2

D2

D3

D3

D3D3

D3D3

D4D4

D4D4

D5

D4

E1E1

E1E2

E2

E2

E2

E2

E3E3E3

E3

E3

E3

E3

E4E4E4

E4

E4E4

F1F1F1

F1F1

F1

F2F2

F2F2

F3F4

F4

F4


Personal Notes: Personal Notes:


Layout MPEG MSD-512 Components Side

1600 B1 1619 E8 2723 C7 2771 D7 2800 F7 2817 E7 2850 G9 2869 B7 2893 F3 2908 F7 3611 C5 3635 C2 3648 C6 3665 E3 3682 D9 3716 G2 3741 D7 3760 E9 3776 C7 3799 C6 3811 F71601 A2 1620 B9 2752 A8 2783 D7 2801 F7 2818 E7 2852 E9 2870 B7 2895 A8 2909 F6 3612 D7 3636 C4 3653 F4 3666 E4 3685 B2 3717 G1 3747 B8 3763 C8 3777 B7 3800 C6 3812 E61602 B4 1621 B9 2759 D9 2785 D7 2802 F7 2819 E8 2853 G9 2871 E1 2896 B8 2910 F7 3613 C5 3637 B2 3654 A8 3667 E3 3686 C2 3718 H1 3748 B8 3764 C9 3778 B8 3801 E6 3813 F71603 A7 2612 B8 2760 B8 2786 D7 2803 F8 2821 A9 2854 F9 2873 G2 2900 E6 2911 F7 3614 D7 3639 B1 3655 B8 3668 F4 3698 B5 3719 H1 3750 B8 3765 B9 3779 B8 3802 E6 3814 F81605 C1 2663 B5 2761 C8 2787 D7 2806 G7 2822 G1 2855 F9 2881 F6 2901 E7 2912 G6 3615 D6 3640 C1 3658 F4 3673 E9 3699 A5 3720 G2 3751 B8 3766 B8 3780 B8 3803 D7 3815 F81606 F9 2683 B7 2762 D7 2790 F7 2808 G7 2823 G9 2856 E9 2883 F2 2902 D7 2913 G7 3616 D6 3641 C5 3659 F4 3674 E9 3700 B6 3721 H2 3752 C7 3770 C8 3781 G8 3804 E8 3816 F81608 B10 2690 C1 2763 C8 2792 F7 2809 G7 2824 B1 2857 F9 2884 E2 2903 E6 2914 G7 3617 D6 3642 C2 3660 C4 3675 E9 3704 G4 3722 G2 3753 D7 3771 C7 3784 C7 3805 D8 3817 F81610 A8 2691 D1 2765 C7 2793 F7 2810 G7 2825 F9 2859 E9 2886 F3 2904 E7 2915 B8 3618 C6 3644 B2 3661 D4 3676 E9 3712 G8 3723 E8 3754 D7 3772 C8 3785 E8 3806 D8 3818 F81611 A6 2692 D1 2766 B8 2794 F7 2811 G8 2838 B9 2862 H2 2888 E3 2905 E7 2916 C8 3630 C6 3645 B5 3662 D4 3677 E9 3713 F8 3724 D2 3757 C7 3773 C8 3786 E8 3807 D8 3820 F81615 E1 2693 D1 2769 B8 2795 F8 2814 E7 2840 D8 2866 E1 2890 F6 2906 E7 3603 C5 3633 B5 3646 A9 3663 D4 3678 C8 3714 F8 3725 D2 3758 D7 3774 C7 3787 F8 3808 D8 3821 F61618 F8 2694 D1 2770 C7 2798 F7 2816 E7 2848 E8 2867 E2 2892 H7 2907 F7 3604 C5 3634 B5 3647 A9 3664 E4 3680 B8 3715 E8 3734 B7 3759 C7 3775 C7 3788 F8 3810 E8 3822 E6

3823 F7 3881 F6 5645 B3 6631 B73824 F8 3882 F6 5646 B3 6633 B73825 F7 3883 F6 5647 B2 7600 D43826 F8 3902 B5 5648 B2 7602 C53827 F8 3904 A5 5651 B5 7603 C23828 F8 3905 A5 5660 C1 7604 B13830 F8 3908 H6 5661 D1 7605 C33831 G6 3910 C7 5662 D1 7606 D33832 E6 3911 C5 5663 D1 7607 D33833 G7 3912 C5 5664 D1 7608 C63834 G8 3913 C5 5702 E7 7609 C63835 G8 3914 C5 5704 E7 7610 C33836 G8 3915 C6 5706 F7 7611 F53837 G8 3916 B6 5708 F7 7612 B63838 G8 3918 C6 5710 G7 7614 C93840 G8 3919 C6 5711 B7 7615 D93841 E6 3920 C8 5712 B7 7616 E93842 E6 3921 H3 5713 B7 7620 B73843 E7 5600 B1 5714 B7 7622 F23844 E8 5601 D6 5715 E7 7624 B83845 E8 5615 B9 5716 E7 7626 B83846 E8 5617 C9 5717 F7 7627 D83847 E8 5618 B8 5718 F7 7628 B93848 E8 5621 B2 5719 G7 7629 D73850 E8 5622 B2 5741 F1 7630 D73851 C6 5623 B2 5742 E1 7631 D73852 C6 5624 B3 5744 E1 7632 D73853 C6 5625 B3 5745 E1 7633 C93854 B6 5626 B3 5747 E2 7640 D83855 C6 5627 B3 5748 F3 7641 F83856 C6 5628 B3 5749 E2 7642 F83857 B6 5629 B4 5770 F2 7643 G83858 B6 5630 B4 5771 F1 7644 E83859 C6 5631 B4 5772 B7 7650 C63861 E8 5632 B4 6601 C7 7651 C63862 B6 5633 B4 6603 D8 7652 D83864 E8 5634 B4 6604 B6 7653 E83865 D8 5635 B4 6605 G9 7655 F83866 E9 5636 B4 6606 F9 7657 F83867 E9 5637 B4 6607 F9 7658 G83870 F9 5638 B5 6608 E9 7670 H13871 E9 5640 B4 6609 D9 7671 H23874 F8 5641 B4 6610 E9 7673 G63875 F8 5642 B3 6611 G2 7674 B73876 G8 5643 B3 6621 A9 7675 G23877 G8 5644 B3 6629 C7 7676 G2


Copper SideLayout MPEG MSD-5122601 C1 2609 C2 2622 E6 2630 D5 2638 D5 2661 D2 2671 F4 2681 B7 2833 B7 2877 D6 3626 D6 3649 C4 3694 C2 3819 F8 3888 D6 3897 C7 3917 C6 5753 D52602 C3 2613 C5 2623 D5 2631 E4 2639 D4 2662 D3 2672 G5 2754 E9 2839 A10 2878 D6 3627 D6 3650 D6 3696 C2 3829 F8 3889 B6 3898 C7 5602 C8 5755 E62603 D3 2614 C4 2624 D6 2632 E4 2640 D4 2664 B4 2673 G4 2755 C9 2841 C8 2879 D6 3628 D6 3651 D2 3701 B6 3839 G8 3890 B7 3899 C7 5665 E6 5756 E62604 D3 2617 D6 2625 D4 2633 E5 2641 C4 2665 B4 2676 F5 2756 B9 2849 B10 2880 F6 3629 D6 3652 D2 3737 C7 3849 E8 3891 H6 3901 G6 5666 E6 5757 D52605 D6 2618 D6 2626 D4 2634 E4 2642 E5 2667 F4 2677 F4 2757 D8 2861 F1 2889 E3 3631 C6 3669 D6 3762 C9 3860 E8 3893 F6 3903 B5 5667 E6 5758 D52606 D6 2619 E6 2627 E4 2635 F6 2643 E4 2668 F4 2678 F4 2764 C8 2864 F2 2891 E6 3632 C6 3679 C1 3767 B9 3880 C8 3894 B8 3906 F4 5750 E6 6630 C62607 D6 2620 E6 2628 E5 2636 E5 2644 C5 2669 G4 2679 F4 2767 C8 2868 G7 3606 C6 3638 C2 3681 D9 3769 D9 3884 C8 3895 B8 3907 F4 5751 D5 6632 A72608 C6 2621 E6 2629 E5 2637 D6 2645 D6 2670 G4 2680 F5 2768 C8 2874 B7 3608 C6 3643 C1 3692 C2 3809 D8 3885 C8 3896 E6 3909 G6 5752 D5 6634 B7

TP1 C1 TP47 F8TP3 C1 TP48 E7TP4 D5 TP49 F8TP5 B1 TP50 E8TP6 C5 TP51 B7TP7 C5 TP52 E8TP8 B6 TP53 G7TP9 B6 TP54 C4TP10 B6 TP55 B9TP11 B6 TP56 A9TP12 B6 TP57 B10TP13 B6 TP58 F8TP14 B5 TP59 A9TP15 F4 TP60 A8TP16 D6 TP61 A6TP19 C6 TP62 A8TP24 E6 TP63 C9TP25 A7 TP64 E2TP26 A7 TP65 D4TP27 D1 TP66 F1TP28 A7 TP67 H3TP29 C1 TP68 F1TP30 D1 TP69 F1TP31 D1 TP70 A8TP32 D1 TP71 D9TP33 D3 TP72 E9TP34 D1 TP73 F9TP35 B9 TP74 F9TP36 F8 TP75 F9TP40 C9 TP76 E9TP42 B9 TP77 F10TP43 C9 TP78 F3TP44 C8 TP79 F6TP45 F8 TP80 E6TP46 G8 TP81 B7

EN 4435MSD-512SCircuit descriptions and List of abbreviations

8. Alignments

No electrical alignments available

9. Circuit descriptions and list of abbreviations

9.1 Decoder IC ZiVATM

-5M

Refer to Appendix A for details

9.2 Hardware & Software Interface

9.2.1 Introduction

This document defines the hardware software interface (HSI) for the DVD-SD5.11 (2) module.

SD5.11 (2) use the same mpeg board for difference slash version, but with POS Mars4.3 loader named at SD5.11 and with A97S&A97ST named at SD5.12. So the back-end s/w must support SD5.11 and SD5.12 separately, this documentation named SD5.11 (2).

The SD5.11 (2) module contains of:

• LSI Logic ZiVA5+ back-end DVD decoder / host processor

• AK4382A for audio DAC

• ATAPI interface to POS Mars4.3 (SD5.11) or A97S&A97ST (SD5.12) loader

• Basic A/V output and SCART output

• Audio (Lt/Rt and SPDIF) output connectors and Video (YUV&S-Video) output connectors for TV and other used

• Master/Slave I2C output connector for TV used

• Diagnostic connector

• JTAG interface

9.2.2 Hardware configurations

9.2.2.1 Configuration matrix

The SD5.11 (2) module is to be used in various end products. The hardware configurations for these products might have some differences, depending on features or functions that need to be implemented. Therefore, the hardware is prepared to have various stuffing options. The following is the hardware configuration matrix:

Configuration Function 1 Function 2 Detection

Flash Flash Auto-detectBack-end code memory

2MByte 2M Byte -

32bit 32bit -Back-end SDRAM

64Mbit 64Mbit Auto-detect

I2C EEPROM I2C EEPROM -NVRAM

32/64kbit 32/64Kbit Auto-detect

Module mode Master Slave Software build

Note:1. "Detection" column in the table above indicates the recommended method for the software to detect the module's

hardware configuration at boot up. 2. Different software will be used for some hardware configurations. Hence, detection by software is not required.

Instead, the software should be separately built and the configurations can be selected via compiler switches.

9.2.2.2 Module mode

The SD5.11(2) module has two I2C buses. The Master I2C is using software I2C via GPIO ports & the Slave uses hardware I2C because of its speed.

The master I2C bus is used to control all on-board devices eg. NVRAM, etc… & the Slave I2C bus is used to connect to an external processor eg. TV micro-p which acts as the I2C Master controller. An additional signal, I2C Int, is used to flag to the external processor when data is available in the Slave mode.

9.2.2.3 Configuration by LOR (Latch On Reset)

The host processor, ZiVA5+, has a number of Latch On Reset (LOR) pins that can be used for setting particular modes/features upon power-up. The following pins are shown:

EN 44 36 MSD-512S Circuit descriptions and List of abbreviations

ZIVZ-5 LOR Pins Feature vs Pin

148 150 151 154 155 156 162 164 187 185

LOR Feature Host Drive Sel System Clock Speed Sel

X’tal Sel PLLBypass Sel

Chip Mode Sel

AtapiMaster/Slave

Normal Function LRCKPCMLt/Rt

PCMLo/Ro

PCMLs/Rs

PCMC/Sw

IEC958IDE Reset

DiagsTXD

Master I2C, SDA

Master I2C Clk

Set To:- Hi Hi Lo Lo Hi Lo Hi Lo Hi Hi

LOR Function on Power-up

Low drive I/O 121.50Mhz

13.5Mhz X’tal

Use Int PLL

Muxed A/D Master (Async Master Mode)

AtapiMaster

Note:1. Other LOR pins are not provisioned with pull-up or pull-down resistors. Hence, the default settings are used. 2. LOR function to be checked on final layout 3. System Clock Setting can be adjusted as shown:

154 151 150 Value Set

0 0 0 108.0MHz

0 0 1 121.5MHz

0 1 0 135.0MHz

System clock (clk_speed_sel)

0 1 1 148.5MHz

9.2.2.4 Configuration description

Back-end code memory

2MB Flash is used to store the back-end software. The Flash is Top-boot & TSOP48 footprint. Devices supported are:

12NC Part No Manufacturer Description

9322 165 50668 M29W160DT-70N1T ST Microelectronics 1Mbit x 16 flash memory (2MB)

9322 178 20668 MX29LV160TTC-70TR Macronix 1Mbit x 16 flash memory (2MB)

Back-end SDRAM

Since the width of ZiVA5+ SDRAM bus is 32-bit, one TSOP86 footprint for 32-bit SDRAM is connected in parallel.

12NC Part No Manufacturer Size

9322 176 03668 K4S643232E-TC70T Samsung 2Mbit x 32 (64Mbit)

9322 168 09685 MT48LC2M32B2TG-7 Micron 2Mbit x 32 (64Mbit)

NVRAM

The NVRAM to be used is a serial I2C bus EEPROM. This device is connected to the master I2C bus. A 32kbit or 64kbit device can be used, depending on the software and feature requirements. The parts to be supported are given below:

12NC Part No Manufacturer Size

9322 156 81668 M24C32-WMN6TNKSA ST Microelectronics 32kbit NVRAM

9322 106 84668 AT24C32N-10SI-1.8 T&R Atmel 32kbit NVRAM

9322 165 31668 24LC32AT-I/SN Microchip 32kbit NVRAM

9322 151 00668 BR24C32F-E2 Rohm 32kbit NVRAM

9322 130 41668 M24C64-WMN6T ST Microelectronics 64kbit NVRAM

E-link daughter card

The E-link daughter card is used for software development only. An interface is prepared on the module to interface to this board.


9.2.3 DVD host processor ZiVA5+

The DVD host processor used in SD5.11 is ZiVA5+ from LSI Logic.

9.2.3.1 Chip selects

CS# Device

0 Flash memory

1 N/u

2 E-Link daughter card

3 IDE0

4 IDE1

9.2.3.2 Interrupts

ZiVA5+ external interrupt pins:

HIRQ# Device

0 E-Link daughter card

1 ATAPI

2 N/u

Note: 1. All interrupt pins are connected to pull-up resistors.

9.2.3.3 GPIO assignments

GPIO Pin Assignment Type Application

0_1 28 GPIO0_1 I IR receiver control signal (Reserved)

1_1 115 VDATA0 IO VFD driver signal, DATA

1_2 114 VDATA1 O VFD driver signal, CLK

1_3 113 VDATA2 O VFD driver signal, CS

1_4 110 VDATA3 O DAC control signal, CS

1_5 109 VDATA4 O DAC control signal, CLK

1_6 108 VDATA5 O DAC control signal, DATA

1_7 107 VDATA6 O Mute the audio (final analog stage)

1_8 106 VDATA7 O N/u

1_9 116 HIRQ2n I N/u

1_10 184 HIRQ1n I ATAPI interrupt

1_11 192 HCS3n O IDE0 chip select

1_12 191 HCS4n O IDE1 chip select

2_10 161 IDC_DA IO Hardware I2C, SDA

2_11 160 IDC_CL IO Hardware I2C, SCL

2_12 185 RTS2 O Software I2C, SCL

2_13 188 CTS2 O I2CRDY

2_14 187 TXD2 O Software I2C, SDA

2_15 186 RXD2 I N/u

3_11 162 GPIO3_11 O IDE reset

3_12 165 GPIO3_12 O N/u

3_13 164 TXD1 O Diagnostic UART TXD

3_14 163 RXD1 I Diagnostic UART RXD

3_15 193 HCS2n O E-Link chip select

4_1 150GPIO4_1 / ADATA0 IO

PCM audio LtRt data output

4_2 151 ADATA1 O N/u




4_5 156 IEC958 O SPDIF (digital audio) output

4_6 159 GPIO4_6 O Scart0

4_7 158 GPIO4_7 O Scart1

4_8 157 DAI_DATA I N/u

5_1 177 SDDATA0 I N/u



5_4 174 SDDATA3 I n/u


5_6 170 SDDATA5 I DMACK, IDE DMA acknowledge


5_8 168 SDDATA7 I DMARQ, IDE DMA request

5_9 178 SDREQ O n/u

5_10 182 SDERROR I N/u

5_11 179 SDEN I N/u

5_12 183 SDCLK I N/u

Service I Option 1: Diagnostic mode select

5_13 199 TDI I Option 2: ZiVA5+ JTAG TDI

5_14 200 TMS I ZiVA5+ JTAG TMS

9.2.3.4 GPIO assignments description

9.2.3.4.1 IR (pin28)

Function: IR receiver signal Type: Input

This signal is from IR receiver that located in the front panel, the signal carry RC-6 code. The back-end s/w must be decoded this signal for the remote control issues & optional.

For UI2002 firmware, it is reserved. For Turnkey version firmware, it is used for IR signal decode.

9.2.3.4.2 VFD driver control signal (pin115, 114, 113)

Function: VFD driver control signals Signal: VFD_DATA, VFD_CLK, VFD_CS Type: SIO serial bus

These signals are SIO serial bus, refer to the VFD driver specification for the detail information. If don’t use IR signal for the remote controller purpose, the VFD driver can decode RC-6 code internal and communicate with ZiVA5+ by the SIO serial bus.

9.2.3.4.3 DAC control signal (pin108, 109, 110)

Function: Audio DAC control signals Signal: DAC_CS, DAC_DATA, DAC_CLK Type: SIO serial bus

These signals are SIO serial bus, refer to the audio DAC specification for the detail information.

9.2.3.4.4 MUTE (pin107)

Function: Mute the audio at the final analog stage Type: Push-pull output

State Function Boot up default

LOW Mute OFF

HIGH Mute ON

This is a global audio mute, which block the final analog stage, and affect all channels simultaneously. The main objective of this signal is to prevent switching noise at the audio output as the player changes its mode of operation.


Apart from this global mute, additional audio mute should be applied to all stages of the audio path where possible. For example, the decoder should apply digital mute to the audio stream as needed. Note that this global mute does not provide adequate attenuation to normal audio signals and should not be used as an alternative to digital mute.

9.2.3.4.5 I2CRDY (pin188)

Function: Data available for transmission in slave I2C bus Type: Push-pull output


LOW No data

HIGH Data available

This signal is used in conjunction with the slave I2C bus & is optional. Its use makes the Slave protocol more robust.

9.2.3.4.6 SCL1, SDA1 (pin185, 187)

Function: Secondary I2C Type: Open-drain IO

This I2C bus is only required when the SD module is operating in slave mode. The secondary I2C bus is a software implementation using GPIO, and cannot handle high data rate.

9.2.3.4.7 SCART0, SCART1 (pin159, 158)

Function: Slow blanking SCART Type: Push-pull output

SCART0 SCART1 Function 0_6_12V (at SCART connector) Boot up default

HIGH HIGH TV display 0V

LOW HIGH TV display 0V

HIGH LOW 16:9 aspect ratio +6V

LOW LOW 4:3 aspect ratio +12V

The SCART0 AND SCART1 signals are converted to the 0_6_12V voltages by external circuitry.

9.2.3.4.8 Service (pin199)

Function: Select diagnostic or application software Type: input


LOW Diagnostic (service) mode

HIGH Normal (player application) mode

The state of this pin is sampled upon reset of the ZiVA5+, by the boot code. Once the Diagnostic or Normal mode is selected, this pin is not used again. This pin is pulled to 5VD via a 10kohm resistor.

9.2.3.5 Audio DAC

The table shows the DAC’s supported, and the clock selection should be comply with spec of ZiVA5+ and DAC.

12NC Part No Manufacturer Description

9322 177 09685 AK4382A AKM 2-Ch, Diff DAC

9.2.3.6 Video DAC

The Table below shows the Multiplexed nature of the ZiVA5+ internal Video Dac’s & the jumper options on the pcb to cater for the different O/P configurations:

Mode Mode DAC1 DAC2 DAC3 DAC4 DAC5

1 SCART RGB CVBS CVBS G B R

2 Y/C Y C

3 SCART Y/C + RGB Y C G B R


4 Non-component CVBS C Y

5 Component CVBS C Y Pb Pr

6 480P Y Pb Pr

For DVD set used, it should support mode1 and mode 5, according to the slash version definitions. For TV used, the back-end s/w should support mode2,3 or mode 5, but for the current product, it must use mode 2 to reduce EMI and temperature issue.

9.2.4 Addresses of I2C devices

Part No Device I2C address

5.11 Module Slave Module 1 1 1 0 0 0 1 (71H)

24C32/64 NVRAM 1 0 1 0 0 0 0 (50H)

9.3 List of abbreviations

Term Meaning

1 kbit / kb 210

bit

1 Mbit / Mb 220

bit

1 kByte /kB 210

Byte (1 Byte = 8 bit)

1MByte / MB 220

Byte (1 Byte = 8 bit)

AC-3 Old term for Dolby Digital ®

ADC Analog to digital converter

ASD Architecture and standard design

AV Audio video

CD Compact disc

CDDA Compact disc digital audio

CDROM Compact disc read-only memory

CVBS Composite video blanking and synchronization signal

DAC Digital to analog converter

DENC Digital encoder

DRAM Dynamic random access memory

DTS Digital Theatre Sound ®

DVD Digital versatile disc

DVD back-end

DVD digital (MPEG, etc) decoder part

DVD front-end

DVD servo part (was previously referred as Basic Engine)

EMC Electromagnetic compatibility

I2C Inter-IC (Philips patented communication bus)

I2S Inter-IC sound

IC Integrated circuit

IO Input output

IRQ Interrupt request

KOK Karaoke

LFE Low frequency (sub-woofer) effect

LPCM Linear pulse code modulation

LSB Least significant bit

LVTTL Low voltage transistor-transistor logic (3.3V logic)

MLP Meridian Lossless Packing

MPEG Motion picture expert group

MPEG1 / MPEG2

MPEG standard used by VCD and DVD

MP3 Informal audio codex, which employs audio portion of MPEG1, MPEG2 and others

MSB Most significant bit

mA Milli-ampere

NTSC Video standard defined by National Television Standards Committee

NVRAM Non-volatile random access memory

OSD On-screen display

PAL Phase alternation line (video standard)

PCB Printed circuit board

PCM Pulse code modulation

PS Power supply

RAM Random access memory

RGB Red green and blue color space

ROM Read-only memory

SACD Super audio compact disc

SDRAM Synchronous dynamic random access memory

SD module Standard design module

SRAM Static random access memory

TTL Transistor-transistor logic (5V logic)

UART Universal asynchronous receiver transmitter

V Volts

VCD Video compact disc

Y/C S-video (luma and chroma) format

YCbCr Color space defined by Recommendation ITU-R BT.601

YUV Luma and chroma video component (actually should be YCbCr)

EN 4441MSD-512SSpare Parts List

3141 019 22761 MSD-512S/00 MONO ASSY

0100 3139 121 27221 TOP SHIELD MPEG BOARD

0101 3139 121 27211 BTM SHIELD MPEG BOARD

1003 3141 018 03924 PBAS MPEG SD5.12

8001 3139 131 02841 CBLE HR-BK 06P/600/08P HR-BK

8002 3104 311 06311 CBLE HR 3P4/340/3P HR WH

8003 3104 311 06301 CBLE HR 7P/340+220/3P+4P HR BK

8004 3139 131 03151 CBLE HR 03P/180/03P HR (BRAIDED)

8005 3139 131 01841 CBLE HR-BK 3P/140/3P HR-BK

8006 3141 010 21592 CWAS 40RK/40RK 400 SHIELD 28S

3141 019 22771 MSD-512S/69 MONO ASSY



1003 3141 018 03924 PBAS MPEG SD5.12

8001 3139 131 02691 CBLE HR 04P/400/03P HR

8002 3139 131 02612 CBLE HR 06P/480/04P HR FERR

8003 3139 131 02321 CBLE HR-BK 3P/400/3P HR-BK 26OS

8004 3139 131 03151 CBLE HR 03P/180/03P HR (BRAIDED)

8005 3139 131 02841 CBLE HR-BK 06P/600/08P HR-BK

8006 3141 010 21592 CWAS 40RK/40RK 400 SHIELD 28S

3141 018 03924 PBAS MPEG SD5.12

Various

1600 4822 267 10618 B7B-PH-K (7P)

1601 2422 025 17357 CON BM V 40P M 2.54 440094 B

1603 4822 267 10565 4P

1611 2422 025 08149 CON BM V 6P M 2.00 PH B

1615 2422 025 12482 CON BM V 6P M 2.50 EH B

1619 4822 267 10565 4P

1620 4822 267 10735 B3B-EH-A

1621 2422 025 16382 CON BM V 03P M 2.50 EH-K

Capacitors

2601 4822 126 14247 CER2 0603 X7R 50V 1N5 COL R

2602 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2603 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2604 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2605 4822 122 33761 22PF 5%NP0 50V

2606 4822 122 33761 22PF 5%NP0 50V

2607 4822 122 33761 22PF 5%NP0 50V

2608 4822 122 33761 22PF 5%NP0 50V

2612 4822 122 33761 22PF 5%NP0 50V

2613 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2614 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2617 3198 016 33380 CER1 0603 NP0 50V 3P3 COL

2618 3198 016 33380 CER1 0603 NP0 50V 3P3 COL

2619 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2620 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2621 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2622 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2623 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2624 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2625 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2626 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2627 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2628 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2629 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2630 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2631 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2632 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2633 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2634 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2635 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2636 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2637 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2638 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2639 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2640 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2641 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2642 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2643 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2644 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2645 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2661 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2662 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2663 4822 124 81286 47UF20% 16V

2667 4822 122 33741 10PF10%NP0 50V

2668 4822 122 33741 10PF10%NP0 50V

2669 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2670 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2671 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2672 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2673 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2676 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2677 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2678 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2679 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2680 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2681 4822 122 33761 22PF 5%NP0 50V

2723 4822 124 81286 47UF20% 16V

2752 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2755 4822 126 13909 680PF 10% X7R 50V

2756 4822 126 13909 680PF 10% X7R 50V

2757 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2760 4822 124 81286 47UF20% 16V

2761 4822 124 81286 47UF20% 16V

2762 4822 124 23052 100UF20% 16V

2763 4822 126 14315 390PF 5% NP0 50V 0603

2764 4822 126 14315 390PF 5% NP0 50V 0603

2765 5322 126 11579 3,3NF10%X7R 63V

2766 4822 126 14315 390PF 5% NP0 50V 0603

2768 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2769 4822 126 14315 390PF 5% NP0 50V 0603

2770 5322 126 11579 3,3NF10%X7R 63V

2771 4822 124 81286 47UF20% 16V

2783 4822 122 33741 10PF10%NP0 50V

2785 3198 016 38210 CER1 0603 NP0 25V 820P COL

2786 4822 126 14315 390PF 5% NP0 50V 0603

2787 4822 124 22652 2,2UF20% 50V

2814 4822 122 33741 10PF10%NP0 50V

2816 3198 016 38210 CER1 0603 NP0 25V 820P COL

2817 4822 126 14315 390PF 5% NP0 50V 0603

2818 4822 124 22652 2,2UF20% 50V

2819 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2822 4822 051 30008 0R00 JUMPER

2823 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2824 4822 051 30008 0R00 JUMPER

2833 4822 122 33761 22PF 5%NP0 50V

2838 4822 126 14226 82PF 5% NP0 50V 0603

2840 4822 124 23052 100UF20% 16V

2841 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2848 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2864 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2866 2238 586 59812 CER2 0603 Y5V50V 100NP80M

EN 44 42 MSD-512S Spare Parts List

2867 4822 124 23052 100UF20% 16V

2868 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2869 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2870 4822 124 81286 47UF20% 16V

2871 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2873 4822 124 40196 220UF20% 16V

2874 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2877 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2878 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2879 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2880 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2881 4822 124 23052 100UF20% 16V

2883 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2884 4822 124 23052 100UF20% 16V

2886 4822 124 23052 100UF20% 16V

2888 4822 124 23052 100UF20% 16V

2889 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2890 4822 124 81286 47UF20% 16V

2891 2238 586 59812 CER2 0603 Y5V50V 100NP80M

2892 4822 124 81286 47UF20% 16V

2893 4822 124 23052 100UF20% 16V

2902 4822 126 14315 390PF 5% NP0 50V 0603

2905 4822 126 14315 390PF 5% NP0 50V 0603

2916 4822 124 11947 10UF 20% 16V

Resistors

3604 4822 051 30008 0R00 JUMPER

3611 4822 051 30472 4K70 5% 0,062W

3613 4822 051 30472 4K70 5% 0,062W

3615 4822 051 30339 33R00 5% 0,062W

3616 4822 051 30339 33R00 5% 0,062W

3617 4822 051 30339 33R00 5% 0,062W

3618 4822 051 30339 33R00 5% 0,062W

3628 4822 051 30472 4K70 5% 0,062W

3629 4822 051 30472 4K70 5% 0,062W

3633 4822 051 30472 4K70 5% 0,062W

3635 4822 051 30472 4K70 5% 0,062W

3636 4822 117 13576 NETW 4 X 33R 5% 1206

3637 4822 051 30103 10K00 5% 0,062W

3638 4822 051 30472 4K70 5% 0,062W

3639 4822 051 30103 10K00 5% 0,062W

3640 4822 051 30101 100R00 5% 0,062W

3642 4822 051 30103 10K00 5% 0,062W

3643 4822 051 30682 6K80 5% 0,062W

3644 4822 051 30103 10K00 5% 0,062W

3645 4822 051 30103 10K00 5% 0,062W

3646 4822 051 30008 0R00 JUMPER

3648 4822 051 30339 33R00 5% 0,062W

3649 4822 051 30339 33R00 5% 0,062W

3650 5322 117 13018 1K0 1% 0.063W 0603 RC22H

3651 4822 051 30472 4K70 5% 0,062W

3652 4822 051 30472 4K70 5% 0,062W

3653 4822 051 30339 33R00 5% 0,062W

3658 4822 051 30339 33R00 5% 0,062W

3659 4822 051 30339 33R00 5% 0,062W

3660 4822 117 13576 NETW 4 X 33R 5% 1206

3661 4822 117 13576 NETW 4 X 33R 5% 1206

3662 4822 117 13576 NETW 4 X 33R 5% 1206

3663 4822 117 13576 NETW 4 X 33R 5% 1206

3664 4822 117 13576 NETW 4 X 33R 5% 1206

3665 4822 117 13576 NETW 4 X 33R 5% 1206

3666 4822 117 13576 NETW 4 X 33R 5% 1206

3667 4822 117 13576 NETW 4 X 33R 5% 1206

3668 4822 117 13576 NETW 4 X 33R 5% 1206

3669 5322 117 13061 180R 1% 0.063W 0603 RC22H

3679 4822 051 30102 1K00 5% 0,062W

3685 4822 051 30472 4K70 5% 0,062W

3686 4822 051 30472 4K70 5% 0,062W

3696 4822 051 30008 0R00 JUMPER

3698 4822 051 30472 4K70 5% 0,062W

3699 4822 051 30102 1K00 5% 0,062W

3700 4822 051 30103 10K00 5% 0,062W

3701 4822 051 30103 10K00 5% 0,062W

3704 4822 051 30103 10K00 5% 0,062W

3716 4822 051 30008 0R00 JUMPER

3724 4822 051 30339 33R00 5% 0,062W

3725 4822 051 30339 33R00 5% 0,062W

3734 5322 117 13026 4K7 1% 0.063W 0603 RC22H

3737 4822 051 30472 4K70 5% 0,062W

3741 4822 051 30472 4K70 5% 0,062W

3747 4822 117 12139 22R 5% 0,062W

3748 4822 051 30101 100R00 5% 0,062W

3752 4822 051 30472 4K70 5% 0,062W

3753 4822 051 30102 1K00 5% 0,062W

3754 4822 051 30102 1K00 5% 0,062W

3757 4822 051 30682 6K80 5% 0,062W

3758 4822 051 30222 2K20 5% 0,062W

3759 4822 051 30008 0R00 JUMPER

3762 4822 051 30103 10K00 5% 0,062W

3763 4822 051 30101 100R00 5% 0,062W

3764 4822 051 30272 2K70 5% 0,062W

3765 4822 051 30272 2K70 5% 0,062W

3766 4822 051 30101 100R00 5% 0,062W

3767 4822 051 30103 10K00 5% 0,062W

3770 2322 704 65102 RST SM 0603 RC22H 5K1 PM1

3771 5322 117 13026 4K7 1% 0.063W 0603 RC22H

3772 2322 704 62001 RST SM 0603 RC22H 200R PM1 R

3773 2322 704 62001 RST SM 0603 RC22H 200R PM1 R

3775 5322 117 13026 4K7 1% 0.063W 0603 RC22H

3776 5322 117 13026 4K7 1% 0.063W 0603 RC22H

3778 2322 704 62001 RST SM 0603 RC22H 200R PM1 R

3779 2322 704 65102 RST SM 0603 RC22H 5K1 PM1

3780 2322 704 62001 RST SM 0603 RC22H 200R PM1 R

3784 2322 704 65102 RST SM 0603 RC22H 5K1 PM1

3785 5322 117 13055 75R 1% 0.063W 0603 RC22H

3786 5322 117 13055 75R 1% 0.063W 0603 RC22H

3799 5322 117 13031 5K6 1% 0.063W 0603 RC22H

3800 5322 117 13031 5K6 1% 0.063W 0603 RC22H

3801 4822 051 30008 0R00 JUMPER

3802 5322 117 13055 75R 1% 0.063W 0603 RC22H

3803 5322 117 13055 75R 1% 0.063W 0603 RC22H

3804 4822 051 30683 68K00 5% 0,062W

3805 4822 117 12925 47K 1% 0.063W 0603

3806 4822 051 30471 470R00 5% 0,062W

3807 4822 051 30101 100R00 5% 0,062W

3808 4822 051 30221 220R00 5% 0,062W

3809 4822 051 30221 220R00 5% 0,062W

3810 4822 051 30689 68R 5% 0,063W 0603 RC21 RST SM

3841 4822 051 30008 0R00 JUMPER

3842 5322 117 13055 75R 1% 0.063W 0603 RC22H

3843 5322 117 13055 75R 1% 0.063W 0603 RC22H

3844 4822 051 30683 68K00 5% 0,062W

3845 4822 117 12925 47K 1% 0.063W 0603

3846 4822 051 30471 470R00 5% 0,062W

3847 4822 051 30101 100R00 5% 0,062W

3848 4822 051 30221 220R00 5% 0,062W

3849 4822 051 30221 220R00 5% 0,062W

3850 4822 051 30689 68R 5% 0,063W 0603 RC21 RST SM

3880 4822 051 30008 0R00 JUMPER

3884 4822 117 13632 100K 1% 0603 0.62W

3885 4822 117 13632 100K 1% 0603 0.62W

3888 4822 051 30008 0R00 JUMPER

3889 2238 586 59812 CER2 0603 Y5V50V 100NP80M

3890 2238 586 59812 CER2 0603 Y5V50V 100NP80M

3891 4822 051 30008 0R00 JUMPER

3893 4822 051 30008 0R00 JUMPER

EN 4443MSD-512SSpare Parts List

3894 2238 586 59812 CER2 0603 Y5V50V 100NP80M

3895 4822 051 30008 0R00 JUMPER

3896 4822 051 30008 0R00 JUMPER

3897 4822 051 30008 0R00 JUMPER

3898 4822 051 30008 0R00 JUMPER

3899 4822 051 30008 0R00 JUMPER

3901 4822 051 30008 0R00 JUMPER

3903 4822 051 30008 0R00 JUMPER

3906 4822 051 30101 100R00 5% 0,062W

3907 4822 051 30101 100R00 5% 0,062W

3908 4822 051 30008 0R00 JUMPER

3909 4822 051 30008 0R00 JUMPER

3910 2322 704 65102 RST SM 0603 RC22H 5K1 PM1

3911 4822 051 30008 0R00 JUMPER

3912 4822 051 30008 0R00 JUMPER

3915 4822 051 30008 0R00 JUMPER

3920 4822 051 30151 150R00 5% 0,062W

Coils & Crystal Quartz

5600 2422 549 43062 IND FXD SM EMI 100MHZ 600R R

5601 3141 018 80781 CRYSTAL 13.5MHZ


5615 2422 549 45618 IND FXD 0603 EMI 100MHZ 60R R

5617 2422 549 45618 IND FXD 0603 EMI 100MHZ 60R R

5618 2422 549 45618 IND FXD 0603 EMI 100MHZ 60R R



























5702 4822 157 10586 2,2UH 10% 0805

5704 4822 157 10586 2,2UH 10% 0805

5715 4822 157 10586 2,2UH 10% 0805

5716 4822 157 10586 2,2UH 10% 0805



















Diodes

6601 4822 130 11397 BAS316

6603 4822 130 11397 BAS316

6604 4822 130 11397 BAS316

6629 4822 130 11397 BAS316

6630 4822 130 11397 BAS316

6631 4822 130 11522 UDZ15B

6632 4822 130 11522 UDZ15B

6633 4822 130 11522 UDZ15B

6634 4822 130 11522 UDZ15B

Transistors & Intergate Circuits

7600 9322 195 06671 IC SM ZIVA-5M (LLC0) Y

7602 9322 130 41668 IC SM M24C64-WMN6 (ST00) R

7603 5322 130 60159 BC846B

7604 5322 130 60159 BC846B

7605 9351 707 10112 IC SM 74LVT573DB (PHS0) L

7606 9351 707 10112 IC SM 74LVT573DB (PHS0) L

7607 9351 707 10112 IC SM 74LVT573DB (PHS0) L

7608 9965 000 04199 BSN20

7609 9965 000 04199 BSN20

7610 3141 017 40951 IC M29W160DT-SD5.12

7611 9322 180 36671 IC SM MT48LC4M32B2TG-7 (MRN0) Y

7612 5322 130 60159 BC846B

7620 9322 177 09685 IC SM AK4382AVT (AKM0) R

7622 3141 018 51741 IC LD1086D2T33 (ST00)

7624 9352 456 80115 74HCT1G125GW

7626 4822 209 30095 LM833D

7627 4822 209 30095 LM833D

7628 5322 130 60159 BC846B

7629 4822 130 60373 BC856B

7630 4822 130 60373 BC856B

7631 5322 130 60159 BC846B

7632 5322 130 60159 BC846B

7633 5322 130 60159 BC846B

7640 9340 425 30115 TRA SIG SM BC847BPN (PHSE) R

7644 9340 425 30115 TRA SIG SM BC847BPN (PHSE) R

7673 9322 167 69668 IC SM LD1117ADT18 (ST00) R

7674 4822 209 33411 MC78L05ACD

3141 019 22751 MSD-512S LOADER ASSY (For MSD-512S/00 & /69)

0103 3139 121 27201 DVD TOP SHIELD

0104 3139 121 27191 DVD BOTTOM PLATE

1004 3141 018 03881 DVD LOADER MODULE A97ST

EN 44 44 MSD-512S Spare Parts List

MSD-512S/78

1001 3141 018 03881 DVD LOADER MODULE A97ST (ACTIMA)

1003 3141 018 03924 PBAS MPEG SD5.12

1005 3141 010 21901 CWAS 40RK/40RK 400 28S

MSD-512S/ARG



1001 3141 018 03881 DVD LOADER MODULE A97ST (ACTIMA)

1003 3141 018 03924 PBAS MPEG SD5.12

1005 3141 010 21901 CWAS 40RK/40RK 400 28S

®

ZiVA®-5+Stream Data Port(ZiVA-5 for Philips Electronics, N.V.)

TECHNICALMANUAL

M a y 2 0 0 2

Advance

LSI Logic Confidential


iiAdvance Copyright © 2002 by LSI Logic Corporation. All rights reserved.

This document is advance. As such, it describes a product under development.This information is intended to help you evaluate the product. LSI Logic reservesthe right to change or discontinue this proposed product without notice.

This document contains proprietary information of LSI Logic Corporation. Theinformation contained herein is not to be used by or disclosed to third partieswithout the express written permission of an officer of LSI Logic Corporation.

Document DB06-000415-00, Advance Edition (May 2002)This document describes LSI Logic Corporation’s Rel. 02 and will remain theofficial reference source for all revisions/releases of this product until rescindedby an update. This on-line document may supersede the printed version of thisdocument.

LSI Logic Corporation reserves the right to make changes to any products hereinat any time without notice. LSI Logic does not assume any responsibility orliability arising out of the application or use of any product described herein,except as expressly agreed to in writing by LSI Logic; nor does the purchase oruse of a product from LSI Logic convey a license under any patent rights,copyrights, trademark rights, or any other of the intellectual property rights of LSILogic or third parties.

Copyright © 2002 by LSI Logic Corporation. All rights reserved.

TRADEMARK ACKNOWLEDGMENTThe LSI Logic logo design and ZiVA are trademarks or registered trademarks ofLSI Logic Corporation. SPARC and microSPARC are registered trademarks ofSPARC International, Inc. Products bearing SPARC trademarks are based on anarchitecture developed by Sun Microsystems, Inc. Motorola and Coldfire areregistered trademarks of Motorola Inc. PowerPC is a trademark of InternationalBusiness Machines Corporation. Windows, Windows NT, and MSDN aretrademarks of Microsoft Corporation. All other brand and product names may betrademarks of their respective companies.

EJV

To receive product literature, visit us at http://www.lsilogic.com.

For a current list of our distributors, sales offices, and design resourcecenters, view our web page located at

http://www.lsilogic.com/contacts/na_salesoffices.html

ZiVA-5+ Stream Data Port Advance Technical Manual iiiAdvance Copyright © 2002 by LSI Logic Corporation. All rights reserved.


Preface

This document describes a nonstandard pinout and block diagram for theZiVA®-5+ device. This pinout is based on the requirements of PhilipsElectronics, N.V., to accommodate the use of a UDE loader, a digitalaudio receiver, and an analog-to-digital converter (ADC).

Conventions Used in This Manual

The first time a word or phrase is defined in this manual, it is italicized.

The word assert means to drive a signal true or active. The worddeassert means to drive a signal false or inactive. Signals that are activeLOW are denoted by an overbar, as in HCS0.

Hexadecimal numbers are indicated by the prefix “0x” —for example,0x32CF. Binary numbers are indicated by the prefix “0b” —for example,0b0011.0010.1100.1111.

The following notational conventions are used in this manual:

Notation Example Meaning and Use

courier typeface .nwk file Names of commands, files, signals, symbols, pins, parts,directories, modules, and macrocells are shown in cou-rier typeface.

bold typeface fd1sp In a command line, keywords are shown in bold, non-italic typeface. Enter them exactly as shown.

italics module In command lines and names italics indicate user vari-ables. Italicized text must be replaced with appropriateuser-specified items. Enter items of the type called for,using lower case.

italic underscore full_pathname When an underscore appears in an italicized string, entera user-supplied item of the type called for with nospaces.


iv PrefaceAdvance Copyright © 2002 by LSI Logic Corporation. All rights reserved.

Revision History

Initial Capital letters UndoEditApply

Names of menu commands, options, check buttons, textbuttons, options buttons, text boxes, list boxes, etc., areshown in text with Initial Capital lettering to avoid mis-reading. These elements may appear on your screen inall lower case.

brackets [version] You may, but need not, select one item enclosed withinbrackets. Do not enter the brackets.

bar les | les.out You may select one (but not more than one) item from alist separated by bars. Do not enter the bar.

braces property | -all You must select one (but not more than one) itemenclosed within braces. Do not enter the braces.

ellipses option... In command formats, elements preceding ellipses maybe repeated any number of times. Do not enter theellipses. In menu items, if an ellipsis appears an item,clicking that item brings up a dialog box.

vertical dots ...

Vertical dots indicate that a portion of a program or listinghas been omitted from the text.

semicolon, and otherpunctuation

Use as shown in the text.

Date Part No. Description

May 2002 DB06-000415-00 Advanced Draft - First Issue

Notation Example Meaning and Use

ZiVA-5+ Stream Data Port Advance Technical Manual vAdvance Copyright © 2002 by LSI Logic Corporation. All rights reserved.


Contents

Chapter 1 Introduction1.1 Features 1-11.2 Block Diagram 1-7

Chapter 2 Pin and Signal Descriptions2.1 Pin Descriptions 2-12.2 Signal Descriptions 2-12

2.2.1 Latch On Reset (LOR) Signals 2-232.2.2 Latch On Reset Signal Descriptions 2-242.2.3 Pin Multiplexing 2-26

Chapter 3 Specifications3.1 Electrical Characteristics 3-1

3.1.1 General Electrical Characteristics 3-13.1.2 Electrical Characteristics Summary 3-4

3.2 AC Timing Diagrams 3-83.2.1 Global Interface Timing 3-83.2.2 SDRAM Timing Diagrams 3-93.2.3 Async Master Personality Module Timing 3-123.2.4 IDE Personality Module Timing 3-143.2.5 IDC Interface AC Timing 3-173.2.6 PCM Audio Interface AC Timing 3-173.2.7 I2S Bus Timing 3-183.2.8 UART Timing 3-193.2.9 Video Interface AC Timing 3-193.2.10 SPI Interface AC Timing 3-23

3.3 Package Mechanical Dimensions 3-253.4 Package Marking 3-27


ZiVA-5+ Stream Data Port Advance Technical Manual viiAdvance Copyright © 2002 by LSI Logic Corporation. All rights reserved.

Figures1.1 Block Diagram 1-71.2 Enhanced Block Diagram 1-82.1 ZiVA-5+ Processor Pinout (208-pin PQFP) 2-23.1 Input Rise and Fall Timing Diagram 3-83.2 SYSCLK Timing Diagram 3-83.3 SDRAM Output Load 3-103.4 SDRAM Write Timing Waveform 3-113.5 SDRAM Read Timing Waveform 3-113.6 Async Master Timing 3-123.7 IDE PIO Data Transfer Cycle 3-143.8 Single-word DMA Transfer 3-163.9 Data Transfers on the IDC Bus 3-173.10 PCM Interface AC Timing 3-183.11 I2S Bus Timing 3-183.12 UART Receiver Timing 3-193.13 Horizontal Synchronization Waveform 3-193.14 VSYNC and HSYNC Master Mode Waveform 3-203.15 NTSC Active Horizontal Line Input Timing 3-203.16 NTSC Active Horizontal Line Output Timing 3-203.17 PAL Active Horizontal Line Input Timing 3-213.18 PAL Active Horizontal Line Output Timing 3-213.19 ITU-R BT.656 Video Output Timing 3-213.20 Video Interface Encoder Mastering AC Timing Diagram 3-223.21 Video Interface Decoder Mastering AC Timing Diagram 3-223.22 ITU-R BT.656 Interlaced Video Input Timing 3-223.23 SPI Serial Data Clocking 3-243.24 SPI Timing 3-243.25 208-pin PQFP Package Mechanical Dimensions 3-263.26 ZiVA5+ Variant Marking 3-27


ZiVA-5+ Stream Data Port Advance Technical Manual ixAdvance Copyright © 2002 by LSI Logic Corporation. All rights reserved.

Tables1.1 ZiVA-5M+ Features 1-41.2 ZiVA-5P+ Features 1-51.3 ZiVA5X+ Features 1-62.1 ZiVA-5+ Processor Pin List 2-32.2 ZiVA-5+ Processor Pin Descriptions 2-122.3 Pins with Schmidt Trigger Inputs 2-222.4 Latch on Reset Pins 2-232.5 Sysclk Selection Options 2-262.6 Multiplexed Signal Assignments 2-273.1 Absolute Maximum Ratings 3-13.2 Recommended Operating Conditions 3-23.3 DC Characteristics 3-33.4 ZiVA-5+ Electrical Characteristic Summary,

Arranged by Signal Name 3-43.5 Global Interface AC Timing Parameters 3-83.6 SDRAM Timing Parameters 3-93.7 Async Master Timing Parameters 3-133.8 PIO Data Transfer Cycle Times 3-153.9 Single-word DMA Transfer Cycle Times 3-163.10 IDC Interface Timing Parameters 3-173.11 PCM Audio Interface Timing Parameters 3-183.12 Video Interface Timing Parameters 3-233.13 SPI Interface Timing Parameters 3-25

ZiVA-5+ Stream Data Port Advance Technical Manual 1-1Advance Copyright © 2002 by LSI Logic Corporation. All rights reserved.


Chapter 1Introduction

This section introduces the ZiVA-5+ features and functionality. It containsthe following sections:

• Section 1.1, “Features,” page 1-1

• Section 1.2, “Block Diagram,” page 1-7

1.1 Features

Building from the feature-rich and mature ZiVA A/V core, the ZiVA-5 DVDSystem Processor incorporates powerful new features based on theintegration of many DVD system components.

• High-performance 32-bit SPARC CPU with DSP Extensions

The ZiVA-5 incorporates a high-performance 32-bit SPARC hostCPU for audio processing and special features. The SPARC CPUincorporates dual execution units with dual instruction issueoperating at speeds up to 148.5 MHz, making it a superior platformfor applications development. The SPARC CPU is designed to act asthe system host processor, thus removing the requirement for anexternal host CPU with associated memory.

• Track Buffer Processor

An integrated Track Buffer Processor parses, frames, and performserror processing on all DVD and CD sector types. It also managesthe track buffer in ZiVA-5 unified local memory, thereby reducingmemory requirements of the DVD drive.

• Flexible DVD Drive Interface

The DVD drive input of the ZiVA-5 device is highly configurable andcan support most serial stream and parallel stream type drives, aswell as EIDE (ATAPI) drives. The combination of this flexible interface


1-2 IntroductionAdvance Copyright © 2002 by LSI Logic Corporation. All rights reserved.

with the SPARC CPU, many on-chip peripherals, and GeneralPurpose I/O (GPIO) pins enables direct interface to DVD drive servoelectronics for overall lower cost and better performing systems.

• High-performance 32-bit 2-D Graphics Processor

ZiVA-5 includes a high-performance 32-bit 2-D graphics processorthat can be used for ergonomic, next-generation graphical userinterfaces (GUIs) as well as graphics-based applications, includingInternet browsers, games, picture browsers, and other third partyapplications.

• Enhanced Video Encoder with High Precision Video DACs

ZiVA-5 incorporates an enhanced video encoder with five 54 MHzhigh precision video DACs to provide high-quality video. The videoencoder supports PAL, NTSC, RGB, SCART, interlaced 480I andprogressive 480P YPbPr components, and is fully programmable forcolor saturation, contrast, brightness, and sharpness. The videoencoder is compliant with both Macrovision 7.1.L.1 for interlacedvideo (PAL, NTSC) and Macrovision AGC 1.03 for Progressive scan(480P).

• On-chip Peripherals

On-chip peripherals include Inter-Device Communications (IDC)master/slave interface, two standard UARTs, SPI, and a direct multi-mode infrared (IR) input. All peripheral interfaces can be configuredas GPIO pins for added flexibility.

• Copy Protection

In addition to CSS, ZiVA-5 provides Copy Protection for Pre-recordedMedia (CPPM), Copy Protection for Recorded Media (CPRM), andaudio watermark detection, all of which are required for DVD-Audio.It is fully compatible with DVD-Video, DVD-Audio, Chaoji-VCD (CVD),SuperVCD, VCD, CD-DA, and CD-ROM formats such as MP3.

• Unified Memory Architecture

The Unified Memory Architecture (UMA) ensures the lowest possiblesystem memory cost by replacing various memory subsystems witha single subsystem. ZiVA-5 also has a flexible bus interface forglueless connection to a number of device types including EIDE,Flash memory, ROM, and RAM.


Features 1-3Advance Copyright © 2002 by LSI Logic Corporation. All rights reserved.

• C-Ware Software Development Platform

ZiVA-5 provides a platform for applications development based onC-Cube’s modular, component-based middleware (C-Ware) thatenables reuse of applications across LSI Logic SPARC-basedproducts. The Real Time Operating System (RTOS) component ofC-Ware is Wind River’s VxWorks, used in conjunction with WindRiver’s Tornado II software development environment. By enablingsoftware reuse, design cycles are considerably shortened andadvanced features can be quickly enabled.



Table 1.1 ZiVA-5M+ Features

Video

Decoding Standards MPEG-1, MPEG-2

CompressedResolutions

720 x 480 @ 30 Hz, 720 x 576 @ 25 Hz480 x 576 @ 25 Hz352 x 480 @ 30 Hz, 352 x 576 @ 25 Hz352 x 240 @ 30 Hz, 352 x 288 @ 25 Hz

Formats NTSC, PAL, CCIR 601/656

Compatibility DVD, DVD-VR, Chaoji VCD, VideoCD, S-VCD

Content Protection CSS

Graphics Processor Multiple planes/color modes, mixing, cursor, scaling

Audio

Decoding Standards MPEG-1 and -2, Layers I, II, and III (MP3), MPEG-2 5.1, Dolby DigitalClass A, DTS, Pro Logic, and HDCD

Input Channel IDS, IEC958

Output Channels 2-channel to 8-channel PCM output and IEC-1937/1958

Content Protection N/A

Sample Rates MPEG-1, MPEG-2, Dolby Digital, DTS

System

Compressed Data Input 8-bit DVD, Serial DVD, Serial CD w/Subcode, 16-bit Host and ATAPI

Peripheral Interfaces Two 16550 UARTs, SPI, IR, IDC, IEC 958 inputs, GPIO, Asynchronous BusInterfaces

DVD Drive ATAPI, UDE, VSTEM and other parallel/serial interfaces

Memory 32 to 128 Mbits SDRAM, 32 bits wide

Physical

Operating Voltage 3.3-V I/O (5-V tolerant), 1.8-V core

Clock Frequencies Input Frequency = 13.5 MHz, Operating = up to 148.5 MHz

Packaging 208-pin PQFP


Features 1-5Advance Copyright © 2002 by LSI Logic Corporation. All rights reserved.

.

.

Table 1.2 ZiVA-5P+ Features

Video




Formats NTSC, PAL, 480P, CCIR 601/656

Compatibility DVD, DVD-VR, Chaoji VCD, VideoCD, S-VCD



Audio

Decoding Standards MPEG-1 and -2, Layers I, II, and III (MP3), MPEG-2 5.1, Dolby DigitalClass A, DTS, Pro Logic, and HDCD



Content Protection N/A

Sample Rates MPEG-1, MPEG-2, Dolby Digital, DTS

System

Compressed Data Input 8-bit DVD, Serial DVD, Serial CD w/Subcode, 16-bit Host, and ATAPI

Peripheral Interfaces Two 16550 UARTs, SPI, IR, IDC, IEC 958 Inputs, GPIO, Asynchronous BusInterfaces

DVD Drive ATAPI, UDE, VSTEM and other parallel/serial interfaces


Physical






Table 1.3 ZiVA5X+ Features

Video




Formats NTSC, PAL, 480P, CCIR 601/656

Compatibility DVD, DVD-VR, Chaoji VCD, VideoCD, S-VCD, DVD Audio



Audio

Decoding Standards MPEG-1 and -2, Layers I, II, and III (MP3), MPEG-2 5.1, Dolby DigitalClass A, MLP, DTS, Pro Logic, and HDCD



Content Protection Watermark detection and CPPM for DVD-Audio

Sample Rates MPEG-1, MPEG-2, Dolby Digital, DTS and DVD-Audio up to 192 kHz

System

Compressed Data Input 8-bit DVD, serial DVD, serial CD w/ subcode, 16-bit host and ATAPI

Peripheral Interfaces Two 16550 UARTs, SPI, IR, IDC, IEC 958 inputs, GPIO, Asynchronous BusInterfaces

DVD Drive ATAPI, UDE, VSTEM, and other parallel/serial interfaces


Physical





Block Diagram 1-7Advance Copyright © 2002 by LSI Logic Corporation. All rights reserved.

1.2 Block Diagram

Figure 1.1 shows a high-level block diagram of the ZiVA-5 functionality.

Figure 1.1 Block Diagram

13.5 MHz Crystal

Bus Interface Unit

32-bit SPARCMicroprocessor

+Audio DSP

PhaseLockLoopIDC

SDRAM Controller

AudioOutput

Unit

JTAG

DVD DriveParallel/Serial

IDS Stereo In

IEC958/1937

Digital Video

LPCM 8-chAudio Out

ZiVAA/V CoreAudio

Input Unit

DecryptionTrack BufferProcessor NTSC/PAL/480P

Video Encoderwith

TrueScanDe-Interfacer

CompositeY/R

Cr/Pr/GCb/Pb/B

CFive 10-bit

VideoDACs

CCIR 656

ASYNC BUS

SDRAM (64/128Mbits)

UARTs IR EIDE GPIO SPI

Multi-Plane2D

GraphicsEngine

Interface

LS

IL

og

icC

on

fid

ential

Block

Diagram

1-8A

dvanceC

opyright©

2002by

LSI

LogicC

orporation.A

llrights

reserved.

Figure 1.2 Enhanced Block Diagram

Multi Plane2D

GraphicsEngine

Video DACs10-bit

NTSC/PAL/480PVideo Encoder

32-bit SPARCMicroprocessor+Audio DSP

Audio OutputUnit

Phase LockLoop

JTAGInterface

UARTs

HOSTInterface

IDC GPIO SPI

IR

Audio InputUnit

SUBCODE_SYNCV4SUBCODE

IIS_ERROR

BIT_CLK

SDREQ

175

176

178

Track BufferProcessor

DAI_DATA 157DAI_BCK 158

DAI_LRCK 159

IRRX 28

RT

S1

162R

XD

1163

TX

D1

164

CT

S1

165

RT

S2

185R

XD

2186

TX

D2

187

CT

S2

188

IDC

_CL

160ID

C_D

A161

GP

IO

SP

I_CLK

185

SP

I_MIS

O186

SP

I_MO

SI

187S

PI_C

S188

XOUT

XIN

138

139

TMS

TCK

200

201

TDO

TDI

198

199

TRST197

XCK

IEC958

147

156

BCK

LRCK

149

148

ADATA[3:0]150 151 154 155

VDAC_[4:0]119 122 125 128 131

VSYNC184

VCLK

VDATA[7:0]

105

106-110 113-115

HSYNC116

HDTACK

HIRQ0

23

24

HA[3:1]

HD[15:0]

206 207 2

3-11 14-19 22

HCS[4:0] 191-195

HREAD

ALE

27

190

HUDS/HLDS 25 26

VDAC_[4B:0B]117 120 123 126 129

VDAC_REF135

VDAC_REFVSS136

VDAC_DVSS132

VDAC_REFVDD134

VDAC_DVDD133

VDD_VDAC[4:0]118 121 124 127 130

XVDD

XVSS

140

137

A_VDD[2:1]

AVSS[2:1]

142 143

141 144

VDDP 12 20 111 152 167 181 196VDD 30 80 145 173 205

GNDP 13 21 112 153 166 180 208

GND 29 79 146 172 204

GND2531 43 54 61

VDD2574 87 98 104

72 85 96 103

CopyEngine

32 44 55 63

VNW 189

RESET 202

SDRAM Controller

MC

AS

52

MC

S[1:0]

50 49

MR

AS

51

MD

QM

[3:0]97 8673 62

MA

[11:0]33-4246 45

MD

[31:0]71-6478-7584-8195-88102-99

60-57

MW

E53

MC

LK56

BA

[1:0]47 48

Decryption

ZiVA A/VCore

Memory

Control

BUSCLK 203

LR_CLK

SDATA

174

171

170

177

RERR 168

SDATA 182LR_CLK 179NVERR 169

BIT_CLK 183



Chapter 2Pin and SignalDescriptions

This section lists the ZiVA-5+ pin-out and signal descriptions. It containsthe following sections:

• Section 2.1, “Pin Descriptions,” page 2-1

• Section 2.2, “Signal Descriptions,” page 2-12

2.1 Pin Descriptions

The ZiVA-5+ processor is packaged in a 208-pin Plastic Quad Flat Pack(PQFP) package. Figure 2.1 shows the pin-out and Table 2.1 lists the pinnumber, pin name, I/O voltage and I/O type.


2-2 Pin and Signal DescriptionsAdvance Copyright © 2002 by LSI Logic Corporation. All rights reserved.

Figure 2.1 ZiVA-5+ Processor Pinout (208-pin PQFP)

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152

53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

101

102

103

104

156155154153152151150149148147146145144143142141140139138137136135134133132131130129128127126125124123122121120119118117116115114113112111110109108107106105

VDD33HA1

HD15HD14HD13HD12HD11HD10HD9HD8HD7

VDD33GNDP

HD6HD5HD4HD3HD2HD1

VDD33GNDP

HD0HDTACK

HIRQ0HUDSHLDS

HREADIRRX1

GNDVDD

GND25VDD25

MA9MA8MA7MA6MA5MA4MA3MA2MA1MA0

GND25VDD25

MA10MA11

BA1BA0

MCS0MCS1MRASMCAS

IEC958ADATA3ADATA2GNDPVDD33ADATA1ADATA0BCKLRCKXCKGNDVDDAVSS1AVDD1/2AVSS2/3AVDD3XVDDXINXOUTXVSSVSS_REFVSSVDAC_REFVDAC_REFVDDVDAC_DVDDVDAC_DVSSVDAC_0VDAC_VDD0VDAC_0BVDAC_1VDAC_VDD1VDAC_1BVDAC_2VDAC_VDD2VDAC_2BVDAC_3VDAC_VDD3VDAC_3BVDAC_4VDAC_VDD4VDAC_4BHSYNCVDATA0VDATA1VDATA2GNDPVDD33VDATA3VDATA4VDATA5VDATA6VDATA7VCLK

ZiVA-5+ ProcessorTop View

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

GN

DP

HA

2H

A3

VD

DG

ND

BU

SC

LKR

ES

ET

TC

KT

MS

TD

IT

DO

TR

ST

VD

D33

HC

S0

HC

S1

HC

S2

HC

S3

HC

S4

ALE

VN

WC

TS

2/S

PI_

CS

TX

D2/

SP

I_M

OS

IR

XD

2/S

PI_

MIS

OR

TS

2/S

PI_

CLK

VS

YN

C/H

IRQ

1S

DC

LK/B

IT_C

LKS

DE

RR

OR

/SD

ATA

VD

D33

GN

DP

SD

EN

/LR

_CLK

SD

RE

QS

DD

ATA

0/S

DAT

AS

DD

ATA

1/LR

_CLK

SD

DAT

A2/

BIT

_CLK

SD

DAT

A3/

IIS_E

RR

OR

VD

DG

ND

SD

DAT

A4/

V4S

YN

CS

DD

ATA

5/H

DM

AC

K/S

UB

CO

DE

_SY

NC

SD

DAT

A6/

HX

CV

R_E

N/N

VE

RR

SD

DAT

A7/

HD

MA

RQ

/RE

RR

VD

D33

GN

DP

CT

S1

TX

D1

RX

D1

RT

S1

IDC

_DA

IDC

_CL

DA

I_LR

CK

/IEC

958B

PD

AI_

BC

KD

AI_

DAT

A

MW

EG

ND

25V

DD

25M

CLK

MD

0M

D1

MD

2M

D3

GN

D25

MD

QM

0V

DD

25M

D4

MD

5M

D6

MD

7M

D8

MD

9M

D10

MD

11G

ND

25M

DQ

M1

VD

D25

MD

12M

D13

MD

14M

D15

GN

DV

DD

MD

16M

D17

MD

18M

D19

GN

D25

MD

QM

2V

DD

25M

D20

MD

21M

D22

MD

23M

D24

MD

25M

D26

MD

27G

ND

25M

DQ

M3

VD

D25

MD

28M

D29

MD

30M

D31

GN

D25

VD

D25


Pin Descriptions 2-3Advance Copyright © 2002 by LSI Logic Corporation. All rights reserved.

Table 2.1 lists the 208 ZiVA-5+ pins in numerical order and shows thename for each pin.

Table 2.1 ZiVA-5+ Processor Pin List

PinNumber Pin Name I/O Voltage I/O Type

1 VDD33 3.3 V –

2 HA1 3.3 V1 I/O

3 HD15 3.3 V1 I/O

4 HD14 3.3 V1 I/O

5 HD13 3.3 V1 I/O

6 HD12 3.3 V1 I/O

7 HD11 3.3 V1 I/O

8 HD10 3.3 V1 I/O

9 HD9 3.3 V1 I/O

10 HD8 3.3 V1 I/O

11 HD7 3.3 V1 I/O

12 VDD33 3.3 V1 –

13 GNDP Ground –

14 HD6 3.3 V1 I/O

15 HD5 3.3 V1 I/O

16 HD4 3.3 V1 I/O

17 HD3 3.3 V1 I/O

18 HD2 3.3 V1 I/O

19 HD1 3.3 V1 I/O

20 VDD33 3.3 V –

21 GNDP Ground –

(Sheet 1 of 9)



22 HD0 3.3 V1 I/O

23 HDTACK 3.3 V1 I/OD

24 HIRQ0 3.3 V1 I

25 HUDS 3.3 V1 O

26 HLDS 3.3 V1 O

27 HREAD 3.3 V1 O

28 IRRX1/GPIO_0[1] 3.3 V1 I

29 GND Ground –

30 VDD 1.8 V –

31 GND25 Ground –

32 VDD25 3.3 V –

33 MA9 3.3 V O

34 MA8 3.3 V O

35 MA7 3.3 V O

36 MA6 3.3 V O

37 MA5 3.3 V O

38 MA4 3.3 V O

39 MA3 3.3 V O

40 MA2 3.3 V O

41 MA1 3.3 V O

42 MA0 3.3 V O

43 GND25 Ground –

44 VDD25 3.3 V –

45 MA10 3.3 V O

Table 2.1 ZiVA-5+ Processor Pin List (Cont.)


(Sheet 2 of 9)



46 MA11 3.3 V O

47 BA1 3.3 V O

48 BA0 3.3 V O

49 MCS0 3.3 V O

50 MCS1 3.3 V O

51 MRAS 3.3 V O

52 MCAS 3.3 V O

53 MWE 3.3 V O

54 GND25 Ground –

55 VDD25 3.3 V –

56 MCLK – O

57 MD0 3.3 V I/O

58 MD1 3.3 V I/O

59 MD2 3.3 V I/O

60 MD3 3.3 V I/O

61 GND25 Ground –

62 MDQM0 3.3 V O

63 VDD25 3.3 V –

64 MD4 3.3 V I/O

65 MD5 3.3 V I/O

66 MD6 3.3 V I/O

67 MD7 3.3 V I/O

68 MD8 3.3 V I/O

69 MD9 3.3 V I/O



(Sheet 3 of 9)



70 MD10 3.3 V I/O

71 MD11 3.3 V I/O

72 GND25 Ground –

73 MDQM1 3.3 V O

74 VDD25 3.3 V –

75 MD12 3.3 V I/O

76 MD13 3.3 V I/O

77 MD14 3.3 V I/O

78 MD15 3.3 V I/O

79 GND Ground –

80 VDD 1.8 V –

81 MD16 3.3 V I/O

82 MD17 3.3 V I/O

83 MD18 3.3 V I/O

84 MD19 3.3 V I/O

85 GND25 Ground –

86 MDQM2 3.3 V O

87 VDD25 3.3 V –

88 MD20 3.3 V I/O

89 MD21 3.3 V I/O

90 MD22 3.3 V I/O

91 MD23 3.3 V I/O

92 MD24 3.3 V I/O

93 MD25 3.3 V I/O



(Sheet 4 of 9)



94 MD26 3.3 V I/O

95 MD27 3.3 V I/O

96 GND25 Ground –

97 MDQM3 3.3 V O

98 VDD25 3.3 V –

99 MD28 3.3 V I/O

100 MD29 3.3 V I/O

101 MD30 3.3 V I/O

102 MD31 3.3 V I/O

103 GND25 Ground –

104 VDD25 3.3 V –

105 VCLK 3.3 V1 I/O

106 VDATA7/GPIO_1[8] 3.3 V1 I/O

107 VDATA6/GPIO_1[7] 3.3 V1 I/O

108 VDATA5/GPIO_1[6] 3.3 V1 I/O

109 VDATA4/GPIO_1[5] 3.3 V1 I/O

110 VDATA3/GPIO_1[4] 3.3 V1 I/O

111 VDD33 3.3 V –

112 GNDP Ground –

113 VDATA2/GPIO_1[3] 3.3 V1 I/O

114 VDATA1/GPIO_1[2] 3.3 V1 I/O

115 VDATA0/GPIO_1[1] 3.3 V1 I/O

116 HSYNC/HIRQ2/GPIO_1[9] 3.3 V1 I/O

117 VDAC_5B Analog O



(Sheet 5 of 9)



118 VDAC_VDD5 3.3 V Analog –

119 VDAC_5 Analog O



122 VDAC_4 Analog O



125 VDAC_3 Analog O



128 VDAC_2 Analog O



131 VDAC_0 Analog O

132 VDAC_DVSS Ground –

133 VDAC_DVDD 3.3 V –

134 VAC_REFVDD 3.3 V –

135 VDAC_REF Analog I

136 VDAC_REFVSS Ground –

137 XVSS Ground –

138 XOUT Analog –

139 XIN Analog –

140 XVDD 3.3 V –

141 AVSS2 Ground –



(Sheet 6 of 9)



142 AVDD2 3.3 V –

143 AVDD1 3.3 V –

144 AVSS1 Ground –

145 VDD 1.8 V –

146 GND Ground –

147 XCK 3.3 V1 I/O

148 LRCK 3.3 V1 O

149 BCK 3.3 V1 O

150 ADATA0/GPIO_4[1] 3.3 V1 O

151 ADATA1/GPIO_4[2] 3.3 V1 O

152 VDD33 3.3 V –

153 GNDP Ground –

154 ADATA2/GPIO_4[3] 3.3 V1 O

155 ADATA3/GPIO_4[4] 3.3 V1 O

156 IEC958/GPIO_4[5] 3.3 V1 O

157 DAI_DATA/GPIO_4[8] 3.3 V1 I

158 DAI_BCK/GPIO_4[7] 3.3 V1 I

159 DAI_LRCK/iec958bp/GPIO_4[6] 3.3 V1 I

160 IDC_CL/GPIO_2[11] 3.3 V1 OD

161 IDC_DA/GPIO_2[10] 3.3 V1 OD

162 RTS1/GPIO_3[11] 3.3 V1 O

163 RXD1/GPIO_3[14] 3.3 V1 I

164 TXD1/GPIO_3[13] 3.3 V1 O

165 CTS1/GPIO_3[12] 3.3 V1 I



(Sheet 7 of 9)



166 GNDP Ground –

167 VDD33 3.3 V –

168 SDDATA7/HDMARQ/RERR/GPIO_5[8] 3.3 V1 I

169 SDDATA6/HXCVR_EN/NVERR/GPIO_5[7]

3.3 V1 I

170 SDDATA5/HDMACK/SUBCODE_SYNC/GPIO_5[6]

3.3 V1 I

171 SDDATA4/V4SUBCODE/GPIO_5[5] 3.3 V1 I

172 GND Ground –

173 VDD 1.8 V –

174 SDDATA3/IIS_ERROR/GPIO_5[4] 3.3 V1 I

175 SDDATA2/BIT_CLK/GPIO_5[3] 3.3 V1 I

176 SDDATA1/LR_CLK/GPIO_5[2] 3.3 V1 I

177 SDDATA0/SDATA/GPIO_5[1] 3.3 V1 I

178 SDREQ/GPIO_5[9] 3.3 V1 O

179 SDEN/LR_CLK/GPIO_5[11] 3.3 V1 I

180 GNDP Ground –

181 VDD33 3.3 V –

182 SDERROR/SDATA/GPIO_5[10] 3.3 V1 I

183 SDCLK/BIT_CLK/GPIO_5[12] 3.3 V1 I

184 VSYNC/HIRQ1/GPIO_1[10] 3.3 V1 I/O

185 RTS2/SPI_CLK/GPIO_2[12] 3.3 V1 O

186 RXD2/SPI_MISO/GPIO_2[15] 3.3 V1 I

187 TXD2/SPI_MOSI/GPIO_2[14] 3.3 V1 O

188 CTS2/SPI_CS/GPIO_2[13] 3.3 V1 I



(Sheet 8 of 9)



189 VNW2 5 V –

190 ALE 3.3 V1 O

191 HCS4/GPIO_1[12] 3.3 V1 I

192 HCS3/GPIO_1[11] 3.3 V1 I

193 HCS2/GPIO_3[15] 3.3 V1 I

194 HCS1 3.3 V1 I/O

195 HCS0 3.3 V1 I/O

196 VDD33 3.3 V –

197 TRST 3.3 V1 I

198 TDO 3.3 V1 O

199 TDI/GPI5[14] 3.3 V1 I

200 TMS/GPI5[13] 3.3 V1 I

201 TCK 3.3 V1 I

202 RESET 3.3 V1 I

203 BUSCLK 3.3 V1 I

204 GND Ground –

205 VDD 1.8 V –

206 HA3 3.3 V1 I

207 HA2 3.3 V1 I

208 GNDP Ground –

1. 5 V-tolerant.2. The ZiVA-5+ core operates at 1.8 V + 5%. Most I/O interface pins can be

5 V-tolerant depending on the voltage applied to VNW.



(Sheet 9 of 9)



2.2 Signal Descriptions

Table 2.2 lists the pin name, pin number, type, and description of eachsignal.

Table 2.2 ZiVA-5+ Processor Pin Descriptions

PinNumber Name Type1 Description

System Services

203 BUSCLK I/O Synchronous Input/Output Signal ClockWhen set as an input, this pin requires an externalclock that synchronizes internal ZiVA-5+ logic toexternal bus events. All the synchronous bus signalsinput to the ZiVA-5+ are latched on the rising edge ofBUSCLK.When set as an output, the internal halfsysclk ispresent on this pin. The halfsysclk timing, however, isdelayed sufficiently to compensate for the externaldelay of the ZiVA-5+ I/O cell and external loading.This ensures that the setup and hold timerequirements for synchronous signals are alwaysrelative to the signal present on the BUSCLK pin andnot the internal halfsysclk.

202 RESET I Active Low Reset. Assert for at least 5 milliseconds inthe presence of clock to reset the entire chip.

105 VCLK I/O Video clock that outputs 27 MHz

138 XOUT O Crystal output. When the internal DCXO is used, a13.5-MHz crystal should be connected between thispin and the XIN pin.

139 XIN I Crystal input. When the internal DCXO is used, a13.5-MHz crystal should be connected between thispin and the XOUT pin. When an external oscillator orVCXO is used, its output should be connected to thispin.

Power and Ground

189 VNW Power 5-V supply voltage for 5 V-tolerant input signals

(Sheet 1 of 10)


Signal Descriptions 2-13Advance Copyright © 2002 by LSI Logic Corporation. All rights reserved.

1, 12, 20,111, 152,167, 181,196

VDD33 Power 3.3-V supply voltage for I/O signals

32, 44, 55,63, 74, 87,98, 104

VDD25 Power 3.3-V supply voltage for SDRAM I/O signals

140 XVDD Power 3.3-V Crystal interface power

30, 80,145, 173,205

VDD Power 1.8-V supply voltage for core logic

118, 121,124, 127,130

VDAC_VDD[5:1] Power 3.3-V Analog Video DAC Power

133 VDAC_DVDD Power 3.3-V Digital supply for 5 DACs

142, 143 AVDD[2:1] Power 3.3-V Analog PLL Power

134 VDAC_REFVDD Power 3.3-V Analog Video Reference Voltage

13, 21,112, 153,166, 180,208

GNDP Ground Ground for I/O signals

29, 79,146, 172,204

GND Ground Ground for core logic

31, 43, 54,61, 72, 85,96, 103

GND25 Ground Ground for SDRAM I/O signals

132 VDAC_DVSS Ground Digital VSS for DACs

141, 144 AVSS[2:1] Ground Analog PLL Ground

136 VDAC_REFVSS Ground Video Analog Ground

137 XVSS Ground Crystal interface ground

Table 2.2 ZiVA-5+ Processor Pin Descriptions (Cont.)


(Sheet 2 of 10)



Host Interface

191-193 HCS[4:2] O Host chip select. Host asserts HCS to select theprocessor for a read or write operation. The fallingedge of this signal triggers the read or write operation.

GPIO_1[12], 1[11],3[15]

I/O General Purpose I/Os 1[12], 1[11 and 3[15],respectively.

194, 195 HCS[1:0] O Host chip select. Host asserts HCS to select theprocessor for a read or write operation. The fallingedge of this signal triggers the read or write operation.

206, 207, 2 HA[3:1] O Host (muxed address) address bus. 3-bit address busselects one of eight host interface registers. Thesesignals are not muxed in ATAPI mode.

3-11, 14-19, 22

HD[15:0] I/O HD[15:0] is the 16-bit (muxed address and data) hostdata bus. MSB of the 32-bit word is written first. Thehost also reads and writes the decoder internalregisters and local SDRAM/ROM via HA[7:0]. Thesesignals are not muxed for ATAPI mode.

23 HDTACK/WAIT OD/I Host Data Transfer Acknowledge

24 HIRQ0 I Host interrupt. Open drain signal, must be pulled-upvia 4.7 kΩ or 3.3 kΩ to 3.3 volts. Driven high for 10 nsbefore 3-state.

25 HUDS/UWE O Host Upper Data Strobe. Host high byte data,HD[15:8], is valid when this pin is active.

26 HLDS/LWE O Host Lower Data Strobe. Host low byte data, HD[7:0],is valid when this pin is active.

27 HREAD O Read/write strobe

190 ALE O Address latch enable



(Sheet 3 of 10)



Parallel DVD/CD or Serial CD Interface

168 SDDATA7 I Compressed data from DVD DSP. Bit 7. In parallelmode, bit 7 is the first (earliest in time) bit in thebitstream, while bit 0 is the last bit.

HDMARQ I Host DMA Request

RERR I Receiver Error input from SAA7812 or CS8415

GPIO_5[8] I/O General Purpose I/O 5[8]

169 SDDATA6 I Compressed data from DVD DSP. Bit 6

HXCVR_EN I ATAPI Transceiver Enable

NVERR I No Validity Receiver Indicator input from SAA7812 orCS8415



HDMACK I Host DMA Acknowledge

SUBCODE_SYNC I Sync input from SAA7812



V4SUBCODE I V4 input from SAA7812



IIS_ERROR I FLAG input from SAA7812




(Sheet 4 of 10)




BIT_CLK I BCLK input from SAA7812 or OSCLK input fromCS8415



LR_CLK I WCLK input from SAA7812 or OLRCK input fromCS8415


177 SDDATA0 I In serial mode, bit 0 should be used as the input, withthe unused bits either used as GPIOs or tied toground.

SDATA I DATA input from SAA7812 or SDOUT input fromCS8415


183 SDCLK I Data clock. The maximum frequency is 37.125 MHzfor parallel mode, and 74.25 MHz for serial mode. Thepolarity of this signal is programmable.

BIT_CLK I OSCLK input from CS8415 or bit clock input from anADC

182 SDERROR I Error in input data. This signal carries the error bitassociated with the channel data type (if set, the byteis corrupted).

SDATA I SDOUT input from CS8415 or audio serial data inputfrom an ADC




(Sheet 5 of 10)



179 SDEN I Data enable. Assertion indicates that data onSDDATA[7:0] is valid. The polarity of this signal isprogrammable.

LR_CLK I OLRCK input from CS8415 or left/right clock inputinput from an ADC


178 SDREQ O Bitstream request. processor asserts SDREQ toindicate that the bitstream input buffer has availablespace.


SDRAM Interface

50, 49 MCS[1:0] O Memory chip select for SDRAM.

52 MCAS O Active LOW SDRAM Column Address Strobe

51 MRAS O Active LOW SDRAM Row Address Strobe

97, 86, 73,62

MDQM[3:0] O These pins are the byte masks corresponding toMD[7:0], [15:8], [23:16] and [31:24]. They allow forbyte reads/writes to SDRAM.

46, 45, 33-42

MA[11:0] O SDRAM Address

102-99,95-88,84-81, 78-75, 71-64,60-57

MD[31:0] I/O SDRAM Data

53 MWE O SDRAM Write Enable. Specifies transaction toSDRAM: read (=1) or write (=0)

56 MCLK O SDRAM Clock

47, 48 BA[1:0] O SDRAM bank select



(Sheet 6 of 10)



Analog Video Output

117, 120,123, 126,129

VDAC_(5B:1B] Analog O Video DAC Bias Bits[4:0]

119 VDAC_5 Analog O DAC video output. Macrovision encoded





135 VDAC_REF Analog I Video DACs Reference Resistor. Connecting to pin136 through a 1.18 K +/- 1% resistor is required.

105 VCLK I/O System clock that drives internal PLLs. ZiVA-5+ 27-MHz TTL oscillator. (See description of VCLK forDigital Video Output.) Also optional video clock forinternal PLLs or external encoder.

Digital Video Input/Output

116 HSYNC I/O Horizontal sync. The decoder begins outputting pixeldata for a new horizontal line after the falling (active)edge of HSYNC.

HIRQ2 I Host Interrupt Request 2


105 VCLK I/O Video clock. Clocks out data on VDATA[7:0]. Clock istypically 27 MHz.

106-110,113-115

VDATA[7:0] I/O Video data bus. Byte serial CbYCrY data synchronouswith VCLK. At power-up, the decoder does not driveVDATA. During boot-up, the decoder samples VDATAfor boot configuration parameters.

GPIO_1[8:1] I/O General Purpose I/Os 1[8:1]



(Sheet 7 of 10)



184 VSYNC I/O Vertical sync. Bi-directional, the decoder outputs thetop border of a new field on the first HSYNC after thefalling edge of VSYNC. VSYNC can accept verticalsynchronization or top/bottom field notification from anexternal source. (VSYNC HIGH = bottom field.VSYNC LOW = top field) Used for CCIR-601.

HIRQ1 I Host Interrupt Request 1


Audio Interface

155, 154,151, 150

ADATA[3:0] O PCM Data Out. Eight channels. Serial audio samplesrelative to BCK and LRCK.

GPIO_4[4:1] I/O General Purpose I/Os 4[4:1]

149 BCK O PCM Bit Clock. This audio bit clock provides the serialshift clock for audio data. BCK can be either 48 or 32times the sampling frequency.

148 LRCK O PCM Sample Clock. Identifies the channel for eachsample. The polarity is programmable.

147 XCK I/O Audio system clock input or output. BCK and LRCKare derived from this clock.

156 IEC958 O PCM data out (IEC-958 format) or compressed dataout (IEC-1937 format).


Digital Mic In

157 DAI_DATA I PCM data (stereo) input.


158 DAI_BCK I PCM sample clock. Also slaves to external audioclock.




(Sheet 8 of 10)



159 DAI_LRCK I PCM left/right clock.

IEC958BP I IEC958 input bypass


IR

28 IRRX I IR Remote Receive. This input connects to anintegrated (photo diode, band pass, demodulator) IRreceiver.


IDC

160 IDC_CL OD Serial clock signal for IDC data transfer. It should bepulled up to the positive supply voltage (depending onthe device) using an external pull-up resistor.


161 IDC_DA OD Serial data signal for IDC data transfer. It should bepulled up to the supply voltage using an external pull-up resistor.


UART1

162 RTS1 O Ready to send, UART1


163 RXD1 I Receive data, UART1


164 TXD1 O Transmit data, UART1


165 CTS1 I Clear to send, UART1




(Sheet 9 of 10)



UART2

185 RTS2 O Ready to send, UART2

SPI_CLK O Serial Peripheral Interface Clock


186 RXD2 I Receive data, UART2

SPI_MISO I Serial Peripheral Interface - Master In Slave Out


187 TXD2 O Transmit data, UART2

SPI_MOSI O Serial Peripheral Interface - Master Out Slave In


188 CTS2 I Clear to send, UART2

SPI_CS O Serial Peripheral Interface Strobe


JTAG

197 TRST I Test reset. BST reset. Resets the TAP controller. Thissignal must be pulled low.

198 TDO O Test data Out. BST serial data output.

199 TDI I Test data In. BST serial data chain input.

GPI_5[14] I General Purpose Input pin 0

200 TMS I Test mode select. Controls state of test access port(TAP) controller.

GPI_5[13] I General Purpose Input pin 1

201 TCK I Test clock. Boundary scan test (BST) serial dataclock.

1. I - input; O - output; OD - open drain; PU - requires external pull-up resistor.



(Sheet 10 of 10)



Table 2.3 lists the pins that have Schmidt Trigger inputs.

Table 2.3 Pins with Schmidt Trigger Inputs

Pin Number Pin Name Pin No. Pin Name

2-11 HA1, HA[15:7] 165 CTS1

14-19 HD[6:1] 168-171, 174-177 SDDATA[70]

22 HD0 178 SDREQ

23 HDTACK 179 SDEN

24 HIRQ0 182 SDERROR

25 HUDS 183 SDCLK

26 HLDS 184 VSYNC

27 HREAD 185 RTS2

28 IRRX1 186 RXD2

106-110 VDATA[7:3] 187 TXD2

113-115 VDATA[2:0] 188 CTS2

116 HSYNC 191 HCS4

147 XCK 192 HCS3

150, 151, 154, 155 ADATA[0:3] 193 HCS2

156 IEC958 194 HCS1

157 DAI_DATA 195 HCS0

158 DAI_BCK 197 TRST

159 DAI_LRCK 199 TDI

160 IDC_CL 200 TMS

161 IDC_DA 201 TCK

162 RTS1 202 RESET

163 RXD1 206 HA3

164 TXD1 207 HA2



2.2.1 Latch On Reset (LOR) Signals

There are a number of Latch On Reset (LOR) pins on the ZiVA-5+ thatare used to enable particular modes and/or features of the part. Thelatch on reset pins used on the ZiVA-5+ are shown in Table 2.4.

All LOR pins are input-only pins that have weak internal pull-up or pull-down resistors. The latching signal is not a clock signal but rather anasynchronous version of the reset signal. The state for the LOR pins isheld in a transparent latch that is transparent while the asynchronousreset is asserted and becomes opaque when the synchronous reset isdeasserted.

LOR pins are programmed by adding either weak pull-up resistors (= 1)or weak pull-down resistors (= 0) to these pins. These resistors shouldbe weak enough that they can be over driven in normal operation.

The LOR pins are all multiplexed with other signal functions. The timingof the LOR function requires that all other functions allow a minimum of21 system clock (sysclk) cycles after the rising (positive) edge of thereset pulse (active low) before using the LOR pins for the other signalfunction(s).

Table 2.4 Latch on Reset Pins

Pin Number LOR Name

148 host_drive_sel

150 clk_speed_sel0

151 clk_speed_sel1

154 clk_speed_sel2



2.2.2 Latch On Reset Signal Descriptions

The following sections briefly describe the Latch On Reset (LOR) signalsused by the ZiVA-5+ device.

2.2.2.1 Chip Mode Selection (chip_mode_sel[2:0])

The chip mode selection pins determine the ZiVA-5+ device’s operatingmode. These should always be configured to the Async Mode (110) asfollows:

bit 2 = 1bit 1 = 1bit 0 = 0

The chip mode selection pins are multiplexed as follows:

bit 2 is multiplexed with TXD2bit 1 is multiplexed with RTS1bit 0 is multiplexed with TXD1

2.2.2.2 Host Drive Selection (host_drive_sel)

The host_drive_sel signal goes to the host interface I/Os to select highdrive or low drive I/Os. When latched at 0, high drive I/Os are used; whenlatched at 1, low drive I/Os are used. This signal is also multiplexed withLRCK.

155 xtal_sel

156 bypass_sel

162 chip_mode_sel1

164 chip_mode_sel0

185 Reserved1

187 chip_mode_sel2

1. Although reserved for future use, this pin must be tied high. A 10K resistoris recommended, but variations in loads may require adjustments.

Table 2.4 Latch on Reset Pins

Pin Number LOR Name



It is recommended that the host_drive_sel signal should always belatched at 1 to enable the low drive I/Os.

2.2.2.3 Clock Generation LOR Signals

The PLL subsystem is responsible for generating the system, video, andaudio clocks for the chip. This is achieved using three PLLs and ahandful of support logic. The primary system clock, sysclk, runs at 108.0,121.5, 135, or 148.5 MHz. sysclk can be locked to either a pullableexternal 13.5-MHz crystal or an external 27-MHz VCXO. A clock at halfthe selected rate, halfsysclk, is generated by dividing sysclk. Three videoclocks are generated by/derived from the video PLL, a 27-MHz clocknamed clk_27, a 54-MHz clock named clk_54, and a 216-MHz clocknamed clk_216. The video PLL can either share the same reference asthe system clock PLL or use a separate 27-MHz/54-MHz clock source(e.g. a digitizer). The audio PLL generates aclk, which can cover a widerange of oversampling rates due to the use of high resolution fractionalsynthesis. Like the video PLL, the audio PLL can either share the samereference as the system clock PLL or use an external 27-MHz/54-MHzreference.

2.2.2.4 Internal Reference Frequency Selection (xtal_sel)

The internal reference source is selected via the LOR signal xtal_sel(ADATA[3]). When latched at 1, the Digital Controlled Crystal Oscillator(DCXO) is enabled and a 13.5-MHz crystal is expected to be connectedbetween the XIN and XOUT pins. When xtal_sel is latched at 0, anexternal 27-MHz clock reference is expected at the XIN pin.

2.2.2.5 Sysclk (clk_speed_sel[2:0])

The sysclk PLL is always locked to the signal on the XIN pin (whetherthe signal is produced by the internal DCXO or an external oscillator).The sysclk frequency is determined at reset by the LOR signalsclk_speed_sel[2:0] (ADATA[1:3] pins). Table 2.5 shows the relationshipbetween clk_speed_sel[2:0] and sysclk. Since these values are latchedon reset, the chip must be reset in order to change the sysclk frequency.



2.2.3 Pin Multiplexing

Various I/O signals of the ZiVA-5+ are multiplexed, depending on whichexternal interfaces are implemented (implementing one interface maypreclude the use of another interface).

Other signals share pins with the Latch On Reset (LOR) signals. TheLOR signals set configurations parameters for the ZiVA-5+ device whenthe device is reset. However, LOR signals do not interfere with normaloperation of any interfaces or signals.

2.2.3.1 Primary And Secondary Signals

The signals being multiplexed can be classified in terms of primary andsecondary signals assigned to a particular set of pins. The scheme ispackage-dependent.

• The primary signals are those that are active when a primary signalis taken out of reset (by toggling the corresponding reset bit in areset register).

• The secondary signals can be made active by holding the primarysignal in reset and selecting the secondary signal (by setting thecorresponding select bit in a configuration register).

Table 2.6 shows the multiplexed primary and secondary signals of theZiVA-5+.

The primary and secondary signals are selected by firmware headerfiles. The scheme for selecting a particular signal is based on setting thecorresponding bit(s) in these registers. In these registers there may be1-, 2-, or 3-bit fields dedicated to selecting among muxed signals by

Table 2.5 Sysclk Selection Options

clk_speed_sel[2:0] sysclk in MHz

001 121.5

010 135.0

011 148.5



setting them to specific values. As an example, the signals VDATA[7:0]could be configured through firmware as GPIO signals.

Table 2.6 Multiplexed Signal Assignments

PrimarySignal Name

PinNumber

SecondarySignal Name

SecondarySignal Direction

SecondarySignal Module

ADATA[0] 150 clk_speed_sel0 Input PLL

GPIO_4 [1] Input/Output





ADATA[3] 155 xtal_sel Input PLL


CTS1 165 GPIO_3 [12] Input/Output

CTS2 188 SPI_CS Output SPI


DAI_BCK 158 GPIO_4 [7] Input/Output

DAI_DATA 157 GPIO_4 [8] Input/Output

DAI_LRCK 159 IEC958BP Input Audio


HCS[2] 193 GPIO_3 [15] Input/Output



HSYNC 116 HIRQ2 Input BIU


IDC_CL 160 GPIO_2 [11] Input/Output

IDC_DA 161 GPIO_2 [10] Input/Output

IEC958 156 bypass_sel Input PLL


IRRX1 28 GPIO_0 [1] Input/Output

LRCK 148 host_drive_sel Input BIU

RTS1 162 chip_mode_sel1 Input BIU, SRM




RTS2 185 SPI_CLK Output SPI

busclk_sel0 Input BIU


RXD1 163 GPIO_3 [14] Input/Output

RXD2 186 SPI_MISO Input SPI


SDCLK 183 BIT_CLK Input


SDDATA[0] 177 GPIO_5 [1] Input/Output

SDATA Input


LR_CLK Input


BIT_CLK Input


IIS_ERROR Input


V4SUBCODE Input


SUBCODE_SYNC Input

HDMACK Output BIU


NVERR Input

HXCVR_EN Output BIU


RERR Input

HDMARQ Input BIU

SDEN 179 GPIO_5 [11] Input/Output

LR_CLK Input

SDERROR 182 GPIO_5 [10] Input/Output

SDATA Input

SDREQ 178 GPIO_5 [9] Input/Output

Table 2.6 Multiplexed Signal Assignments (Cont.)

PrimarySignal Name

PinNumber






TDI 199 GPI_5 [14] Input

TMS 200 GPI_5 [13] Input

TXD1 164 chip_mode_sel0 Input BIU, SRM


TXD2 187 SPI_MOSI Output SPI

chip_mode_sel2 Input BIU, SRM


VDATA[0] 115 board_id_lor0 Input SRM
















VSYNC 184 HIRQ1 Input/Output BIU


Table 2.6 Multiplexed Signal Assignments (Cont.)

PrimarySignal Name

PinNumber






Chapter 3Specifications

This section describes the electrical characteristics, AC timingparameters/diagrams and package dimensions of the ZiVA-5+ device. Itcontains the following sections:

• Section 3.1, “Electrical Characteristics,” page 3-1

• Section 3.2, “AC Timing Diagrams,” page 3-8

• Section 3.3, “Package Mechanical Dimensions,” page 3-25

• Section 3.4, “Package Marking,” page 3-27

3.1 Electrical Characteristics

3.1.1 General Electrical Characteristics

Table 3.1 Absolute Maximum Ratings

Parameters Value1 Units

VDD Supply Voltage −0.3 to 3.465 V

VDDA Analog Supply Voltage −0.3 to 4.65 V

VIN Input Voltage −0.3 to 5.5 V

VOUT Output Voltage −0.3 to VDD +0.3 V

TSTG Storage Temperature Range −55 to 150 °C

TAmb Ambient Temperature Range (device) −0 to 60 °C

TSLD Reflow Soldering Temp. 200° C for five secondsmax.

–

1. Exposure to stresses beyond those listed in this table can result in device unreliability, permanentdamage, or both.


3-2 SpecificationsAdvance Copyright © 2002 by LSI Logic Corporation. All rights reserved.

Table 3.2 Recommended Operating Conditions

Parameters

Values1

UnitsMin Typ. Max

VDD Supply Voltage 1.71 1.8 1.89 V

VDDA Analog Supply Voltage 3.135 3.30 3.465 V

VNW 5-V Supply Voltage for 5 V-tolerant signals – 5.00 – V

VDD33 3.3-V Supply Voltage for I/O signals 3.135 3.30 3.465 V

VDD25 3.3-V Supply Voltage for SDRAM I/O signals 3.135 3.30 3.465 V

XVDD 3.3-V Crystal interface power 3.135 3.30 3.465 V

VDD_VDAC Analog Video DAC power 3.135 3.30 3.465 V

VDAC_DVDD 3.3-V Digital Supply Voltage for Video DACs 3.135 3.30 3.465 V

VDAC_REFVDD 3.3-V Analog Reference Voltage 3.135 3.30 3.465 V

TAMB Ambient Temperature (Device) 0 – 60 °C

1. Typical 5% on VDD supply. For normal device operation, adhere to these limits. Sustained oper-ation at conditions exceeding these values, even if they are within the absolute maximum ratinglimits, might result in permanent device damage or impaired device reliability. Device functionalityto stated DC and AC limits is not guaranteed if conditions exceed recommended operating condi-tions.


Electrical Characteristics 3-3Advance Copyright © 2002 by LSI Logic Corporation. All rights reserved.

Table 3.3 DC Characteristics

Parameters Test Conditions Min Typ. Max Units

VIH High-Level Input Voltage1 VDD = Max 2.4 – 3.45 V

VIL Low-Level Input Voltage1 VDD = Min – – 0.8 V

VOH High-Level OutputVoltage

VDD = Min,IOH = drive level of specific signalshown in Table 3.4.

2.4 – – V

VOL Low-Level Output Voltage VDD = MinIOL = drive level of specific signalshown in Table 3.4.

– – 0.5 V

IIH High-Level Input Current VDD = Max, VIN = VDD – – 10 µA

IIL Low-Level Input Current VDD = Max, VIN = 0 V −10 – – µA

IINU Input Current with Pull-upResistor

VIN = VSS -70 -225 µA

IOZ Output Leakage Current Hi-Z output driven to 0 V and 5.25 V −10 – +10 µA

IOZM Output Leakage Current,SDRAM pins

Hi-Z output driven to 0 V and VDD −10 – +10 µA

CIN Input Capacitance1 – 10 – pF

COUT Output Capacitance1 – 12 – pF

CI/O I/O Pin Capacitance1 – 12 – pF

PD Power Dissipation VDD Nominal @ 25 °C,Internal clock = 135 MHz

– 2.1 – W

1. Not 100% tested, guaranteed by design characteristics.



3.1.2 Electrical Characteristics Summary

Table 3.4 summarizes the electrical characteristics of ZiVA-5+ signals,including their direction (input, output, or input/output), their terminations,and their drive and voltage tolerance.

Table 3.4 ZiVA-5+ Electrical Characteristic Summary,Arranged by Signal Name

Signal Name Direction

SchmittTrigger(if shown) Drive V. Tolerance

ADATA [3:0] Output yes 6 ma 5 V

AVDD [3:1] – – – –

AVSS [3:1] – – – –

BA [1:0] Output – 15 ma 3.3 V

BCK Output – 6 ma 5 V

BUSCLK Input/Output – 12 ma 5 V

CTS1 Input yes 6 ma 5 V

CTS2 Input yes 6 ma 5 V

DAI_BCK Input yes 6 ma 5 V

DAI_DATA Input yes 6 ma 5 V

DAI_LRCK Input yes 6 ma 5 V

DATA_EN Output yes 6 ma 5 V

HA[3:1] Input/Output yes 6 ma 5 V

HCS[1:0] Input/Output yes 6 ma 5 V

HCS[3:2] Output yes 6 ma 5 V

HCS 4 Output yes 6 ma 5 V

HD[15:0] Input/Output yes 6 ma 5 V

HDMACK Output – 6 ma 5 V

(Sheet 1 of 4)



HDMARQ Input yes 6 ma 5 V

HDTACK I/OD1 yes 6 ma 5 V

HIRQ0 Input/Output yes 6 ma 5 V

HIRQ1 Input/Output yes 6 ma 5 V

HLDS Input/Output yes 6 ma 5 V

HREAD Input/Output yes 6 ma 5 V

HSYNC Input/Output yes 6 ma 5 V

HUDS Input/Output yes 6 ma 5 V

HXCVR_EN Output yes 6 ma 5 V

IDC_CL I/OD yes 6 ma 5 V

IDC_DA I/OD yes 6 ma 5 V

IEC958 Output yes 6 ma 5 V

IRRX1 Input yes 3 ma 5 V

LRCK Output – 6 ma 5 V

MA [11:0] Output – 15 ma 3.3 V

MCAS Output – 15 ma 3.3 V

MCLK Output – 36 ma 3.3 V

MCS[1:0] Output – 15 ma 3.3 V

MD[31:0] Input/Output – 15 ma 3.3 V

MDQM[3:0] Output – 15 ma 3.3 V

MRAS Output – 15 ma 3.3 V

MWE Output – 15 ma 3.3 V

Table 3.4 ZiVA-5+ Electrical Characteristic Summary,Arranged by Signal Name (Cont.)



(Sheet 2 of 4)



RESET Input yes 3 ma 5 V

RTS1 Output yes 6 ma 5 V

RTS2 Output yes 6 ma 5 V

RXD1 Input yes 6 ma 5 V

RXD2 Input yes 6 ma 5 V

SDCLK Input yes 6 ma 5 V

SDDATA [7:0] Input yes 6 ma 5 V

SDEN Input yes 6 ma 5 V

SDERROR Input yes 6 ma 5 V

SDREQ Output yes 6 ma 5 V

SPI_CLK Output – 6 ma 5 V

SPI_CS Output – 6 ma 5 V

SPI_MISO Input – 6 ma 5 V

SPI_MOSI Output – 6 ma 5 V

TCK Input yes 3 ma 5 V

TDI Input yes 3 ma 5 V

TDO Output – 3 ma 5 V

TMS Input yes 3 ma 5 V

TRST Input yes 3 ma 5 V

TXD1 Output yes 6 ma 5 V

TXD2 Output yes 6 ma 5 V

VCLK Input/Output – 12 ma 5 V




(Sheet 3 of 4)



VDAC_[4:0] Output – – –

VDAC_[4B:0B] – – – –

VDAC_DVDD – – – –

VDAC_DVSS – – – –

VDAC_REF Input – – –

VDAC_REFVDD – – – –

VDAC_REFVSS – – – –

VDAC_VDD [4:0] – – – 3.3 V

VDATA [7:0] Input/Output yes 6 ma 5 V

VDDCDL – – – –

VNW – – – –

VSYNC Input/Output yes 6 ma 5 V

XCK Input/Output yes 12 ma 5 V

XIN Input – – –

XOUT Output – – –

XVDD – – – –

XVSS – – – –

1. I/OD = Input / open drain output.




(Sheet 4 of 4)



3.2 AC Timing Diagrams

3.2.1 Global Interface Timing

Table 3.5, Figure 3.1, and Figure 3.2 specify AC timing parameters forZiVA-5+ signals on the global interface or parameters that apply tosignals on all interfaces.

Figure 3.1 Input Rise and Fall Timing Diagram

Figure 3.2 SYSCLK Timing Diagram

Table 3.5 Global Interface AC Timing Parameters

Symbol Description

Timing Value

UnitMin Max

A1 Input rise and fall time 3 – ns

A2 Reference input frequency (forall NTSC and PAL modes)

TBD MHz

A3 SYSCLK HIGH pulse width 0.45 * A2 0.55 * A2 ns

A4 SYSCLK LOW pulse width 0.45 * A2 0.55 * A2 ns

Input10%

90%

A1A1

90%

10%

SYSCLK

A2

A4A3


AC Timing Diagrams 3-9Advance Copyright © 2002 by LSI Logic Corporation. All rights reserved.

3.2.2 SDRAM Timing Diagrams

This section gives SDRAM device AC timing specifications. Thisspecification is defined for 100 MHz, 0, 0 clock tap settings, and 50-pfloading. The timing values in Table 3.6 assume a load on each outputfrom the ZiVA-5+ SDRAM interface, as shown in Figure 3.3. Timingdiagrams for the SDRAM interface are shown in Figure 3.4 andFigure 3.5.

Table 3.6 SDRAM Timing Parameters1

Symbol Mnemonic Description Min Max Unit

D1 tCK MCLK cycle 10 – ns

D2 tCH MCLK HIGH 3.5 – ns

D3 tCL MCLK LOW 3.5 – ns

D4 MCLK Programmable Delay = (X/256) •D1

N/A N/A ns

D5 tASU MCS[2:0), MRAS, MCAS, MWE,MS[11:0], BA[1:0] MDQM[3:0] SetupTime relative to MCLK

2.5 – ns

D6 tAH MCS[2:0), MRAS, MCAS, MWE,MS[11:0], BA[1:0] MDQM[3:0] Hold Timerelative to MCLK

2 – –

D7 tDS MD[31:0] in setup 2.5 – ns

D8 tDH MD[31:0] in hold 2.5 – ns

1. The timing parameters specified in this table are based on the clock tap settings of 0 for bothSDRAM_CLK_OUT and SDRAM_CLK_IN. Changing the tap setting changes the timing parame-ters. Please see application note TD10-1055 to recalculate parameters.



Figure 3.3 SDRAM Output Load

The timing of the SDRAM input and output clock (MCLK) is controlled byfields within the SDRAM Clock Control register (SCC). The valuesprogrammed into these fields are used to set the relative offset betweenthe clock on the external pin and the internal SYSCLK.

The three fields and the timing that they affect are:

• OutClkTapSel - This field sets the delay when MCLK is used as anoutput during Single Data Rate writes.

• InClkTapSel - This field sets the delay when MCLK is used as aninput during Single Data Rate reads. It is also used to control theoutput clock timing during Double Data Rate (DDR) writes.

• DDRTapSel - This field sets the delay between the MDQS signal andthe device strobe signal that is used to sample data read fromSDRAM in DDR mode only.

By programming these clock tap settings, the read and write timings canbe customized to accommodate all variations of SDRAM and boarddesign timing differences.

Z = 50 Ω

1.4 V

50 Ω

50 pF

Output



Figure 3.4 SDRAM Write Timing Waveform

Figure 3.5 SDRAM Read Timing Waveform

MCLK(OutTapSel=0)

MCLK(OutTapSel=X)

MCS[2:0], MRAS,MCAS, MWE,

MA[11:0],BA[1:0],

MDQM[3:0]

MD[31:0] (Write) Stable

D2D2

D3

D1

D5

D4

D5

D4

Stable

MCLK(OutTapSel=0)

MCLK(OutTapSel=X)

Stable

Stable

D2D2

D3

D1

Stable

D8

D6D7

D4D5MCS[2:0],

MRAS, MCAS,MWE, MA[11:0],

BA[1:0],MDQM[3:0]

MD[31:0] (Read)InClkTapSel=0

MD[31:0] (Read)InClkTapSel=Y



3.2.3 Async Master Personality Module Timing

Timing for the Async Master Personality Module is shown in Figure 3.6;the timing parameters are described in Table 3.7.

Figure 3.6 Async Master Timing

CSO

BDT

BH

BUSCLK

ADDR

R/W_n

CSOUT_n

UDS_n/LDS_n

DATA

DTack_n

CSOCSO BH

68K Mode Read 68K Mode Write 68K Mode Burst Read

BH

AS_n

1 1 1

DSODSODSO

DT DT DT



In the case of device-paced transfer, the peripheral generates theacknowledge signal after the MPM has placed all control signals on theexternal Host Bus. The external acknowledge signal is used as an inputto generate an internal DTACK_n signal in either synchronous orasynchronous mode.

Some devices require the host to wait an indefinite time for the transferto complete. These devices drive the HDTACK or WAIT signalthemselves, instead of relying on the host to self-time the transfer.

Besides these programmable parameters, the following additional timingparameters are assumed by default according to the processor:

• The time between address valid and assertion of AS_n is oneBUSCLK period.

Table 3.7 Async Master Timing Parameters

ParameterRange ofValues Description

CSO 0–7 clocks Delay from Addr and R/W stable to fall of CS. For write cycles, Data isdriven out along with fall of CS.

DSO 0–7 clocks Delay from Addr and R/W stable to fall of data strobes (UDS and LDS orOE, WEH and WEL).

DT 0–63 clocks For self-timed accesses, delay from Addr and R/W stable to HDTACK orasserted or WAIT deasserted. For self-timed accesses, HDTACK ispulsed low for one clock, then brought high for one clock before being3-stated whereas WAIT is driven low at the start of the cycle then broughthigh for one clock before being deasserted. On a read cycle, data islatched in at the end of the clock cycle where HDTACK is asserted orWAIT deasserted. For device-paced HDTACK transfers.For device-paced WAIT transfers, this value indicates the amount of timeto wait before sampling the WAIT pin for cycle completion.

BDT 0–3 clocks For self-timed burst accesses, delay from end of previous data transferphase to assertion of HDTACK or deassertion of WAIT for next phase.

BH 0–15 clocks Added delay from end of cycle (CS and data strobes deasserted) to startof next cycle. During the BH time, Addr and R/W are held stable and allother signals are held inactive. On a write cycle, the Data bus is alsodriven with the write data for the BH time.

AH 0–1 clock Multiplexed address hold time from fall of HTS to Addr/Data change.



• In case of writing, the R/W_n pin is made low one BUSCLK periodafter putting a valid address.

• The AS_n is negated along with negation of data strobe signals.

• In case of reading, the R/W_n pin is made high along with putting avalid address on the ADDR bus.

3.2.4 IDE Personality Module Timing

Figure 3.7 shows the timing diagram for the PIO data transfer cycle;Table 3.8 describes the timing parameters. Figure 3.8 shows the timingdiagram for a single-word PMA transfer cycle; Table 3.9 describes thetiming parameters.

Figure 3.7 IDE PIO Data Transfer Cycle

CS0/CS1

DIOR/DIOW

Data (Read)

Data (Write)

IOCS16

IORDY1

IORDY2

IORDY3

tA

tRD

t7t5

t6z

t6

t3 t4

t1 t2t9 t8

t0



Table 3.8 PIO Data Transfer Cycle Times

Symbol DescriptionTypicalTiming Value Units

t0 PIO Data Transfer Cycle Time 240 ns

t1 Data/Address Setup Time beforeDIOR/DIOW

30 ns

t2 DIOR/DIOW Assertion Time 100 ns

t3 Setup Time to DIOW 20 ns

t4 Data Hold Time after deassertion of DIOW 15 ns

t5 Data Setup Time to DIOR 20 ns

t6 Data Hold Time after DIOR 5 ns

t6z Data 3-state Time after DIOR 30 ns

t7 IOCS16 Delay Time from CS 40 ns

t8 IOCS16 Hold Time after CS 30 ns

t9 CS Hold Time after deassertion ofDIOR/DIOW

10 ns

tA DIOR/DIOW delay to IORDY 0 ns

tRD IORDY Hold Time after assertion of data 0 ns



Figure 3.8 Single-word DMA Transfer

DMARQ

DMACK

DICR/DIOW

HD[15:0] (Read)

HD[15:0] (Write)

ta

thtg

te

td

ti

tb

tc

tf

Table 3.9 Single-word DMA Transfer Cycle Times

Symbol Description Mode1 Units

ta Single-word DMA Data Transfer Cycle Time (min) 480 ns

tb DMACK to DMARQ Delay Time (max) 100 ns

tc DMACK to DIOR/DIOW Delay Time (min) 0 ns

td DIOR/DIOW Assertion Time (min) 240 ns

te Data Delay from Assertion of DIOR/DIOW (Read)(max)

150 ns

tf Data Hold from Deassertion of DIOR/DIOW(Read) (min)

5 ns

tg Data Setup Time before Deassertion ofDIOR/DIOW (Write) (min)

100 ns

th Data Hold Time after Deassertion of DIOR/DIOW(Write) (min)

30 ns

ti DMACK Hold Time after Deassertion ofDIOR/DIOW (min)

0 ns



3.2.5 IDC Interface AC Timing

This section shows the timing for the inter-device communication (IDC)interface. Figure 3.9 shows the data transfers on the IDC bus; Table 3.10shows the IDC interface timing parameters.

During write operations, data transfers are relative to the IDCSCL output.During read operations, data transfers are relative to the IDCSCL input.

Figure 3.9 Data Transfers on the IDC Bus

3.2.6 PCM Audio Interface AC Timing

Figure 3.10 shows the PCM Audio Interface timing. Symbols used in thisdrawing are explained in Table 3.11.

IDC_DA

IDC_CL

D7 D6 D5 D4 D3 D2 D1 D0

t1 t2 t3

Table 3.10 IDC Interface Timing Parameters

Symbol Description

Typical Timing Value

Standard 100 kHz Fast 400 kHz

t1 Data setup time before clock (master) 2552 ns 600 ns

t2 Data hold time after clock (master) 2623 ns 100 ns

t3 Clock period 10180 ns 2600 ns

t4 Value programmed into the IDC ClockRegister 0 or 1 (0x98C or 0x09CC)1

0x66 0x19

1. t4 is the value that must be programmed into the IDC Clock Register 0 or 1 (0x98C or 0x09CC) toget the timing shown in parameter t3.



Figure 3.10 PCM Interface AC Timing

3.2.7 I2S Bus Timing

Figure 3.11 shows the timing on the I2S bus. When the AUDIO_CONFGparameter is set for IDS output, the LRCK polarity field in theAUDIO_DAC_MODE parameter must be set to high during right channel.

Figure 3.11 I2S Bus Timing

Table 3.11 PCM Audio Interface Timing Parameters

Symbol Description Min Typ Max Units

P1 Clock Period 300 244 – ns

P2 Clock Low Time 120 – 134 ns

P3 Clock High Time 120 – 134 ns

P4 Output Delay – – 50 ns

P5 Input Setup 10 – – ns

P6 Input Hold 10 – – ns

P2

P1P3

P4 P5 P6

SDCLK

LRCK

DAI_LRCK

Right ChannelLeft Channel

DA_BCK

DAI_LRCK

DA_DATA

One Sample, T = 1/fs

MSB LSB MSB LSB MSB

16 or 24 Bits



3.2.8 UART Timing

Figure 3.12 shows typical UART timing.

Figure 3.12 UART Receiver Timing

3.2.9 Video Interface AC Timing

This section shows functional and AC timing for the ZiVA-5+ videointerface. All timing parameters are described in Table 3.12.

Figure 3.13 through Figure 3.18 shows the input and output functionalwaveforms for NTSC and PAL formats. Figure 3.19 through Figure 3.22shows the AC timing for the video interface signals; Table 3.12 describesthe AC timing parameters.

Note: VSYNCH is not shown in these figures, due to its relativelylong period.

Figure 3.13 Horizontal Synchronization Waveform

RXD [2:1] Start Data Bits (5-8) Parity Stop

LastRightBorderPixel OfLine N

First LeftBorderPixel OfLine N+1

Last LeftBorderPixel OfLine N+1

(Active)

Cb0 Y1 Cb2 Y3Ybor.Crbor. Y0 Cr0 Y2 Cr2

Note: “Boxed” values indicate interpolated pixels when interpolating horizontally.

VCLK In (27 MHz)

HSYNC

VDATA[7:0]



Figure 3.14 VSYNC and HSYNC Master Mode Waveform

Figure 3.15 NTSC Active Horizontal Line Input Timing

Figure 3.16 NTSC Active Horizontal Line Output Timing

HSYNC

VSYNCTop Field Bottom Field

2.5 HSYNCPeriods

Note: Top field means the field that starts with the first line from the top of the screen, while bottomfield begins with the second line from the top of the screen.

3 HSYNCPeriods

1 2 3 118 119 120 121 242 243 244 245

CbVDIN[7:0]

DECHSYNC

VCLK

Y Cr Y

1 2 3 118 119 120 121 242 243 244 245

CbVDOUT[7:0]

ENCHSYNC

VCLK

Y Cr Y



Figure 3.17 PAL Active Horizontal Line Input Timing

Figure 3.18 PAL Active Horizontal Line Output Timing

Figure 3.19, showing ITU-R BT.656 video output timing, is shown firstbecause that is the standard most designers will use. Other timingdiagrams for legacy products are shown in Figure through Figure 3.22.

Figure 3.19 ITU-R BT.656 Video Output Timing

1 2 3 118 119 120 121 262 263 264 265

CbVDIN[7:0]

DECHSYNC

VCLK

Y Cr Y

1 2 3 118 119 120 121 262 263 264 265

CbVDOUT[7:0]

ENCHSYNC

VCLK

Y Cr Y

V1V2 V3

V5V4

VCLK

VDATA[7:0]



Figure 3.20 Video Interface Encoder Mastering AC Timing Diagram

Figure 3.21 Video Interface Decoder Mastering AC Timing Diagram

Figure 3.22 ITU-R BT.656 Interlaced Video Input Timing

VCLK

ENCVSYNC,ENCHSYNC,

VDIN[7:0]

DECVSYNC,DECHSYNC,VDOUT[7:0]

V8

V6

V9

V7

V1V3V2

VCLK

DECVSYNC,DECHSYNC,

VDIN[7:0]

ENCVSYNC,ENCHSYNC,VDOUT[7:0]

V8

V6

V9

V7

V1V3V2

V1V2 V3

V5V4

VCLK

VDATA[7:0]



3.2.10 SPI Interface AC Timing

Figure 3.23 shows typical SPI Interface data clocking. Figure 3.24 showstypical SPI Interface timing. Table 3.13 defines the parameters and liststhe values used in Figure 3.24.

Table 3.12 Video Interface Timing Parameters

Symbol Description

Units (ns)

Min Typ Max

V1 VCLK1 Period 34 37 41

V2 VCLK1 Low Time 17 18.5 20

V3 VCLK1 High Time 17 18.5 20

V4 VDATA Interlaced Output Setup to VCLK 5 – –

V5 VDATA Interlaced Output Hold from VCLK 4 – 7

V6 Encoder HSYNC, VSYNC and Video Data Input Setup Timebefore VCLK

7

V7 Encoder HSYNC, VSYNC and Video Data Input Hold Timeafter VCLK, Encode Mode

3

V8 Decoder HSYNC, VSYNC and Video Data Input Setup Timebefore VCLK, Encode Mode

25

V9 Decoder HSYNC, VSYNC and Video Data Input Hold Timeafter VCLK, Encode Mode

2 7

1. VCLK frequency is 27 MHz with a 45/55% duty cycle.



Figure 3.23 SPI Serial Data Clocking

Figure 3.24 SPI Timing

SPI_CLK

SPI_CS

SPI_DO

SPI_DI

1 2 3 4 5 6 7 8

Note: 1. Not defined, but normally the MSB of previous character received.

tCtrtf th1

MSB 6 5 4 LSB3 2 1

LSB Note 1.1MSB 6 5 4 3 2

tsu1

td1 td2 td3

tr tftc

th2tsu2 tCS

th1

SPI_CLK

SPI_CS

SPI_DI

SPI_DO


Package Mechanical Dimensions 3-25Advance Copyright © 2002 by LSI Logic Corporation. All rights reserved.

3.3 Package Mechanical Dimensions

The ZiVA-5+ is available in the 208-pin Plastic Quad Flat Pack (PQFP)package, which is shown in Figure 3.25.

Table 3.13 SPI Interface Timing Parameters

Symbol Parameter1 Min2 Typ2 Max2 Units

tc SPI_CLK Cycle Time 0.062 – – µsec

tdty SPI_CLK Duty Cycle Tolerance 40 50 60 %

tjitter SPI_CLK Period Jitter Tolerance 120 – 120 ns

tr Rise Time, SPI_CLK – – 25 ns

tf Fall Time, SPI_CLK – – 25 ns

td1 Delay Time, SPI_CLK fall to SPI_DOUT Active – – 20 ns

td2 Delay Time, SPI_CLK Fall to SPI_DOUT Transition – – 20 ns

td3 Delay Time, SPI_CS Rise to SPI_DOUT 3-state – – 20 ns

tsu1 Setup time, SPI_CS to SPI_CLK Fall 25 – – ns

th1 Hold time, SPI_CS to SPI_CLK Rise 20 – – ns

tsu2 Setup time, SPI_DIN to SPI_CLK Rise 25 – – ns

th2 Hold time, SPI_DIN to SPI_CLK Rise 20 – – ns

tCS Delay Time between Chip Selects 220 – – ns

1. VD = 3.13 to 5.25 V TA = 0 to 70 °C, CL = 20 pF2. All timing is referenced to the 50% level of the waveform. Input test levels are VIH - VI/O - 0.4V, VIL

= 0.4V



Figure 3.25 208-pin PQFP Package Mechanical Dimensions

C

Lθ

A

D D1

DD1

A1

A2

B

SymbolDimensions in Millimeters1 (Inches)

1. The metric (millimeter) values are the controlling dimensions, andshould be used for PC board design.

Min. Typ. Max.A – – 4.10 (0.161)A1 0.00 – 0.50 (.020)A2 3.15 (0.124) 3.50 (0.138) 3.85 (0.152)B 0.15 (0.006) 0.22 (0.009) 0.30 (0.012)C 0.09 (0.004) 0.15 (0.006) 0.25 (0.010)D 30.35 (1.195) 30.6 (1.205) 30.85 (1.215)D1 27.90 (1.098) 28.00 (1.102) 28.10 (1.106)L 0.30 (0.012) 0.50 (0.020) 0.75 (0.030)L1 – 1.30 (0.051) –P – 0.50 (0.020) –θ 0 – 10 deg.

P

L1


Package Marking 3-27Advance Copyright © 2002 by LSI Logic Corporation. All rights reserved.

3.4 Package Marking

Some of the ZiVA-5+ devices receive additional marking as shown inFigure 3.26.

Figure 3.26 ZiVA5+ Variant Marking

ZiVA-5P+ devices do not get any additional marking. ZiVA-5M+ devicesare marked with an “M” immediately behind the Silicon Revision marking(B0 M). ZiVA-5X+ devices are marked with an “X” immediately behindthe Silicon Revision marking (B0 X).

L S IZiVA™-5B0 __F YYWWASSY-LOTCOUNTRY

sd 5.12 312278514120

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