OPERATION CONTROL OF MULTILEVEL INVERTERS FOR INDUCTION MOTORS

Asst. Prof. Hamdy A. Ashour Prof. Yasser G. Dessouky Eng. Samia A. Mahmoud

Arab Academy for Science and Technology, Department of Electrical and Computer Control Engineering

Miami, P.O. Box: 1029, Alexandria, EGYPT, hashour@aast.edu

Abstract This paper introduces theoretical and experimental analysis of 3-ph induction motor operated from 12 semiconductor

switches connected in the form of neutral point clamped multilevel inverter. The general objective of a multi-level

inverter is to synthesize a near sinusoidal voltage from several levels of DC voltages as a staircase (discreet) shaping

waveform. A brief comparison of multilevel inverter has been introduced. Simulation models of the NPC inverters with

different number of switches have been carried out using Simulink under MATLAB. Methods to increase number of

levels (steps), hence reducing filter requirements and total harmonic distortion by increasing number of switches or

controlling the firing patterns of the switches are suggested and analyzed. Controlling the switching pattern of the three-

phase multi-level inverters to eliminate certain harmonic order in stator voltage of the three-phase induction motor is

explained and analyzed. Motor speed response together with voltage and current waveforms for each configuration are

obtained and discussed. Experimental setup has been designed, implemented and tested for practical validation.

I. INTRODUCTION

Electric machines have been considered as the main workhorse of industry for many years. AC machines are rugged, less

expensive with lower maintenance requirements due to the absence of commutation problems but they exhibit highly

coupled, nonlinear, multi-variable structures, as opposed to separately excited DC machines. There has been intensive

research on the development of AC drive technology and as a consequence, the cost and performance of AC drives have

been improved considerably [1]–[4]. The concept of multilevel inverters have been introduced to perform a power

conversion in multiple voltage steps to obtain improved power quality, lower switching losses, better electromagnetic

capability and higher voltage ratings [5]-[8]. Methods of operation control and performance enhancement of multilevel

inverters have been investigated [9]-[12]. The availability of such inverters for power system and standard electrical

machine drives for industrial applications has been illustrated [13]-[20]. Through this paper, a brief comparison between

multilevel inverter configurations is discussed, control operation of the 3-ph NPC inverter for driving the 3-ph induction

motor has been modeled and studied, methods of increasing number of voltage levels and elimination of certain harmonic

orders to improve motor performance are demonstrated, and experimental setup has been implemented for practical

validation.

II. MULTILEVEL INVERTERS

The multilevel voltage source inverters provide a unique structure of power electronics devices allows synthesizing a

desired voltage from several steps of DC voltages as depicted in figure 1a. For a large power rating, a multi-stepped

inverter can be utilized with a series-parallel connection of devices. However this arrangement requires matching, and

some amount of voltage or current derating of the devices with complex and not easily available design. A possible

solution for such higher power ratings is an arrangement of identical 1-ph inverters fed from single dc supply while the

output is shaped through series connection of center-tapped transformers with different turns ration [9]-[10] or by a

parallel connection of 3-ph inverters through center-tapped reactors in the output [2]. Other arrangements of multilevel

inverters eliminating the need for the output transformers can be seen in figures 1b, 1c and 1d. These arrangements of

power electronics devices convert the DC supply to an AC supply by proper selection of conducting devices (switching

pattern), and the output is a multi-stepped (discrete) sinusoidal waveform with reduced filter requirements. The features

of the three configurations can be summarized as follows [3]:-

A. Diode-clamped multilevel inverter

A diode-clamped multilevel inverter (DCMLI), and also may be name as neutral point clamped (NPC), is shown in figure

1b where one leg requires (m-1) DC sources, 2(m-1) switching devices with free wheeling diodes and (m-1)(m-2)

clamping diodes. This implies that a multilevel inverter has a (m) output phase-leg voltage and a (2m-1) level output line

voltage. Although each switching device is only required to block a voltage level of Vdc/(m-1), the clamping diodes need

to have a reverse voltage blocking rating VD of:

dcD Vm

kmV

1

1

(1)

Where m is the number of phase-leg voltage levels; k goes from 1 to (m-2) and Vdc is the total DC link voltage. When

(m) is sufficiently high, the number of diodes makes the system impractical to implement, which in fact limits the

possible number of levels with such configuration.

B. Flying-capacitors multilevel inverter

Figure 1c shows one leg of multi-level inverter based on a flying-capacitors multilevel inverter (FCMLI). Assuming that

each capacitor has the same voltage rating, series connection of the capacitors indicates the voltage level between the

clamping points. The inner-loop balancing capacitors for phase- leg ‘a’ are independent from those for phase-leg ‘b’. The

voltage level for the flying-capacitors inverter is similar to that of the diode-clamped type of inverter. That is, the phase

voltage Va0 of a multi-level inverter has ‘m’ levels, and the line voltage Vab has (2m-1) levels. Assuming that each

capacitor has the same voltage rating as the switching device, the DC bus needs (m-1) capacitors for a multi-level

inverter. The number of capacitors required for each phase is:

m

j

C jmN1

)( (2)

The switching devices have unequal turn-on time. Like the diode-clamped inverter, the line voltage consists of the

positive phase-leg voltage of terminal ‘a’ and the negative phase-leg voltage of terminal ‘b’. The inverter requires a large

number of storage capacitors. A multilevel inverter requires a total of (m-1)(m-2)/2 auxiliary capacitors per phase leg in

addition to (m-1) main DC bus capacitors in case of individual DC batteries are not available. On the contrary, a

multilevel diode-clamp inverter may require only (m-1) DC bus capacitors of the same voltage rating. It should be noted

that the issue of maintaining the charging balance of the capacitor adds complexity to the system requirements.

C. Cascaded multilevel inverter

A cascaded multilevel inverter as shown in figure 2d consists of a series of H-bridge (single-phase, full-bridge) inverter

units. The general function of this multilevel inverter is to synthesize a desired voltage from several separate DC sources

(SDCSs), which may be obtained from batteries, fuel cells, or solar cells. Each SDCS is connected to an H-bridge

inverter. The AC terminal voltages of different level inverters are connected in series. Unlike the diode-clamp or flying-

capacitors inverter, the cascaded inverter does not require any voltage-clamping diodes or voltage-balancing capacitors.

The phase output voltage is synthesized by the sum of inverter outputs, Van = Va1 + V a2 + --- + V aNS. The required

number NS of isolated dc sources, hence number of H-bridges, to get the m output phase voltage levels is:

2/)1( mNS (3)

It should be noted that each switching device always conducts for 1805 (or half-cycle), regardless of the pulse width of

the quasi-square wave of each bridge, making the switching device current stresses equal while identical repeated design

of such H-bridges optimizes the layout and packaging of such inverter configuration.

A comparison of components requirements per leg for each configuration can be summarized as in table 1.

III. SIMULATION AND ANALYSIS

A) Operation analysis

In this paper, the neutral-point-clamped (NPC) multilevel inverter is proposed to be utilized for operation of a 3-ph

induction motor. The three-phase neutral-point-clamped (NPC) inverter using 12 switches is shown in figure 2a. In this

circuit the DC bus voltage is split into two levels. The middle point ‘o’ is defined as the neutral point. The output voltage

Vao has up to three states (levels), (Vdc /2), (0) and (-Vdc /2). For voltage level Vdc /2 , the switches S1a and S2a are the

path of positive current, while D1a and D2a are the path of negative current, as shown in figure 2b. For voltage level 0,

the switches S2a and DC1 are the path of positive current, while S3a and DC2 are the path of negative current, as shown

in figure 2c. For voltage level -Vdc /2, the switches S3a and S4a are the path of positive current, while D3a, D4a are the

path of negative current, as shown in figure 2c. The two diodes DC1 and DC2 clamp the switches voltage to the DC bus

voltage. When both S1a and S2a turn on, the voltage across points ‘a’ and ‘G’ is Vdc (i.e.VaG = Vdc ). In this case, DC2

balance output voltage charging between S3a and S4a.The output voltage Vao is AC and VaG is DC, the difference

between Vao and VaG is Vdc /2. The conduction angle of switch Sa1 is reduced from 180o to an angle of (180o – 2α), and

the number of levels would also change. By changing in switching angles or the firing pattern α, the number of level in

the inverter can be increased, (this will be shown in section C).

B) Modeling of 3-ph (NPC) inverters

For comparison analysis, three different configuration models of the 3-ph NPC multilevel inverters have been built using

the Simulink under Matlab software program including:-

i- 3-ph using 12 switches

ii- 3-ph using 24 switches

iii- 3-ph using 36 switches

An example of such models is shown in figure 3 for the 3-ph (NPC) inverter with 12 switches, which consists of a load

bus, a supply bus, three legs (a, b, c), each leg has four switches, and measurement blocks. Simulation analysis is carried

out based on such models and results will be demonstrated through the following sections.

C) Increasing number of levels

Multi-level inverters include an array of power semiconductors and voltage sources. The output generated is voltage with

stepped wave forms. The term multi-level starts with the three-level inverter, and by increasing the number of levels, the

output voltage has more steps generating a staircase wave form which has a nearly sinusoidal wave shape. Number of

levels in the output voltage can be increased by the following two methods:-

i) Increasing number of devices

The operation of three-phase (NPC) inverters using 12-switch, 24-switgh and 36-switch has been simulated and

investigated. A comparison between the output phase voltage waveforms has been performed keeping the dc voltage

sources constant for all cases. From the analysis of simulation results shown in the figure 4, and when the number of

switches per leg is increased, followings can be concluded:-

-The output voltage wave form is becoming near to a sinusoidal waveforms.

-The total harmonic distortion (THD) becomes lower.

- The peak reverse voltage of the switch is lower.

-The rating of voltage and current sharing by each switch is lowered.

-According to the phase to neutral voltage, the 12-switch inverter may give 7 levels, and 24-switch may give 9 levels

while 36-switch may give 11 levels.

- 12-switche inverter has only α1, 24-switch has α1 and α2 while 36-switch has α1, α2 and α3 control firing delay angles.

- Number of levels of each inverter can be decided by controlling the (α) pattern which has more degree of freedom by

increasing number of switches (this will be illustrated in the next section).

- Adding more complexity and increasing the overall cost.

ii) Controlling the firing pattern (α) Figure 5 shows gate signals and different voltage waveforms of the simulated 3-ph 12 switch NPC inverter, where left

column is for α = 0 wile right column is for α = 20. y changing in switching angles or the firing pattern α (the shift angle

from the origin during positive half cycle from ‘0’ to ‘π’, and during negative half cycle from ‘π’ to ‘2 π’ the number of

levels in the output voltage can be increased. Considering that ‘i’ is the number of switching angles, the stepped phase

voltage waveform synthesized by a (2i +1) level inverter, where α1 to αi must satisfy α1 < α2 < …..< αi < π /2. To

explain how the staircase voltage is synthesized, the line to line waveform across the load terminal, where the potentials

of terminals ‘a’ and ‘c’ are positive if (S1a & S2a) and (S1c & S2c) are on, and the potential of terminal ‘b’ is negative if

(S3b & S4b) are on. Hence, the line to line voltages have 3 levels, and can be computed as follows:

Vao = Vdc/2 , Vbo = - Vdc/2 and Vco = Vdc/2

Vab = Vao – Vbo = Vdc , Vbc = Vbo – Vco = -Vdc and Vca = Vco – Vao = 0 (4)

The phase voltage VaN has four levels (3

2 Vdc , 3

1 Vdc, , -3

1 Vdc , -3

2 Vdc ), while the line to line voltage Vab has 3-

levels ( Vdc, 0, - Vdc) and the voltage between the terminal ‘a’ and center point ‘o’ Vao has two levels ( 2

1 Vdc , -2

1 Vdc ).

It should be bearing in mined that the firing pattern of the inverter can be controlled to operate this inverter in higher level

mode as follows: If the control signal of switch S1a is delayed by an angle α and consequently other control signals will

be modified as shown in right columns of figure 5. The voltage between terminal ‘a’ and center point of DC supply (Vao)

will have three level (Vdc, 0, - Vdc ) , while the line to line voltage will have five voltage levels ( Vdc ,2

1 Vdc , 0, -2

1Vdc ,

- Vdc ) and the phase voltage across the load (VaN) will have seven voltage levels ( 3

2 Vdc ,

2

1Vdc ,

3

1 Vdc, ,0 , -

3

1 Vdc ,

-2

1Vdc, -

3

2 Vdc ) as shown in figure 5. It can be seen that number of levels in the generated output waveform can be

increased by controlling the delay angle. Increasing number of switches introduce more degrees of freedom since it

increasing the number of available delay angles. Through the analysis in this work, the values of such angles (α1 ….. αi)

are set by try and error to set maximum level from each configuration. Technique for calculation of optimal delays angle

may be suggested as a future work.

D) Operation of 3- phase induction motor through 3-ph (NPC) multi-level inverters

The 3-ph multilevel inverters can be evolved into the standard low and medium voltage motor drive system. Each inverter

has 3 legs, and the number of voltage levels depends on the number of switches in each le and the firing pattern (as

described in section C). MATLAB simulation results have been obtained for the 3-ph induction motor of 300W 220V

start-connected 1490rpm fed through different NPC inverter configurations using 12, 24 and 36 switches. Figure 6

illustrates different simulation results obtained for different inverter configurations. As could be seen from figure 6,

increasing number of switches increases the level of the voltage and current waveforms and the currents became nearly

sinusoidal hence the speed response is faster and better moor response can be achieved. Since the analysis has been

carried out for direct motor starting, increasing in the starting current and torque is also increased by increasing the

number of switch. This problem can be eliminated by introduced a control method such as (v/f) constant ratio control

technique or soft starting technique.

E) Selective harmonic elimination

When the current flows through three phase induction motor, it produces sinusoidally distributed magneto-motive-force (M.M.F) in the

air gap. The fundamental M.M.F is a rotating M.M.F in the forward direction. The third harmonic M.M.F in the three-phase, three-wire

system is pulsating because third harmonic currents are in phase. The fifth harmonic M.M.F wave is also a rotating wave in the

opposite direction to the fundamental. The seventh harmonic M.M.F wave rotates in the same direction as the fundamental wave. In

general, All odd harmonic M.M.F waves of order h = 6n + 1, where ‘n’ is harmonic order and is an integer number, rotate in the same

direction as the fundamental wave while those whose order is h = 6n - 1 rotate in the opposite direction. When the current fed through

the NPC inverter through motor windings, the M.M.F distribution in space has a staircase wave form. The space harmonic wave rotate

at 1/n times the speed of the fundamental wave. The effects of space harmonic are significant. If the effect of seventh harmonic torque

is appreciable, the motor may settle to a lower speed, the motor crawls. To reduce the crawling effect the seventh harmonics should be

reduced. Also the fifth harmonics produce a negative torque. Therefore, eliminating this fifth harmonics reduces this negative torque.

From a typical quarter-wave symmetric stepped voltage wave form, shown in figure 1a, synthesized by a (2i+1) level,

where ‘i’ is the number of switching angles, and by applying Fourier series analysis, the amplitudes of the dc offset and

all even harmonics are zero, while the amplitude of any odd nth harmonic of the stepped waveform can be written as[3]:

Vn = (4/nπ)

1

1

mk

k

[ Vk cos (nαk) ] (5)

Where k integer from 1 to m-1 , Vk is the Kth level of DC voltage, n is an odd harmonic order, m is the number of

level and αk is the Kth switching angle.

To minimize harmonic distortion and to achieve amplitude of the fundamental component, up to (m-1) harmonic contents

can be removed from the voltage wave form. In general, the most significant low-frequency harmonics are chosen to be

eliminated by properly selecting angles among different level inverters, and high-frequency harmonic components can be

removed by using additional filter circuit if required. The effect of high-frequency components on the torque is not

significant as the amplitude of the harmonic current components is inversely proportional to the index of the harmonic

components. From the MATLAB harmonic analysis and measurement blocks, results for three-phase 12-switch inverter,

and for the switching angle α1 = 20o , can be plotted as shown in figure 7. The firing angle can be adjusted to eliminate

a certain harmonic. For instance, from equation (5), to eliminate the fifth harmonic, the angle is adjusted as follow:

V5 = (4/5π) [ V1 cos (5α1) ] = 0 hence α1 = 0.2 cos-1 0 = 90/5 = 18 o (6)

These results can be plotted as shown in figure7b.

Also the firing angle can be adjusted to eliminate the seventh harmonic where the switching angle

V7 = (4/5π) [ V1 cos (7α1) ] = 0 hence α1 = 0.2 cos-1 0 = 90/7 = 12.857 c

These results can be plotted as shown in figure 7c.

From equation (5), to eliminate the fifth and seventh harmonic using the 3ph NPC 24-switch inverter, the angles are

adjusted as fallow:

V5 = (4/5π) [ V1 cos (5α1) + V2 cos (5α2)] = 0 (8)

V7 = (4/5π) [ V1 cos (7α1) + V2 cos (7α2)] = 0 (9)

These equations can be solved iteratively by iteration (MATLAB program) for calculations the α1 and α2 , giving :-

α1 = 30.8571 o and α2 = 5.1429 o (10)

Harmonic spectrums of the 12-swutch and 24-switche inverters for different firing patters are illustrated in figures 7 and

8 respectively, showing the effect of selection the right angles (α1 and α2) for certain harmonic cancellation. It can be

concluded that increasing number of switches introducing more angles hence more harmonic orders can be eliminated for

better motor performance.

IV. Experimental Validation

A) Experimental setup

Electronic circuits have been utilized to implement the proposed experimental setup and different experimental results are

obtained. It should be noted that the setup and circuits has been designed and implemented as a printed board circuits

(PCB) using available components and material in the local market. The implemented system is proposed to drive 3-ph

induction motor with 12 semiconductor switches connected in the form of a neutral-point-clamped (NPC) multilevel

inverter, this system is composed of five main modules as shown in figure 9, each performs a certain function as follows:

1-PIC module: The hardware circuit is designed to generate 6 switching signals (Q1 ----- Q6) of the inverter

according to the required switching pattern. The circuit has a 16F84A PIC microcontroler used to execute the

software program written in PIC basic programming language for simplicity.

2-Inverse signals generator: This circuit receives the six pulses ( Q 1 ------ Q 6 ) from the PIC modules and

generates corresponding inverse signals ( Q 1 -------- Q 6) through two stages transistors with dead time interval to

prevent the simultaneous operation of power transistors in the same inverter arm, hence prevents possible DC

supply short circuit

3- Gate drive circuits: This circuit receives the 12 single-ended non-isolated signals ( Q 1 ------ Q 6 ) and ( Q 1 ----

---- Q 6) generated by the PIC and inversion modules then provides corresponding 12 double-ended isolated-

ground gate signals for the neutral-point-clamped (NPC) power transistor devices with 12v DC supply level

suitable for the MOSFET switching transistors. Each circuit of the 12 gate drive circuits consists of isolated

power supply, opto-isolating and amplification stages.

4- The 3-ph NPC inverter: It consists of 12 MOSFET IRF740 power transistors with their own built in

freewheeling diodes and also additional 6 power clamped diodes are utilized with two series dc supplies to

implement the circuit shown in figure 2a.

5- Three-phase induction motor : The experimental setup has been tested on a squirrel cage induction motor1

of 0.3 kW, Δ / Y, 220 / 380 V, 1.25 / 0.75 A, 50 Hz, 1410 rpm as a load.

B) Experimental Results

The experimental setup described in section (A) has been implemented and each circuit has been gathered and tested for

different gating pattern by controlling the shift angle for practical validation of the simulation analysis described in

section (III). Different experimental waveforms are obtained using digital scope then compared with the corresponding

simulated results obtained by the simulink model introduced in section (III). The left column of figure 10 depicts the

experimental waveforms of transistor signals, phase voltages, line voltages and motor phase voltage and current, while

the right column depicts the corresponding simulated waveforms. It can be seen that experimental and simulated results

are quit similar. The 3-ph voltages are balanced and phase shifted by 120 c. Phase voltages have 7 levels while line

voltages have 5 levels since the motor is star connected. Although the motor voltages are staircase stepped waves, motor

phase currents are approximately sinusoidal due to the motor inductance equivalent circuit.

V. Conclusions

A brief comparison of the multilevel configurations has been introduced and models of the 3-ph NPC inverter with

different number of switches have been simulated and tested. The multilevel inverter features can be summarized as: the

output voltage and power increase with number of levels without the requirement of increase in rating of individual

device, the harmonic content decreases as the number of levels increases and filtering requirements are reduced, with

additional voltage levels, the voltage waveform has more free-switching angles, which can be reselected for harmonic

elimination without having to restore PWM technique, the switching devices do not encounter any voltage-sharing

problems, and multilevel inverters can easily be applied for high-power applications such as large motor drives and

utility supplies. However, more number of devices, gate drive circuits and isolating power supplies are required, hence

increasing the complexity of the system. Such problem can be overcome by the new technologies of power electronics

devices, power and intelligent modules. The analysis carried out through this paper has shown that:- increasing number of

switches per inverter leads to more staircase in the output voltage and motor currents, motor current becomes nearly

sinusoidal using more switches hence fundamental output voltage is increased while the harmonic component decreases

hence improving the speed response and torque pulsation of the induction motor, controlling the firing angle can be

directly chosen to cancel certain harmonic order such as 5th and 7th which have a major drawbacks effects on the motor of

they are found with non-negligible magnitudes in the harmonic spectrum. Simulation and experimental results are well

matched showing the effectives of the proposed setup and validating such multi-level inverter configuration for driving

the 3-ph induction motor particularly for higher voltage ratting applications.

References

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[2] B. K. Bose, “Power electronics and AC Drives” prentice-hall, Upper Saddle River, NJ, 1986

[3] Muhammad H. Rashid “Power Electronics Circuits, devices and Applications”

[4]

[5] A.M.Massoud, S.J.Finney and B.W.Williams , “High-power, high voltage IGBT applications series connection of

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[6] Jose’ Rodrignez, Jih-sheng Lai,senior “Multilevel inverters:A survey of topologies. Controls, and application”,

IEEE Transactions on Industrial Electronics. vol.49.NO.4, August 2004

[7]

[8] Sherif M.W.Ahmed, G.M.A.Sowelam and M.F.Abd El-Kader “Comparison Study between three-phase three-level

inverter techniques” The Tenth Middle East Power Systems Conference, dec. 13-15, Port Said, Egypt. November 2005

[9] Keith A. Corzine, Mike W. Wielebski, and Jin wang. “Control of cascaded multilevel inverters”, IEEE Transactions

on Power Electronics. vol.19.NO.3, May 2004.

[10] Brendan Peter Megrath, Donald Grahame Holmes, and Thomas Lipo, “Optimized space vector switching sequences

for multilevel inverters”, IEEE, Transactions on Power Electronics. vol.1.NO.3 , November 2003.

[11] Jose’ Rodriguez, Luis Moron, Jorge Pontt, “A High-performance vector control of an 11-level inverter”, IEEE

Transactions on Industrial Electronics. vol.50.NO.1,February 2003.

[12] Jose’ Rodriguez, Jorge Pontt, Pablo Carrea, Patricio Cartes’ and Cesar Silva, “A New Modulation Method to reduce

common mode voltages in multilevl inverters”, IEEE, Transactions on Industrial Electronics. vol.51.NO.4, August 2004

transmission systems”, IEEE, Industrial Electronics, vol. 2, pp. 488-494 , 2000

[13] Brian A.Welchko, Mauricio Beltraode and Thomas A.Lipolife “A three-level MOSFET inverter for low-power

drives”, IEEE Transactions on Industrial Electronics. vol.51.NO.3, June 2004

[14]

[15] Dudi A. Rendusara, Victor R.Stefanovie, and James W. “Analysis of Common Mode Voltage-‘Neutral Shift’ in

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vol.15.NO.6, November 2000

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Alexandria, Egypt, 2004

Inverter configuration Diode-Clamped Flying-Capacitor Cascaded

Switching devices 2(m-1) 2(m-1) 2(m-1)

Freewheeling diodes 2(m-1) 2(m-1) 2(m-1)

Clamping diodes (m-1)(m-2) 0 0

Flying capacitors 0 (m-1)(m-2) 0

DC sources (m-1)

(series dc supplies or

capacitors)

(m-1)

(series dc supplies or

capacitors)

(m-1)/2

(isolated dc supplies)

Table 1: Comparison of components requirements per phase for different multilevel inverter configurations

Fig.2: Transistors and diodes current path in

3-ph, 3-level, 12-switch inverter

(a) Circuit diagram

(b) +Vdc /2 V ( level-1 )

(c) 0V ( level-2 )

(d) -Vdc /2 V ( level-3 )

Fig.1: Types multilevel inverter

(a) Output phase voltage

(c) Capacitor clamped (d) Cascaded

(b) Diode clamped

ga1

ga2

ga3

ga4

gb1

gb2

gb3

gb4

gc1

gc2

gc3

gc4

pulses

ph3R3s+s-scoi-s

mesurements3

sig

mesurements2ph1

R2

R1.

sco

sig

mesurements1

V DC/2

V .DC/2

+v e

sa1

sa2

sa3

sa4

sb1

sb2

sb3

sb4

sc1

sc2

sc3

sc4

N1

PH1

N2

PH2

N3

PH3

s+

s-

i-s

Switches.

R3

R2

99

R1

(a) Overall system

(b) One leg of the 3-ph inverter

Fig 3: Simulink diagrams of the 3-ph 12-switch

inverter as an example of different simulated inverters

(a) Gate signals

(b) Vao

(c) Vab

(d) VaN

α = 00 α = 200

Fig 4 : Increasing number of levels by changing the delay angle α

0 0.5 1 1.5 2 2.5 3-25

-20

-15

-10

-5

0

5

10

15

20

25output current of 3-level 3ph 12-switches with motor

time -sec.

arm

atu

re c

urr

ent,

Am

p.

line current

1.61 1.615 1.62 1.625 1.63 1.635 1.64 1.645 1.65 1.655 1.66-5

-4

-3

-2

-1

0

1

2

3

4

output current of 3-level 3ph 12-switches with motor

time -sec.

arm

atu

re c

urr

ent,

Am

p.

0.015 0.02 0.025 0.03 0.035 0.04

-10

-8

-6

-4

-2

0

2

4

6

8

10

output current of 7-level 3ph 36-switches with motor

time -sec.

arm

atu

re c

urr

ent,

Am

p.

0.82 0.83 0.84 0.85 0.86 0.87 0.88

-200

-150

-100

-50

0

50

100

150

200

phase voltage of 3-level 3ph 12-switches with motor

volt

Gate signals Phase voltage ( VaN)

Fig 5: Increasing number of levels by increasing number of inverter switches

(a) 3-ph 12-switch 7-level with one control delay angle

(b) 3-ph 24-switch 9-level with two control delay angles

(c) 3-ph 36-switch 11-level with three control delay angles

12-switch

Fig 6: Direct 3-ph induction motor staring waveforms when being fed through different

multilevel inverter configurations

(a) Transient motor Speed

(b) Transient line current

(c) Steady state line currents

(d) Steady state phase voltage

24-switch 36-switch

Fig 7: Selection of delay angle (α) for elimination of

certain harmonics order in the 12- switch inverter

(a) α = 20o ( no harmonics elimination)

(b) α = 18o (elimination of 5th harmonics order)

(c) α = 12.857o (elimination of 7th harmonics order)

th5 th7

th5 th7

th5 th7

Fig 8: Selection of delay angles (α1 & α2) for elimination of certain harmonics order in the

24-switch inverter

(a) α1= 40o & α2= 20o

(no harmonics elimination)

(b) α1= 30.857o & α2= 5.1429o

(elimination of 5th and 7th harmonics order)

th5

th5 th7

th7

12 gate

drive

circuits

12-switch

Multilevel

inverter

PIC

module

(Q1----Q6)

Inverse

signals

generator

(Q1----Q6)

(a) Block diagram

(b) Photograph

Fig 9: Experimental setup

(Ch1 is 25V/div , Ch2 is 0.5A/div )

Ch1

Ch2

Ch3

Ch1

Ch2

Ch3

Ch4

Ch1

Ch2

Ch3

Ch1

Ch2

(Ch1, Ch2, Ch3 are 50V/div) (Ch1, Ch2, Ch3 are 50V/div)

(c) 3-ph line voltages

(Ch1 is 50V/div , Ch2 is 2A/div )

(c) Motor phase voltage and current

(Ch1, Ch2, Ch3 are 50V/div) (Ch1, Ch2, Ch3 are 50V/div)

(b) 3-ph phase voltages

(Ch1, Ch2, Ch3, Ch4 are 12V/div)

(a) Gate signals of leg (A) 4 switches

(Ch1, Ch2, Ch3, Ch4 are 25V/div)

Fig 10: Experimental and simulated waveforms

of 3-ph 12-switch NPC inverte (α = 200 )

Experimental Simulated