mixed signal systems and integrated circuits · 2010. 4. 2. · dynamic element matching dac ... k....
TRANSCRIPT
2009/12/18 A. Matsuzawa 1
Mixed signal systems and integrated circuits
Akira Matsuzawa
Tokyo Institute of Technology
2009/12/18 A. Matsuzawa 2
1. Z transform2. Noise shaping3. Sigma-delta modulation4. SNR5. Hider order system6. Multi-stage Sigma-delta modulation7. Recent important developments8. Design example
Over sampling ADC and DAC
Sigma-delta modulation
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Frequency characteristics of DS modulator
103
104
105
106
107
-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0SNDR = 99.5dB
SNR = 100.1dB
In-bandOSR=64200kHz
Dyn
amic
Ran
ge (d
B)
Frequecy (Hz)
Thermal noise
5th order, 1bit
100dB/dec
103
104
105
106
107
-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0SNDR = 99.5dB
SNR = 100.1dB
In-bandOSR=64200kHz
Dyn
amic
Ran
ge (d
B)
Frequecy (Hz)
Thermal noise
5th order, 1bit
100dB/dec
103
104
105
106
107
-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
1st order
20dB/dec
2nd order
40dB/dec
dBFS
Frequency (Hz)
fs=26MHz
103
104
105
106
107
-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
1st order
20dB/dec
2nd order
40dB/dec
dBFS
Frequency (Hz)
fs=26MHz
)z(Qz1)z(X)z(YL1
s
22q f12
)f(h
1L22L2
s
f
f s
2
f
f
L2
ez12
OSR1L231
2df
ff2j
f12
z1)f(hN
b
b
b
bfs/f2j
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12
2 121223
LN OSRLSNR
0
20
40
60
80
100
120
140
160
180
200
1 10 100 1000
Dyn
amic
Ran
ge (
dB)
1st
2nd
3rd
4th5th
OSR
n=1bit
SNR vs. OSR
OSR=M
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111
z 111
z 1z...
Quantizer
Q
)z(Ez)z(X)z(Y
QYzz.....Y
zzY
zzX
zY
k
kkk
1
1
1
11
1
1
1
1
1
11111
111
z
3rd-- >10 steps 4 th ---- >30
In OutH
Higher order sigma-delta modulation
Cascade connection of the integrators
The feed back loop becomes unstabledue to large phase delay,When the order is larger than 2.
Increase the resolution of the quantizerfor stabilization
Higher order sigma-delta modulator becomes unstable easily.
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Feed Forward type vs. Feed Back type
+ +
nQ
+1
1
1
zz
1
1
1
zz
1
1
1
zz
1
1
1
zz
X Y
b1 b2 b3 b4
+
1
1
1
zz
XY
nQ
1z
+ 1
1
1
zz
1
1
1
zz a41
1
1
zz
a1 a2 a3
+ +
+
FF
FB
Integrator
Integrator
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Signal swing of integrator in FF type and FB type
time
1
-11
-11
-1
0
0
0
time
5
-55
-55
-5
0
0
0
(a) FF (b) FB
1st Integrator
2nd Integrator
3rd Integrator
FF type can suppress signal swings
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Actual SNR of Sigma delta ADC
M 阪大 谷口教授より
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Pole, zero, and frequency characteristics
Unit circle
Zeros: Z=1Quadrature
Poles
阪大 谷口教授より
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Design for position of zeros
1z
阪大 谷口教授より
Spiting zeros on the unit circle
Deeper blacking for noise in signal-band
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Local resonators
)()(:
zFzHNTF
11
Local resonator can form the zeros
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Effect of zero-spreading
阪大 谷口教授より
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MASH (Multi-stage noise shaping)
111
z+
1z
Q1
+
+
11 z
111
z+
1z
Q2
+
+
11 z
111
z+
1z
Q3
XY
-Q1
-Q2
1st
quantization noise
Y1
Y2
Y3
2nd
quantization noise
3
123
21
12
11
1
11
1
QZQYQZQY
QZXY
3
31
321
21
1
1
11
QZXY
YZYZYY
Realizing the stable 3rd order sigma delta modulation.
Feed forwarded multi-stage noise shaping architecture is free from instability,however requires good matching.
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Signal swing of integrator
Reduce signal swings
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Model for Scaling
f = [MAXmax3 MAXmax4 MAXmax5 MAXmax6 MAXmax7] / Targethalfswinga5 = [ a5(1)/f(1) a5(2)*f(1)/f(2) a5(3)*f(2)/f(3) a5(4)*f(3)/f(4) a5(5)*f(4)/f(5) ]lfb5 = [ lfb5(1)*f(3)/f(1) lfb5(2)*f(5)/f(3) ]w = [ w(1)*f(1) w(2)*f(2) w(3)*f(3) w(4)*f(4) w(5)*f(5) ]
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Signal swing and scaling
a5 = 0.8106 0.3861 0.2236 0.1280 0.0401lfb5 = 0.0177 0.8412w = 1.0 1.0 1.0 1.0 1.0
a5 = 0.2996 0.3219 0.2811 0.2417 0.1565lfb5 = 0.0169 0.1141w = 2.7054 3.2444 2.5804 1.3670 0.3500
Scaling後Scaling前
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1bit
Effect of scaling
Before scaling After scaling
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5bit
Effect of scaling
Before scaling After scaling
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Effect of scaling
Before scaling After scaling
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kT/C Noise vs. Capacitance
1st stage
2nd Stage
3rd stage
4,5 Stage
5order 1bit 3order 3bit
1st Stage
2nd Stage
3rd stage
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General expression of ΣΔ modulator
Input signal
+
nQzFzHX
zFzHzHY
)()()()()(
11
1
Output signalQuantizer
)(zH
)(zF
nQ YX
)()()(zFzH
zH1
)()( zFzH11
STF: Signal Transfer Function
NTF: Noise Transfer Function
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Contribution of noise
Int. 1 Int. 2 Int. 3 Int. 4
DAC
+In入力 Out
Vn1 Vn2 Vn3 Vn4
724
6
4N523
4
3N322
2
2N1Ntot_N MA7P
MA5P
MA3P
M1PP
IntegratoriuntilgainA thi :
-+ + +
Contribution of noise of 1st stage integrator and DAC is very large
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Effect of thermal and 1/f noises
Thermal and 1/f noise of the 1st integrator appear directly.
FrequencyIdeal
Actual
Magnitude (dB)
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IntegratorCf
VinVout
Vref
Csφ1
φ1
φ2
φ2
-+G
Cf
VinVout
-+
φ1 φ1
φ2 φ2Cs
G
-+
φ2 φ2Cs1
Cs2
φ1φ1
φ1
φ2
Vin
Cf
Vref
G Vout
Delayed
Non-Delayed
With subtractor
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Circuit example
・ComparatorComparator
・OPampOPamp・DACDAC
・Local Feedback PathLocal Feedback Path
・SumSum
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Data Weighted Averaging
+VDACー
+VDACー
+VDACー
010、100、011
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Dynamic Element matching DAC
4322571547
DA
C
4322571547
(a) Conventional DAC (b) Dynamic Element matching
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DEM Comparison
Y.Geerts and M. Steyaert, “Guidelines for implementation of CMOS multibitoversampling modulators”, ESPRIT project: SYSCONV Work Package 2,http://www.imse.cnm.es/esd-msd/deliverables.html
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Continuous time ΣΔADC
L. Breems and J.H. Huijsing,”Continuous-time sigma-delta modulation for A/D conversion in radio Receivers”Kluwer
We can make sigma delta ADC with CT filter.
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Effect of clock jitter
DAC Pulse
Ts
T
2281
Tbwit Mf
SNR
lim_
SNR=85dB, M=32, fbw=1.25MHz, 2.8psfbw=12.5MHz, 0.028ps
SNR of CT ΣΔADC is very sensitive to the clock jitter.In contrast, DT type is not so.
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Performance of DS ADC
BW [MHz]
ENO
B
4
6
8
10
12
14
16
18
0.01 0.1 1 10 100 1000
FlashSubrangingpipelinedSARfolding
Sigma-Delta
BW of DS ADC becomes wider to 20MHz
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Understanding of DS ADC
)()(
1)(
)()(1
1)()(1)()(
zQzH
zX
zQzH
zXzHzHzY
n
n
LPF+
Quantizationnoise:QN
X Y
-
DAC
XH(z)
Y’
YX
-A
Vn
ΔΣMod
Negative feedback
nn VA
XVA
XAAY 1
11
1
ΔΣMod
Negative feedback )1)(( zH
Loop gain of integrator
sf
jf
jff
ffje
zzH sss
s
ffjs
2211
1
1
111)(
21
High gain for low frequency
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High dynamic range design
P. Balmelli, et al., ISSCC 2004
Sigma delta method with multi-bit quantizer and dynamic element matching technique realized 25MS/s, 80dB ADC.
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Add new functionSigma-delta ADC can change the performance by changing over sampling ratio and filter characteristics. High DR and narrow BW
Low DR and wide BW Compatible:
T. Burger and Q. Huang, ISSCC 2001
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Add new function
K. Philips, ISSCC 2003
Complex band-pass sigma-delta
gm-C filter5th order complex sigma-delta 1b, @64MHz
Delta-sigma ADC can use complex band-pass filter.Analog filter and VGA can be removed from IF stage.
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Design example of ΣΔ型ADC
Signal bandwidth:10MHzDynamic range: >80dB
Matsuzawa Lab. Now designing high speed sigma delta ADC
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Architecture
シミュレーションの概要
1、上図のフィルタの係数を決定する
2、以下の可変パラメータ・ノイズ・非理想性を加えたモデルの作成振幅・周波数等 量子化器積分非直線性誤差オーバーサンプリング率 DAC素子ばらつき量子化分解能 オペアンプノイズジッター オペアンプゲインスルーイング 振幅範囲
サンプリング容量(kT/Cノイズ)
3、各パラメータを変化させてシミュレーションを行いSNRをグラフ化、考察
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Transfer function, pole and zero location for stability
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Simulation model with Simulink
積分器係数0.75 0.40 0.30 0.15 0.15ローカルフィードバック係数0.05 0.25(比較用に 0.0 0.0 も)
信号帯域 10MHzサンプリング周波数 640MHz(オーバーサンプリング率32)量子化器分解能 4bit
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SNR vs. Input signal intensity
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SNR vs. M
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SNR vs. Quantizing level
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SNR vs. Jitter
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SNR vs. Capacitor
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SNR vs. quantizer INL
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SNR vs. DAC nonlinearity
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SNR vs. gain of OP amp
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References
• J.C. Candy and G.C. Tems, “Oversampling Delta-Sigma Converters,” IEEE Press, 1992.
• Rudy van de Plassche, “ CMOS Integrated Analog to Digital and Digital to Analog Converters,” Kluwer.
• F. Medeiro, A. Perez-Verdu and A. Rodriguez-Vazquez, “Top-Down Design of High-Performance Sigma-Delta Modulators,”, Kluwer.
• C. Toumanzou, G. Moschytz, and B. Bilbert, “Trade-offs in Analog Circuit Design,” Kluwer.
• 岩田 「CMOSアナログ回路設計技術」 トリケップス