International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 23 (2016) pp. 11491-

© Research India Publications. http://www.ripublication.com

11491

LFM chirp signal synthesis using FPGA and DAC

S. A. Ermushev1 and A. V. Tsarkov2

1CEO, Clustech LLC, 124498 Moscow, Zelenograd, Georgievsky pr. d. 5, str. 1., Russia.

2Senior Researcher, Clustech LLC 124498 Moscow, Zelenograd, Georgievsky pr. d. 5, str. 1. Russia.

Abstract

The use of synthetic aperture radar for UAVs allows to obtain

detailed contrast images of ground surface with the resolution up

to 50 cm regardless of meteorological and light conditions. Such a

high resolution is made possible with wideband linear frequency

modulated (LFM) chirp signals. Recent developments in digital

radar subsystems illustrate a trend toward digital methods in

synthesis of complex waveforms, including the use of FPGA. The

paper is concerned with the principles of building a LFM chirp

signal synthesizer using FPGA and DAC.

Keywords: LFM chirp signal, SAR, FPGA, DAC.

INTRODUCTION

Continuous wave linear frequency modulated (LFM) radars are

widely used for many civil and military tasks such as mapping,

remote sensing, missile guidance and global positioning [1-3]. In

recent years, an interest is growing for remote sensing using

unmanned aerial vehicles (UAV) as an alternative platform for

synthetic aperture radars (SAR). Compared to classical space-

borne SAR, synthetic aperture radar placed on UAV has lower

development and operation cost and can be used for radar ground

monitoring tasks with high repetition requirements.

This paper presents the results of development and

implementation of a direct digital synthesis (DDS) architecture on

field programmable gate arrays (FPGA). The main advantage of

FPGA for DDS systems is its speed performance. A DDS

architecture can be downloaded into FPGA as many times as

needed, without restrictions for functional capability. As opposed

to the development of signal synthesizers by hardware, the use of

FPGA has an additional advantage of correcting design errors by

simply adjusting logical functions and links, not by replacing the

hardware components.

Direct digital synthesis based on the system of frequency-

dependent sequence generation allows for required accuracy and

low noise, while the use of modern FPGA allows, within a single

chip, to place a generator and filters, and apply algorithms of

digital processing and synthesis of radar imagery. For the

synthesis of complex signals, a generated binary code has to be

converted to the analog signal using digital-analog converters

(DAC). This paper describes a combination of FPGA and ADC

that form a system of digital radar signal synthesis to be used in

X-band LFM SAR for UAV.

DEVELOPMENT OF FPGA-BASED DDS SYSTEM

The key component of modern SAR is a direct digital

synthesis SP system are FPGA, ADC and DAC that provide

full advantages of a compact and reconfigurable architecture.

DAC is used in the transmit channel to generate complex

waveforms that are calculated in the FPGA core. Depending

on the flight altitude and the required ranging distance, the

signal form and duration can be configured. FPGA firmware

is a combination of configurable logic blocks, similar to the

switches for complex combination functions (calculator,

multiplexor and decoder, memory). In digital circuits, such

switches implement basic binary operations such as AND,

OR, NOT.

One of the popular architectures of digital LFM signal

synthesizers is the direct digital synthesis architecture. This

approach is based on the generation of the digital code that is

changed over time with the subsequent conversion into the

analog signal using DAC. The synthesizer performs a short

switching between the output frequencies, allowing for a high

resolution and a wide bandwidth. A simplest example of a

digital generator of this kind, that can be implemented on

FPGA, will consist of the frequency reference source fc,

address counter, look-up table and DAC [4-7]. Digital

information about the amplitude of the full cycle sinusoid is

stored into the memory block. The address counter goes

through each look-up table element and extracts the required

value, which is transferred to DAC. A diagram of DDS

architecture is presented in Fig. 1.

Figure 1. Proposed DDS Architecture.

International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 23 (2016) pp. 11491-11493

© Research India Publications. http://www.ripublication.com

11492

Figure 2. Phase locking and stabilization in the outside PLL for digital signal synthesis.

The algorithm of digital signal synthesis is implemented in

Verilog for the subsequent programming of FPGA Stratix IV.

Apart from the FPGA kernel, the algorithm uses various

peripheral equipment and external dynamic memory modules. An

imbedded tool Qsys is used to automate the connection of

external devices to the kernel using standard interfaces.

From an external very stable oscillator a reference signal ref_clc

is transmitted with the frequency of 100 MHz (10 ns period) and a

10 ns frequency reset signal pll_areset. For the next 45 ns, a

locking of the local oscillator phase is carried out with the phase-

lock loop (PLL). When the local oscillator phase is locked (Fig. 2,

55 ns point) the signal value output of pll_locked changes from 0

to 1; a clock signal with the LVDS input signaling frequency of

1600 MHz is sent from the output 0, while from the output 1 a

clock signal with the output signaling frequency of 300 MHz. At

the same time, the generated signal is sent into the LVDS

channels.

It is not always possible to process the input data in real time, that

is why an external memory module is used as their temporary

storage. The module databus is 64-bit wide, while the recording

frequency is selected to be divisible by the sampling frequency

output of FPGA 480 MHz = 3*160 MHz.

In order to synchronize the data transmission frequency into

RAM memory and the data receive frequency from FPGA, a

buffer has to be used to store the data during the recording.

Therefore, 240-bit words input of buffer will be added with

zeroes and transmitted by parts into the RAM memory as 64-bit

words.

RESULTS

In order to verify the proposed architecture and solutions a DAC

evaluation board based on IC AD9129 has been developed and

manufactured. As a main calculation unit, the system uses

FPGA Altera Stratix IV EP4SGX230KF40C2N.

DAC and FPGA are implemented as separate PCBs and have

their own feeding and clock circuits as well as corresponding

input-output ports for mutual connection and connection to

peripheral equipment. Apart from the transmission of radar

signals, FPGA sends control signals to DAC and to the

corresponding frequency clock synthesizers ADF4351 by

Analog Devices. ADC AD9129 and the clock synthesizer

ADF4351 is controlled via SPI interface. Control signals

from FPGA Stratix IV via HSMC ports.

Fig. 3 shows the topology of the DAC board that has been

designed according to IPC-2221A requirements. The

evaluation board is designed in such a way that low

frequency, high frequency and super-high frequency

components are separated at different parts of the board.

Fig. 4 shows a picture of the manufactured board.

Figure 3. DAC board topology.

International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 23 (2016) pp. 11491-11493

© Research India Publications. http://www.ripublication.com

11493

Figure 4. Manufactured DAC board.

Fig. 5 shows the signal spectrum with 300 MHz bandwidth which

has been generated using FPGA and DAC. Real time spectrum

analyzer Tektronix RSA6100A has been used to measure the

main radar characteristics.

Figure 5. FPGA based DDS generated LFM chirp bandwidth of

300 MHz.

CONCLUSION

In this paper, the principles of building a system for direct digital

synthesis of radar LFM chirp signal for UAV SAR have been

presented. The DAC board have been developed which, along

with FPGA Stratix IV evaluation board, form a basis for a digital

part of a modern radar with 300 MHz bandwidth allowing for

remote sensing with high resolution.

ACKNOWLEDGEMENTS

The research has been supported by the Ministry of

Education and Science of the Russian Federation in the

framework of the Federal Target Program “Research and

development in the priority fields of Russia’s research and

technology industry 2014-2020”; project ID

RFMEFI57614X0041.

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