layout compliance for triple patterning lithography: an...

Layout Compliance for Triple PatterningLithography: An Iterative Approach

Bei Yu†, Gilda Garreton‡, David Z. Pan†

†ECE Dept. University of Texas at Austin, Austin, TX, USA‡Oracle Labs, Oracle Corporation, Redwood Shores, CA, USA

09/16/2014

1 / 27

Outline

Introduction

New Challenges in Triple Patterning Lithography (TPL)

Layout Compliance Algorithms

Results and Conclusions

2 / 27

Outline

Introduction




3 / 27

Lithography Status & Challenges

1980 1990 2000 2010 2020

10

1

0.1

um

[Courtesy Intel]

X

Advanced lithography to extend 193nm lithographyI Now and near future: double/triple/quadruple patterningI Long term future: other advanced lithography

4 / 27

From Double Patterning to Triple Patterning

ITRS roadmap

28nm Single Patterning

22nm Double Patterning

14nm Triple Patterning

11nm Quadruple Patterning

Mask 2

Mask 1

stitch

Mask 1 Mask 2 Mask 3

I Layout decompositionI Patterning friendly design

5 / 27

Previous Works in TPL Layout DecompositionI ILP or SAT

[Cork+,SPIE’08][Yu+,ICCAD’11][Cork+,SPIE’13]I Greedy or Heuristic

[Ghaida+,SPIE’11][Fang+,DAC’12][Kuang+,DAC’13][Yu+,DAC’14][Fang+,SPIE’14]

I SDP or Graph based (trade-off)[Yu+, ICCAD’11][Chen+,ISQED’13][Yu+,ICCAD’13]

Limitations: can NOT guarantee TPL friendly

(a) (b)

6 / 27

Layout Compliance Problem FormulationInput:

I Input layout patterns (may not be TPL friendly)I Minimum coloring distance mins

a

b

c

d

a1

a2 b

c

d1

d2

a1

a2 b

c

d1

d2

(b) (c)(a)

Output:I Apply layout decomposition and layout modificationI Remove all conflicts

7 / 27

Layout Decomposition v.s. Layout Compliance

a

b

c

d

(b) Layout decomposition (c) Layout Modification(a) Input layout

a

b

c

d

c

b

a

d

Layout Compliance

= Layout Decomposition + Layout Modification

8 / 27

Outline

Introduction




9 / 27

Challenge 1: NO Shortcut in TPLComplexityOptimizing conflict & stitch simultaneously is NP-hard for DPL/TPL.

Shortcut in DPL:I Step by stepI Each step can be optimally solved

(a) (b) (c)

Input Layout Step 1:Conflict MinimizationStep 2:

Stitch Minimization

TPL:I NO such shortcut, as conflict minimization is NP-hardI Door closed?

10 / 27

Challenge 2: Where do the conflicts come from?DPL:

I Detect odd-cycleI Long pattern chains

(a) (b)

TPL:I NP-hard to detectI But mostly local 4-clique

(a) (b) (c)

11 / 27

Challenge 3: Decomposer – Clutching at Straws

CPU runtime

Conflict #

Performance targetILP: Good performance

but expensive

Greedy or heuristic: Fast but bad quality

SDP or graph search: Tradeoff,still not good in performance

I GapI Our performance target

12 / 27

Outline

Introduction


Layout Compliance AlgorithmsStep 1: Initial Layout DecompositionStep 2: Layout ModificationStep 3: Incremental Layout Decomposition


13 / 27

Overall Flow

Input Layout

Decomposition Graph Construction

1. Fast Initial Layout Decomposition

2. Layout Modification

Output Masks

3. Incremental Layout Decomposition

14 / 27

Overall Flow

Input Layout




Output Masks


a

b

c

d

14 / 27

Overall Flow

Input Layout




Output Masks


a1

a2 b

c

d1

d2

14 / 27

Overall Flow

Input Layout




Output Masks


a1

a2 b

c

d1

d2

native structurebehind conflict

14 / 27

Overall Flow

Input Layout




Output Masks


a1

a2 b

c

d1

d2

14 / 27

Overall Flow

Input Layout




Output Masks


a1

a2 b

c

d1

d2

color re-assignment region

14 / 27

Overall Flow

Input Layout




Output Masks


a

b

c

d

14 / 27

Step 1: Initial Layout Decomposition

I Our method: linear color assignmentI Linear runtime complexity [Yu+,DAC’14]I May leave some conflicts to Step 2 & 3I Much faster than ILP or SDP

a1

a2 b

c

d1

d2

a1

a2 b

c

d1

d2

native structurebehind conflict

Runtime comparisions:

15 / 27

Step 1: Fast Layout Decomposition (cont.)

I But, Any coloring order results in Local OptimalityI Example: order a-b-c-d

a c

d

ba c

d

b

(a) (b)

b ca

d

Half Pitch

(c)

b ca

d

a c

d

b

(d)

Color-Friendly Rules:I a-c tend to be with the same color

16 / 27

Step 1: Fast Layout Decomposition (cont.)Peer Selection:

I Three orders would be processed simultaneouslyI Best solution would be selectedI Still Linear runtime complexity

3Round-Coloring

Degree-Coloring

Sequence-Coloring

17 / 27

Step 1: Fast Layout Decomposition (cont.)Peer Selection:

I Whole problem → a set of componentsI Different components have different dominant ordersI Overall better results than any single order

18 / 27

Fast Layout Decomposition Result Example

I Row by rowI Resolved in 0.1 second

19 / 27

Step 2: Layout ModificationInitial layout decomposition output: native conflict is labeled:

(a) (b)

Layout modification to break down each four-clique:

(a) (b)

20 / 27

Step 3: Incremental Layout Decomposition

I Input: One layout region & stitch# boundI Output: color re-assignment in the regionI Method: branch-and-boundI Early return if satisfy stitch# bound

a1

a2 b

c

d1

d2

a1

a2 b

c

d1

d2

color re-assignment region

Runtiem & stitch# bound trade-off:

21 / 27

Step 3: Incremental Layout Decomposition– Example

(a) (b)

(c) (d)

a Decomposed result after initial layout decomposition.b All layout patterns to be re-assigned colors are labeled.c The constructed local decomposition graph.d The result of incremental layout decomposition.

22 / 27

Outline

Introduction




23 / 27

Interfaced with open source tool Electric

24 / 27

Layout Compliance Results

25 / 27

ConclusionsI First attempt for TPL layout complianceI Faciliating the advancement of patterning technique

CPU runtime

Conflict #

Performance targetILP: Good performance

but expensive

Greedy or heuristic: Fast but bad quality

SDP or graph search: Tradeoff,still not good in performance

-

Future worksI Timing issueI Smarter automatically layout modification

26 / 27

Thank You !27 / 27

Main TalkIntroductionNew Challenges in Triple Patterning Lithography (TPL)Layout Compliance AlgorithmsStep 1: Initial Layout DecompositionStep 2: Layout ModificationStep 3: Incremental Layout Decomposition


layout compliance for triple patterning lithography: an...

Documents