introduction to sequential logic design flip-flops
TRANSCRIPT
![Page 1: Introduction to Sequential Logic Design Flip-flops](https://reader036.vdocuments.us/reader036/viewer/2022081418/56649e3b5503460f94b2d810/html5/thumbnails/1.jpg)
Introduction to Sequential Logic Design
Flip-flops
![Page 2: Introduction to Sequential Logic Design Flip-flops](https://reader036.vdocuments.us/reader036/viewer/2022081418/56649e3b5503460f94b2d810/html5/thumbnails/2.jpg)
2
Prev…
Latches S-R S-bar-R-bar S-R with enable signal D
![Page 3: Introduction to Sequential Logic Design Flip-flops](https://reader036.vdocuments.us/reader036/viewer/2022081418/56649e3b5503460f94b2d810/html5/thumbnails/3.jpg)
3
FF vs. Latch
Latches and flip-flops (FFs) are the basic building blocks of sequential circuits.
latch: bistable memory device with level sensitive triggering (no clock), watches all of its inputs continuously and changes its outputs, independent of a clocking signal.
flip-flop: bistable memory device with edge-triggering (with clock), samples its inputs, and changes its output only at times determined by a clocking signal.
![Page 4: Introduction to Sequential Logic Design Flip-flops](https://reader036.vdocuments.us/reader036/viewer/2022081418/56649e3b5503460f94b2d810/html5/thumbnails/4.jpg)
4
Edge triggered D Flip-Flop
A D FF combines a pair of D latches. Master/slave
D FF Positive-edge-triggered D FF Negative-edge-triggered D FF Edge-Triggered D FF with Enable Scan FF
![Page 5: Introduction to Sequential Logic Design Flip-flops](https://reader036.vdocuments.us/reader036/viewer/2022081418/56649e3b5503460f94b2d810/html5/thumbnails/5.jpg)
5
Positive-Edge-triggered D flip-flop
![Page 6: Introduction to Sequential Logic Design Flip-flops](https://reader036.vdocuments.us/reader036/viewer/2022081418/56649e3b5503460f94b2d810/html5/thumbnails/6.jpg)
6
Positive-Edge-triggered D flip-flop
Dynamic-input indicator
![Page 7: Introduction to Sequential Logic Design Flip-flops](https://reader036.vdocuments.us/reader036/viewer/2022081418/56649e3b5503460f94b2d810/html5/thumbnails/7.jpg)
7
Edge-triggered D flip-flop behavior
![Page 8: Introduction to Sequential Logic Design Flip-flops](https://reader036.vdocuments.us/reader036/viewer/2022081418/56649e3b5503460f94b2d810/html5/thumbnails/8.jpg)
8
Edge-triggered D flip-flop behavior
![Page 9: Introduction to Sequential Logic Design Flip-flops](https://reader036.vdocuments.us/reader036/viewer/2022081418/56649e3b5503460f94b2d810/html5/thumbnails/9.jpg)
9
Edge-triggered D flip-flop behavior
![Page 10: Introduction to Sequential Logic Design Flip-flops](https://reader036.vdocuments.us/reader036/viewer/2022081418/56649e3b5503460f94b2d810/html5/thumbnails/10.jpg)
10
D flip-flop timing parameters
Propagation delay (from CLK) Setup time (D before CLK) Hold time (D after CLK)
![Page 11: Introduction to Sequential Logic Design Flip-flops](https://reader036.vdocuments.us/reader036/viewer/2022081418/56649e3b5503460f94b2d810/html5/thumbnails/11.jpg)
11
D FF with asynchronous inputs
Force the D FF to a particular state independent of the CLK and D inputs. PR (Preset) and CLR (Clear)
![Page 12: Introduction to Sequential Logic Design Flip-flops](https://reader036.vdocuments.us/reader036/viewer/2022081418/56649e3b5503460f94b2d810/html5/thumbnails/12.jpg)
12
Negative-edge triggered D FF
Simply inverts the clock input. Active low.
![Page 13: Introduction to Sequential Logic Design Flip-flops](https://reader036.vdocuments.us/reader036/viewer/2022081418/56649e3b5503460f94b2d810/html5/thumbnails/13.jpg)
13
Negative-edge triggered D FF
Simply inverts the clock input. Active low.
![Page 14: Introduction to Sequential Logic Design Flip-flops](https://reader036.vdocuments.us/reader036/viewer/2022081418/56649e3b5503460f94b2d810/html5/thumbnails/14.jpg)
14
J-K flip-flops
![Page 15: Introduction to Sequential Logic Design Flip-flops](https://reader036.vdocuments.us/reader036/viewer/2022081418/56649e3b5503460f94b2d810/html5/thumbnails/15.jpg)
15
T (toggle) flip-flops
A T FF changes state on every tick of the clock. (be toggled on every tick) Q has precisely half the frequency of the T. Important for counters Positive-edge-triggered T FF
How to build T FF using J-K FF and D FF?
![Page 16: Introduction to Sequential Logic Design Flip-flops](https://reader036.vdocuments.us/reader036/viewer/2022081418/56649e3b5503460f94b2d810/html5/thumbnails/16.jpg)
16
T (toggle) flip-flops with enable
How to build a T FF with enable using? D FF J-K FF
![Page 17: Introduction to Sequential Logic Design Flip-flops](https://reader036.vdocuments.us/reader036/viewer/2022081418/56649e3b5503460f94b2d810/html5/thumbnails/17.jpg)
17
T (toggle) flip-flops with enable
![Page 18: Introduction to Sequential Logic Design Flip-flops](https://reader036.vdocuments.us/reader036/viewer/2022081418/56649e3b5503460f94b2d810/html5/thumbnails/18.jpg)
18
Next…
FSM analysisRead Ch-7.3