ee365 adv. digital circuit design clarkson university lecture #10 latches, flip flops &...
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EE365Adv. Digital Circuit Design
Clarkson University
Lecture #10
Latches, Flip Flops & Sequential PALS
Topics
• Basic Definitions
• Latches
• Edge-Triggered Flip-Flops
• Timing Requirements
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Sequential Circuits
• Output depends on current input and past history of inputs.
• “State” embodies all the information about the past needed to predict current output based on current input.– State variables, one or more bits of
information.
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Describing Sequential Circuits
• State table– For each current-state,
specify next-states as function of inputs
– For each current-state, specify outputs as function of inputs
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Describing Sequential Circuits
• State diagram– Graphical version of state table
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Clock signals
• Very important with most sequential circuits– State variables change state at clock edge.
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Bistable element• The simplest sequential circuit
• Two states– One state variable, say, Q
HIGH LOW
LOW HIGH
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Bistable element• The simplest sequential circuit
• Two states– One state variable, say, Q
LOW HIGH
HIGH LOW
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Analog analysis• Assume pure CMOS thresholds, 5V rail
• Theoretical threshold center is 2.5 V
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Analog analysis
• Assume pure CMOS thresholds, 5V rail
• Theoretical threshold center is 2.5 V2.5 V 2.5 V
2.5 V 2.5 V
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Analog analysis
• Assume pure CMOS thresholds, 5V rail
• Theoretical threshold center is 2.5 V
2.5 V
2.5 V 2.5 V
2.0 V
2.0 V 4.8 V
2.5 V2.51 V4.8 V 0.0 V
0.0 V 5.0 V
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Metastability
• Metastability is inherent in any bistable circuit
• Two stable points, one metastable point
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Another look at metastability
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“sube y baja” behavior
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Why all the harping on metastability?
• All real systems are subject to it– Problems are caused by “asynchronous inputs” that
do not meet flip-flop setup and hold times.– Details in Chapter-7 flip-flop descriptions and in
Section 8.9– Especially severe in high-speed systems– since clock periods are so short, “metastability
resolution time” can be longer than one clock period.
• Many digital designers, products, and companies have been burned by this phenomenom.
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Back to the bistable….
• How to control it?– Screwdriver– Control inputs
• S-R latch
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S-R latch operation
Metastability is possibleif S and R are negatedsimultaneously.
(try it in Foundation)
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S-R latch timing parameters
• Propagation delay
• Minimum pulse width
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S-R latch symbols
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S-R latch using NAND gates
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S-R latch with enable
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D latch
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D-latch operation
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D-latch timing parameters• Propagation delay (from C or D)
• Setup time (D before C edge)
• Hold time (D after C edge)
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Edge-triggered D flip-flop behavior
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D flip-flop timing parameters• Propagation delay (from CLK)
• Setup time (D before CLK)
• Hold time (D after CLK)
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TTL edge-triggered D circuit• Preset and
clear inputs– like S-R
latch
• 3 feedback loops– interesting
analysis
• Light loading on D and C
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CMOS edge-triggered D circuit• Two feedback loops (master and slave latches)• Uses transmission gates in feedback loops• Interesting analysis method (Sec. 7.9)
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Other D flip-flop variations
• Negative-edge triggered
• Clock enable
• Scan
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Scan flip-flops -- for testing
• TE = 0 ==> normal operation• TE = 1 ==> test operation
– All of the flip-flops are hooked together in a daisy chain from external test input TI.
– Load up (“scan in”) a test pattern, do one normal operation, shift out (“scan out”) result on TO.
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J-K flip-flops
• Not used much anymore
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T flip-flops
• Important for counters
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In Class Practice Problem
The characteristic Equation for a D latch is:
Q* = D
Write the Characteristic Equation for an S-R latch
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In Class Practice Problem
The characteristic Equation for an S-R latch is:
Q* = S + R’ • Q
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In Class Practice Problem #2
Write characteristic equations for each of the following:
• J-K flip flop• T flip flop• T flip flop with enable
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In Class Practice Problem #2
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J-K flip flop:
T flip flop:
In Class Practice Problem #2
Write characteristic equations for each of the following:
• J-K flip flop– Q* = J • Q’ + K’ • Q
• T flip flop– Q* = Q’
• T flip flop with enable– Q* = EN • Q’ + EN’ • Q
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• SSI LATCHES and Flip-Flops
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Sequential PALs
• 16R8
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One output of 16R8
• 8 product terms to D input of flip-flop– positive edge triggered, common clock for all
• Q output is fed back into AND array– needed for state machines and other applications
• Common 3-state enable for all output pins
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PAL16R6
• Six registered outputs
• Two combinational outputs (like the 16L8’s)
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GAL16V8
• Each output is programmable as combinational or registered
• Also has programmable output polarity
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GAL16V8 output logic macrocell
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GAL22V10
• More inputs
• More product terms
• More flexibility
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GAL22V10 output logic macrocell
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Next time
• State Machine Types
• State machine Design
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