introduction to sequential logic design flip-flops fsm analysis
TRANSCRIPT
Introduction to Sequential Logic Design
Flip-flops
FSM Analysis
Prev… Latches
S-R S-bar-R-bar S-R with enable signal D
D latch
D
C
Q
Q
D-latch operation
When C is asserted, Q follows the D input, the latch is “open” and the path (D-->Q) is “transparent”.
When C is negated, the latch “closes” and Q retains its last value.
D-latch timing parameters
Propagation delay (from C or D) Setup time (D before C edge) Hold time (D after C edge)
S-R vs D latches S-R
Useful in control applications, “set” and “reset” S=R=1 problem Metastability problem when S, R are negated
simultaneously, or a pulse applied to S, R is too short.
D Store bits of information No S=R=1 problem Metability still possible.
FF vs. Latch
Latches and flip-flops(FFs) are the basic building blocks of sequential circuits.
latch: bistable memory device with level sensitive triggering (no clock), watches all of its inputs continuously and changes its outputs, independent of a clocking signal.
flip-flop: bistable memory device with edge-triggering (with clock), samples its inputs, and changes its output only at times determined by a clocking signal.
Edge triggered D Fli-Flop A D FF combines a pair of D latches.
Master/slave D FF
Positive-edge-triggered D FF Negative-edge-triggered D FF Edge-Triggered D FF with Enable Scan FF
Positive-Edge-triggered D flip-flop
Dynamic-input indicator
Edge-triggered D flip-flop behavior
D flip-flop timing parameters
Propagation delay (from CLK) Setup time (D before CLK) Hold time (D after CLK)
D FF with asynchronous inputs
Force the D FF to a particular state independent of the CLK and D inputs. PR (Preset) and CLR (Clear)
Negative-edge triggered D FF
Simply inverts the clock input. Active low.
Edge-triggered D FF with Enable
Scan flip-flops -- for testing
TE = 0 ==> normal operation TE = 1 ==> test operation
All of the flip-flops are hooked together in a daisy chain from external test input TI.
Load up (“scan in”) a test pattern, do one normal operation, shift out (“scan out”) result on TO.
Scan FF
J-K flip-flops
Not used much anymore
T (toggle)flip-flops
A T FF changes state on every tick of the clock. (be toggled on every tick)
Q has precisely half the frequency of the T. Important for counters, frequency dividers
Positive-edge-triggered T FF
T (toggle)flip-flops with enable
Clocked Synchronous State-Machine
State machine: generic name for sequential circuits;(Finite State Machine:FSM)
Clocked: the storage elements(FFs) use a clock input;
Synchronous: all of the FFs in a circuit use the same clock signal.
Such a FSM changes states only when a triggering edge(rising or falling) on the clock signal.
State Machine Structure
State memory: n FFs to store current states. All FFs are connected to a common clock signal.
Next-state logic: determine the next state when state changes occur;
Output logic: determines the output as a function of current state and input
Mealy machine vs. Moore machine
Mealy Machine
Next state= F (current state, input)Output= G(current state, input)
Moore Machine
Next state= F (current state, input)Output= G(current state)
Characteristic Equations A Characteristic equation specifies the FF’s (or latch’s)
next state as a function of its current state and inputs.
Analysis of FSM with D FFsNext state= F (current state, input)Output= G(current state, input)
Step 1: Determine the next-state and output functions F, G Step 2: Use F, G to construct a state/output table that completely specifies the next state and output of the circuit for every possible combination of current state and input.
Step 3: (optional) Draw a state diagram which is a graphical form of the state/output table.
Example: clocked synchronous FSM using positive-edge triggered D FFs
Transition, state, state/output tables
Excitation equations
Transition Equations (next-state equations)
Output equations
State Diagram
Summary: how to analyze a clocked symchronous state machine?
1) Determine the excitation equations for the FF control inputs;
2) Substitute the excitation equatiions into the FF characteristic equations to obtain transition equations;
3) Use the transition equations to construct a transition table;4) Determine the output equations;5) Add output values to the transition table for each state
(Moore) or state/input combination (Mealy) to create a transition/output table;
6) Name the states and substitute state names for state-variable combinations in the transition/output table to obtain state/output table;
7) Draw a sate diagram corresponding to the state/output table.