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Electronic Design Process

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Introduction to VHDLIntroduction to VHDL

NiveauxNiveaux dabstractiondabstraction pour la conceptionpour la conception numriquenumrique

Chaque niveau d'abstraction dfinit un description de la circuit avec moins ou plus de

dtails par rapport au niveaux infrieur ou suprieur

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Code comportementaldcrit les fonctionnalitset le comportement de

la circuit

Introduction to VHDLIntroduction to VHDL

Behavioral vs. RTL (Structural)Behavioral vs. RTL (Structural)

Code structural dcrit la

niveau registres et porte

logique de circuit

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RTL

SimulationSynthse

Gate

Level

SimulationLay-outPlacement/routage

FPGA ASIC

Flot de

conceptionBehavioral

Testbench

Tech.

Lib.

Simui.

Lib.

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Cest quoit VHDL?

VHSIC

Hardware

Description

Language

VHSIC Very High Speed Integrated Circuit

vhdl

Fonctions

concurrents

Description

hirarchique

Fonctions

squentielles

Modlisation

de temps

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6

VHDL: concepts de base

Structure gnraleVotre fichier texte de

description: xxx.vhd

Mode transfert des

signaux de votre

entity

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VHDL:Les en-ttes de fichier

LibraryIEEE ;

Use IEEE.std_logic_1164.all;

Use IEEE.std_logic_arith.all;

.

Le mot use : indique quelle package de la librairie nous allons utiliser

Il faut pas utiliser Numeric_std et std_logic_arith en mme temps pour ne pas avoir

conflit

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VHDL:Lentit

entity sequencement is

Port (

clock : in std_logic;

reset : in std_logic;

Q : out std_logic_vector (1 down to 0)

);End sequencement ;

sequencement

Clock

reset

Q(1:0)

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VHDL: Dclaration de l'architecture

Rfrence

une entit

Nom de

larchitecture

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The 2-to-1 Multiplexer

Introduction to VHDLIntroduction to VHDL

d0

d1

f

s

ENTITY mux2to1 ISPORT( d0, d1, s :IN STD_LOGIC;f :OUT STD_LOGIC);

END mux2to1;

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Description compartmental

If s=0, d0 passes sur la sortie f: f=d0

If s=1, d1 passes sur la sortie f=d1

Introduction to VHDLIntroduction to VHDL

d0

d1

f

s

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Introduction to VHDLIntroduction to VHDL

d0

d1

f

s

ARCHITECTURE behavior OF mux2to1 IS

BEGIN

WITH s SELECTf

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Description structuralDescription structural

Introduction to VHDLIntroduction to VHDL

d0

d1

f

s

d0

d1

s

f

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Introduction to VHDLIntroduction to VHDL

d0

d1

f

s

d0

d1

s

f

ARCHITECTURE structure OF mux2to1 IS

BEGINf

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Un bon exemple est la construction d'un multiplexeur(4-pour-1) partir de 2 (Muxes 2-pour-1 ) qui seront

utilis comme composants

HierarchieHierarchie

Introduction to VHDLIntroduction to VHDL

d0

d1

f

d2

d3

s0s1

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The 4-to-1 Mux

Introduction to VHDLIntroduction to VHDL

d0

d1

f

d2

d3

ENTITY mux4to1 ISPORT( d0, d1, d2, d3, s0, s1 : IN STD_LOGIC;

f : OUT STD_LOGIC);

END mux4to1;

d0

d 1

f

d2

d3

s 1 s 0

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Introduction to VHDLIntroduction to VHDLIntroduction to VHDLIntroduction to VHDL

d0

d 1

fd2

d3

s 1 s 0

ENTITY mux4to1 ISPORT(w0, w1, w2, w3, sel0, sel1 :IN STD_LOGIC;

f :OUTSTD_LOGIC);

END mux4to1;

ARCHITECTURE structure OF mux4to1 IS

SIGNALI1, I2 :STD_LOGIC;

COMPONENT mux2to1

PORT(d0, d1, s :IN STD_LOGIC;f :OUTSTD_LOGIC);

END COMPONENT;

BEGIN

u1:mux2to1 PORT MAP(w0, w1, sel0, I1);

u2:mux2to1 PORT MAP(w2, w3, sel0, I2);

u3:mux2to1 PORT MAP(I1, I2, sel1, f);

END structure;

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Processes

Un processus est une rgion de code VHDL qui

excute squentiellement

Existe l'intrieur de l'architecture

Plusieurs processus sexcutent en

concurrence les uns avec les autres

Introduction to VHDLIntroduction to VHDL

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Introduction to VHDLIntroduction to VHDL

ProcessesProcesses

ENTITY orgate IS

PORT (a,b : in bit;

z : out bit);

END orgate;

ARCHITECTURE Behavior OR orgate IS

BEGIN

or_func: PROCESS (a,b)

BEGIN

IF (a='1' OR b='1') THEN

z

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Back to the 4-to-1 Mux example

Introduction to VHDLIntroduction to VHDL

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY mux2to1 IS

PORT (d0, d1, s :IN STD_LOGIC;

f :OUTSTD_LOGIC);

END mux2to1;

ARCHITECTURELogicFunc OF mux2to1 IS

BEGIN

f

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Types

Introduction to VHDLIntroduction to VHDL

ENTITY fulladd IS

PORT (a,b,Cin : IN bit;

sum, Carry : OUT bit);

END fulladd;

ARCHITECTURE struct OF fulladd IS

SIGNAL n_sum : bit;

-- oth

er declarationsBEGIN

-- Code

END struct;

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When an assignment is made to a signal,

the types on either side of the signal

assignment operator must match up

Introduction to VHDLIntroduction to VHDL

TypesTypes

ENTITY fulladd IS

PORT (a,b,Cin :IN bit;

Sum, Carry: OUT bit);

END fulladd;

ARCHITECTURELogic OF fulladd IS

BEGIN

Sum

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Types prdfinis

Introduction to VHDLIntroduction to VHDL

PACKAGE standard ISTYPE boolean IS (true, false);

TYPE bit IS (0, 1)

TYPE character IS (-- ascii set)

TYPE integer IS range implementation_defined;

TYPE real IS range implementation_defined;

-- bit_vector, string, timeEND standard;

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Types predefinsTypes predefins

Introduction to VHDLIntroduction to VHDL

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Standard Logic represented byIEEE 1164

In general, std_logic should be used ALL OF

THETIME

Introduction to VHDLIntroduction to VHDL

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Introduction to VHDLIntroduction to VHDL

ArraysArrays

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Introduction to VHDLIntroduction to VHDL

Assignment des matricesAssignment des matrices

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Introduction to VHDLIntroduction to VHDL

Assignment de matrixAssignment de matrix

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Introduction to VHDLIntroduction to VHDLIntroduction to VHDLIntroduction to VHDL

matrices etmatrices et ConcatenationConcatenation

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Introduction to VHDLIntroduction to VHDL

ArraysArrays etetAggregatesAggregates

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Introduction to VHDLIntroduction to VHDL

Assignment dun matrixpar nomAssignment dun matrixpar nom

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Introduction to VHDLIntroduction to VHDL

Assignment dun matrixpar nomAssignment dun matrixpar nom

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VHDL Operators

Il existe 3 varits d'oprateurs: logique, relationnel,et arithmtique.

Les oprateurs logiques sont "et", "ou", etc

Les oprateurs relationnels sont utiliss pourcomparer les diffrentes valeurs

Les oprateurs arithmtiques sont utilises poureffectuer des fonction mathmatiques

Introduction to VHDLIntroduction to VHDL

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Comprend ET, OU, NAND, NOR, XOR et NOT

Tous ont la mme priorit

Excuter de gauche droite

NOT a la plus grande priorit, et excute donc avant

d'autres oprateurs dans une expression logique.

Les oprations logiques ne peut tre applique que

des matrice du mme type et de mme longueur Correspondants des lments dans des matrice se

fait par POSITION

Introduction to VHDLIntroduction to VHDL

VHDL OperatorsVHDL Operators -- LogicalLogical

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Introduction to VHDLIntroduction to VHDL

VHDL OperateursVHDL Operateurs -- RelationnelRelationnel

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Introduction to VHDLIntroduction to VHDL

VHDL OperatorsVHDL Operators -- RelationalRelational

111 > 1011

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Introduction to VHDLIntroduction to VHDL

VHDL OperatorsVHDL Operators -- ArithmeticArithmetic

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Dclarations squentielle en VHDL

Processes

If-then-else

Case

Introduction to VHDLIntroduction to VHDL

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Back to the ProcessBack to the Process

Introduction to VHDLIntroduction to VHDL

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Introduction to VHDLIntroduction to VHDL

DclarationDclaration IFIF--ELSIFELSIF

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The order in which statements are written in theIF-ELSIF structure is very important

More than one of the conditions may be true

The first true condition causes its set ofstatements to be executed

Introduction to VHDLIntroduction to VHDL

The IFThe IF--ELSIF StatementELSIF Statement

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Introduction to VHDLIntroduction to VHDL

The IFThe IF--ELSIF ExampleELSIF Example

dd

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The CASEStatement

Introduction to VHDLIntroduction to VHDL

I d VHDLI d VHDL

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Introduction to VHDLIntroduction to VHDL

The CASE StatementThe CASE Statement

I d i VHDLI d i VHDL

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The FOR Loop

Introduction to VHDLIntroduction to VHDL

I t d ti t VHDLI t d ti t VHDL

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ConfigurationsConfigurations

Introduction to VHDLIntroduction to VHDL

Theory behind the configurationTheory behind the configuration

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I t d ti t VHDLI t d ti t VHDL

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ConfigurationsConfigurations

Introduction to VHDLIntroduction to VHDL

ENTITY mux2to1 ISPORT( d0, d1, s :IN STD_LOGIC;

f :OUTSTD_LOGIC);END mux2to1;

ARCHITECTURE behavior OF mux2to1 IS

BEGIN

WITH s SELECT

f

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THE COMPLETE IDEA

Introduction to VHDLIntroduction to VHDL

A complete design hierarchy is defined by multiple entities, which have atA complete design hierarchy is defined by multiple entities, which have at

least one architectureleast one architecture

Introduction to VHDLIntroduction to VHDL

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THE COMPLETE IDEATHE COMPLETE IDEA

Introduction to VHDLIntroduction to VHDL

Each of these entities and architectures will reference standards and typesEach of these entities and architectures will reference standards and types

from within a stated libraryfrom within a stated library

Introduction to VHDLIntroduction to VHDL

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THE COMPLETE IDEATHE COMPLETE IDEA

Introduction to VHDLIntroduction to VHDL

Many of these entities and architectures will reference one or moreMany of these entities and architectures will reference one or more

packages of common definitionspackages of common definitions

Introduction to VHDLIntroduction to VHDL

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THE COMPLETE IDEATHE COMPLETE IDEA

Introduction to VHDLIntroduction to VHDL

The link between each level of hierarchy, and the specification as to whichThe link between each level of hierarchy, and the specification as to which

architecture will be used is provided by the configurationarchitecture will be used is provided by the configuration

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A package contains a collection of definitions thatmay be referenced by many designs at the same time

Usage is similar to that of a component

Separate design file that exists outside of the otherdesign units seen thus far, such as entities and

architectures

Introduction to VHDLIntroduction to VHDL

Packages

Introduction to VHDLIntroduction to VHDL

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User DefinedTypes

Types can also be defined by the user

A user defined type is known as an enumerated

type

Types are most commonly defined inside a package,architecture, or process

Most synthesis tools are able to synthesize VHDLcontaining enumerated types

Introduction to VHDLIntroduction to VHDL

Introduction to VHDLIntroduction to VHDL

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Syntax for declaring a user defined type

Introduction to VHDLIntroduction to VHDL

User DefinedTypesUser DefinedTypes

Introduction to VHDLIntroduction to VHDL

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Having defined a type, signals can be

defined of that type SIGNAL state cannot be assigned anything

which is not of type my_state

Introduction to VHDLIntroduction to VHDL

User DefinedTypesUser DefinedTypes

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Synthesis tools build logic from a signal which is of anenumerated type Usually the minimum number of bits required to

represent the number of possible values

Introduction to VHDLIntroduction to VHDL

User DefinedTypesUser DefinedTypes