iii-v nanoelectronics for energy efficient...

III-V Nanoelectronics for Energy Efficient Information Processing

PhD Students: Vinay Saripalli (Intel), Dheeraj Mohata, Bijesh R., Mike Barth, Ashkar Ali

Suman Datta

Electrical Engineering Materials Research Institute (MRI)

March 01, 2012

Energy Efficiency

• Near threshold voltage (NTV) computing achieves highest energy efficiency

• Can III-V nanoelectronics be employed to enhance transistor characteristics targeted for NTV computing Variable precision floating point unit processor

on 32nm CMOS (Source Intel: ISSCC 2012)

Emerging Nano Devices

• Leverage emerging Nano devices for advanced, extended and beyond CMOS for energy efficiency

Ge / InGaAs / InSb FINFETs

Enhanced CMOS

Extended CMOS

Beyond CMOS

State of the Art CMOS

NTV Computing Devices

1E12 1E13101

102

103

Si PMOS

Hole

Mob

ility

[cm

2 /Vs]

Carrier Density [/cm2]

Ga0.6In0.4Sb QW Layers

7x

Stanford, NRL (IEDM '09)

1E12 1E13101

102

103

104

105

Si NMOS

Elec

tron

Mob

ility

[cm

2 /Vs]

Carrier Density [/cm2]

InAs1-xSbx QW Layers

60x

Penn State, NRL (IEDM '10)x=0.2-0.3

Antimonide III-V CMOS

InAs1-xSbx QW electron mobility ~ 13,000 cm2/Vs (60x over Si)

GaxIn1-xSb QW hole mobility ~ 850 cm2/Vs (7x over Si)

Promising for low power, high-performance III-V CMOS logic

InGaSb QW

S.I. GaAs Nucleation and Buffer Layer

Al0.8Ga0.2Sb buffer(Unified Buffer for NMOS and PMOS)

InAsSb QW

High-κ

GS D

NMOS

High-κ

GS D

PMOS

Isol

atio

nInAlSb Barrier InAlSb Barrier

InAlSb Barrier InAlSb Barrier

4o(100) Offcut Si Substrate

ILD

Shared Metamorphic Buffer

M. Hudait, S. Datta, R. Chau et al.; US Patent No. 7429747

Antimonide NMOS and PMOS have similar lattice constants

Can be grown on the same buffer Promising for III-V CMOS

Outline

• Device Layer Design

• Dielectric Integration Strategy

• Device Transport Characterization

– Long Channel Mobility

– Short Channel Velocity

• Gate Stack Scalability

– Quantum Capacitance Effects

• Conclusions Substrate

Mismatch Accommodation Layer

High Mobility QW

Bottom Barrier Layer

δ-doped Barrier

Wor

k Fu

nctio

n En

gine

ered

S/D

M

etal

High-k gate oxide

Work Function Engineered Gate Metal

Wor

k Fu

nctio

n En

gine

ered

S/D

M

etal

Device Architecture

for Ultra-low VDD Logic

Quantum Well Device Layer Design

InAs0.8Sb0.2 quantum well device layer was modified to incorporate an ultra-thin GaSb cap layer for dielectric integration

Any parallel channel in the device ?

GaSb Cap: 2.5 nm

Al0.8In0.2Sb Barrier: 9 nm

InAs0.8Sb0.2 Channel: 12 nm

Al0.8Ga.2Sb Buffer 5nm

Al0.8Ga.2Sb Buffer

GaAs Substrate

QW Device Layers

1.5 µm

Device layers grown by Brian R. Bennett, NRL

Quantitative Mobility Spectrum Analysis

Higher conductivity peak corresponds to InAs0.8Sb0.2 QW

No dominant parasitic channel in the device layers

10 20 30 40-0.8

-0.4

0.0

0.4

0.8

EFE1

Al0.

8In 0

.2SbGaS

b

Ener

gy [e

V]

Distance [nm]

Al0.

8In 0

.2Sb InAs

0.8S

b 0.2

Al0.

8Ga 0

.2Sb

Te δ−doping

E0

0.3eV

(a)

10-6

10-4

10-2

10-6

10-4

10-2

102 103 104 105 10610-6

10-4

10-2

electrons holes

300K2DEG

2DEG

2DEG 200K

Cond

uctiv

ity [/Ω

]

77K

Mobility [cm2/Vs]

Hall Mobility and Scattering Analysis

10 100

104

105

106

µInterface Charge

µModel µExperiment

µPOPµADP

µInterface Roughness

µRemote Ionized Impurity

µAlloy

Mob

ility

[cm

2 /Vs]

Temperature [K]

Electron mobility of 13,000 cm2/Vs at 300K (Ns=2.2 x 1012 /cm2)

Coulomb scattering due to interface charge limits transport

Interf

ace Cha

rge

Polar

Optical

Phon

on

Remote

Ioniz

ed Im

purity

Acou

stic P

hono

n

Alloy

Disorde

r

Interf

ace Rou

ghne

ss0

10

20

30

40

50

% C

ontri

butio

n to

1/µ T=300K

Ultra-thin GaSb Cap Layer on InAlSb Barrier Enables High-κ Dielectric Integration

High Al content barrier oxidizes in air giving rise to surface pitting during surface preparation prior to high-κ deposition

GaSb cap layer on InAlSb barrier enables high-κ dielectric integration

Surface clean on device layers with InAlSb surface

Surface clean on device layers with GaSb cap on InAlSb barrier

300 nm

0.40.60.81.01.2 75kHz to 2MHz

300K

Capa

cita

nce

[µFc

m-2]

300K

-2 -1 0 1 20.40.60.81.01.2

250K

Gate Voltage [V]( )

-2 -1 0 1 2

250K

n-GaSb MOSCAPs

Gate (Pd/Au)

n-GaSb (Te doping)

ND=1x1018 /cm3

5nm Al2O3

Low Temp Plasma Enhanced ALD

Plasma Enhanced ALD MOSCAPs show good Fermi level modulation

High Temp ALD

p-GaSb MOSCAPs

0.40.60.81.01.2 75kHz to 2MHz

300K

Capa

cita

nce

[µFc

m-2]

300K

-2 -1 0 1 20.40.60.81.01.2

200K

Gate Voltage [V]-2 -1 0 1 2

200K

Gate (Pd/Au)

p-GaSb (unintentional doping)

NA=1x1018 /cm3

5nm Al2O3

High Temp ALD Low Temp Plasma Enhanced ALD

Plasma Enhanced ALD MOSCAPs show good Fermi level modulation

0.0 0.2 0.4 0.6 0.81012

1013

D it [/c

m2 /e

V]

E-EV [eV]

Interface State Density (Dit)

High Temp ALD

Low Temp PEALD

Dit extracted from multi-temperature CV/GV analysis of n&p GaSb MOSCAPs

Low Dit near EV of GaSb for PEALD Good Sb QW NMOS turn off

High Dit towards midgap Likely affect drive current

Fermi Level movement at high-κ/GaSb interface for Sb QW MOSFET ON-OFF

10 20 30-1.0

-0.5

0.0

0.5

1.0

GaSb

Oxid

e

E2

E1

BufferQW Barrier

EF

EV

Ener

gy [e

V]

Distance [nm]

EC

Sb QW MOSFET ON-State

10 20 30-0.5

0.0

0.5

1.0

1.5

GaSb

Oxid

e

E2

E1

BufferQW Barrier

EF

EV

Ener

gy [e

V]

Distance [nm]

EC

Sb QW MOSFET OFF-State

-1 0 10.51.01.52.02.53.0

Capa

cita

nce

[µF/

cm2 ]

75 kHz to 2MHz

-1 0 1

Gate Voltage [V]

Pd / (5 nm HfO2-1 nm Al2O3) / p & n-GaSb

Scaled Gate Stack Low Temperature ALD

0.0 0.2 0.4 0.6 0.81012

1013

ALD Al2O3/HfO2

TOXE=1.4 nm

EV EC

E-EV [eV]D it [

/cm

2 /eV]

PEALD Al2O3

TOXE=3.1 nm

Al2O3 / HfO2 bilayer stack enables gate dielectric scaling

1nm Al2O3/10nm HfO2

S.I. GaAs Substrate

Al0.8Ga0.2Sb Buffer : 1.5μm

InAs0.8Sb0.2 QW:12nm

GaSb : 1 nmAl0.8In0.2Sb Barrier : 9nmTe δ-doping

Pd/P

t/Au

D

rain

Pd/P

t/Au

So

urce

1nm Al2O3/10nm HfO2

S.I. GaAs Substrate




Pd/P

t/Au

D

rain

Pd/P

t/Au

So

urce

Pd/Au Gate

Sb NMOSFET Device Fabrication As Grown Device Layers

S.I. GaAs Substrate



GaSb : 2.5nmAl0.8In0.2Sb Barrier : 9nmTe δ-doping

S.I. GaAs Substrate



GaSb : 2.5nmAl0.8In0.2Sb Barrier : 9nmTe δ-doping

Pd/P

t/Au

D

rain

Pd/P

t/Au

So

urce

Pd/Pt/Au Source-Drain Contacts

and Device Isolation

Gate Stack Processing (HCl based surface clean)

Gate Patterning E-beam Lithography

Final Processed Device

1nm Al2O3/10nm HfO2

S.I. GaAs Substrate




Pd/P

t/Au

D

rain

Pd/P

t/Au

So

urce

Pd/Au Gate

SEM Micrograph of Sb NMOSFET

Long and short channel Sb NMOSFETs fabricated with composite high-κ gate stack(1 nm Al2O3 / 10 nm HfO2 on GaSb)

Gates defined using electron beam lithography LG = 150 nm–20 µm

Pd/Au Gate LG= 150 nm

Devices Fabricated at the Penn State Nanofabrication Facility

-2 -1 010-1

100

101

102

Gm a

t VDS

=0.5

V [µ

S/µm

]

VDS=0.1V,0.5VLG=5µm

I D & I G

[µA/µm

]

Gate Voltage [V]0

100

200

-2 -1 0100

101

102

I D &

I G [µ

A/µm

]

VDS=0.1V,0.5VLG=450 nm

Gate Voltage [V]0

200

400

600

Gm a

t VDS

=0.5

V [µ

S/µm

]

-2 -1 0100

101

102

VDS=0.1V,0.5VLG=150nm

Gate Voltage [V]0

200

400

600

Gm a

t VDS

=0.5

V [µ

S/µm

]

I D & I G

[µA/µm

]

Transfer Characteristics of Sb NMOS

Good ION-IOFF for long LG devices

Gm,peak= 400 µS/µm at VDS=0.5V for LG= 450 nm (Rext limits short channel performance)

The sub-threshold characteristics degrade as LG is scaled due to non-optimized barrier and oxide thickness (TOXE=4.6 nm)

o Need to scale the barrier, oxide and quantum well thickness

0.0 0.5 1.00100200300400500600 VGS Start=0.5V

Step=-0.25VLG=150nm

I D[µ

A/µ

m]

Drain Voltage [V]0.0 0.5 1.00

100200300400500

I D[µ

A/µ

m]

VGS Start=0.5VStep=-0.25VLG=450nm

Drain Voltage [V]0.0 0.5 1.00

50

100

150

200 VGS Start=0.5VStep=-0.25VLG=5µm

I D[µ

A/µ

m]

Drain Voltage [V]

Output Characteristics of Sb NMOS

Excellent saturation (at low VG) in the output characteristics for long LG device

IDSAT of 450 µA/µm at 0.75 V VDS for 150 nm LG device

Short channel ION limited by contact resistance

Long Channel Transport

Record high electron drift mobility of 6,000 cm2/Vs at 2x1012 /cm2 of Ns

Drift mobility lower than measured Hall mobility of QW layers by 2.2x

o Measured C-V overestimates the charge density due to Dit

o Scattering from high-κ phonons or surface charge at oxide interface

1011 1012

103

104

In0.53Ga0.47As MOSFET

InAsSbQW MOSFET

Drift

Mob

ility

[cm

2 /Vs]

Carrier Density [/cm-2]

Hall MobilityAs Grown

Si/SiO2

S. Takagi, IEDM 2011

15x 3x

Long Channel Transport

Stretch-out in measured C-V compared to simulated C-V is due to Dit

~20% enhancement in mobility at ns=2x1012 /cm2 after correcting the sheet charge density for trapped charge

Pulsed I-V measurements will reduce charge trapping in the Dit

-1.5 -1.0 -0.5 0.00.0

0.2

0.4

0.6

0.8

Capa

citan

ce [µ

F/cm

2 ]

Gate Voltage [V]

Measured Simulated

LG=20µmFreq.=2MHz

1011 1012

4000

6000

8000100001200014000 Hall Mobility

As Grown

Corrected for Dit

Extracted usingMeasured C-V

Dr

ift M

obili

ty [c

m2 /V

s]Carrier Density [/cm-2]

-2 -1 0100

101

102

VDS=0.1V,0.75VLG=450 nm

I D [µ

A/µ

m]

Gate Voltage [V]

, DC, Pulsed

(2µs)

0.0 0.5 1.00100200300400500

15%

35%

VG-VT=1.25V

VG-VT=0.75V

Closed - Pulsed (2µs)Open - DC

I D[µA

/µm

]

Drain Voltage [V]

VG-VT=0.25V31%

LG=450nm

Pulsed I-V

Expected time constant for trapping / de-trapping ~ 0.5 - 1µs

Pulsed I-V characteristics shows significant enhancement in ION and ION/IOFF over DC due to reduced charge trapping from Dit

o~35% ION enhancement at 0.75 V gate overdrive

τ = Rtunnel x Cit τ ~ 0.5 – 2 µs

Gate

VG VD VS

ID Oxide GaSb

Barrier Channel Barrier

JG

Peak extrinsic RF gm improves by 30% compared to DC Gm

RF and Pulsed Measurements

-0.5 0.0 0.5 1.00100200300400500 30% DC

Pulsed (2µs) RF

Ex

trins

ic G m [µ

S/µm

]

VG-VT[V]

LG=450nmVDS=0.75V

221 0 Re[ ]mRF g Y

ω ==

Effective source injection velocity (veff) determines the performance in short channel devices

RF measurements are used to extract charge in short channel devices

Short Channel Device Characterization: Virtual Source Injection Velocity Extraction

A. Khakifirooz et al., TED, 2008 M. Lundstrom, EDL 1997

1 1 1(0 )eff T effv v Eµ += +

2*

BT

k Tvmπ

=

EC

veff ID/W = Qinj x veff

0 L x

VG VD VS

RD RS Qinj

ID

Source

Gate Drain

A simplified MOSFET small signal equivalent circuit was used to model the measured s-parameters of Sb NMOSFET

Excellent fit between measured and modeled data is obtained for all 4 s-parameters obtained till 50 GHz

Short Channel Device Characterization: RF Measurements and S-parameter Modeling

LG = 150 nm, WG=2x33 µm VGS-VT=0.6 V, VDS=0.75 V

0.2 0.5 1.0 2.0 5.0

-0.2j

0.2j

-0.5j

0.5j

-1.0j

1.0j

-2.0j

2.0j

-5.0j

5.0j

Measured Modeled

S112*S22

10*S12

S21

100 MHz to 50 GHz

150 nm LG Sb NMOS at 0.75 V VDS and 0.6 V overdrive demonstrates

o 2.7 x 107 cm/s veff

Highest veff among III-V MOSFETs

0.01 0.1 10

1

2

3

InGaAs NMOSVDS=0.5V [2]

Sb NMOS; VDS=0.75V

Strained Si [1]

v ef

f [x

107 cm

/s]

Gate Length [µm]

Si NMOS [1] VDS = 1.1-1.3V

Short Channel Transport

[1] D. Antoniadis et al., IEDM 2008 [2] M. Radosavljevic et al.; IEDM 2009

1.5x 4x

4x higher than Si NMOS at 1.0-1.2 V VDD

1.5x higher than InGaAs NMOS at 0.5 V VDS

E-Mode Sb NMOS

Scaled device architecture increases the gate field to QW coupling improving device electrostatics

o SS = 150 mV/dec for E-mode for LG=5 µm (350 mV/dec for D-mode)

High access resistance limits the short channel device performance

o Need self-aligned device architecture

-2 -1 0 110-2

10-1

100

101

102

E-Mode150m

V/de

c

VDS=0.05V,0.5VLG=5µm

I D [µA

/µm

]

Gate Voltage [V]

350m

V/de

c

D-Mode

-2 -1 0 110-2

10-1

100

101

102

E-Mode

250m

V/de

c

VDS=0.05V,0.5VLG=150 nm

I D [µA

/µm

]Gate Voltage [V]

700mV/dec

D-Mode

IOFF

VT

veff =2.7 x 107 cm/s for D-Mode , 1.8 x 107 cm/s for D-Mode at VDS=0.75 V

Lower veff for E-Mode devices due to the lower Hall Mobility of as grown samples:

E-Mode : 13000 cm2/Vs at ns=2.2x1012 /cm2 ,

D-Mode : 5,500 cm2/Vs at ns=1.8x1012 /cm2

Short Channel Performance D-Mode vs E-Mode Sb NMOSFETs

0.01 0.1 10

1

2

3

E-Mode

D-Mode

Strained Si [1]

v eff [

x 10

7 cm/s

]

Gate Length [µm]

Si NMOS [1] VDS = 1.1-1.3V [1] D. Antoniadis

et al.,IEDM 2008

Drive Current Expectation from Sb NMOSFET for 0.5V VDD Logic

Assume 5nm Sb Quantum well

ION = q x ns x veff

= (1.6 x 10-19 C ) x (3.5 x 1012 /cm2)x (2.7 x 107 cm/s)

Experimentally demonstrated

Projected based on experiments

= 1.5 mA/µm

ION = ? at VG-VT = 2/3 x VDD ~ 0.3V

Assuming RS as in Si (~ 80 Ω.µm): ION = 960 µA/µm at VG-VT~ 0.3V

Key Challenges: Maintaining veff for very thin channels Obtaining optimum RS at required footprint Acceptable short channel effects

Conclusions

Demonstrated antimonide (Sb) QW MOSFETs with integrated high-k gate dielectric for low VDD logic application

Sb NMOSETs exhibit:

o Electron drift mobility of 6000 cm2/Vs at ns=2 x 1012 /cm2

o Short channel (150nm LG) source injection velocity (veff) of 2.7x107 cm/s

o Extrinsic fT - LG product of 18GHz.um at VDS=0.75 V, VG-VT=0.6 V

Benchmarked Sb NMOSFET figures of merit to standard strained Si NMOS

o 15x higher drift mobility at ns=2x1012 /cm2

o 4x higher veff for VD=0.75 V at comparable LG

o 2x higher fT - LG product

Energy Efficiency Computing Devices

Steep Switching in Tunnel FET

Switching slope in TFETs can be less than kT/q

TFET: SS < kT/q possible

MOSFET: SS >= kT/q

VG

IOFF

IOFF

ID

Gate

Gate

i-channel P++

Source N+

Drain

high-k

high-k

Tb

TOX

EFS EFD

Band-pass filter

Filled States

Empty States

Band-gap EFC

Presenter

Presentation Notes

Tunnel FETs on the other hand donot suffer from this fundamental kT/q limitation. A Tunnel FET switches on and off via band-to-band tunneling and the band-pass filtering action between the source fermi-level and the channel conduction band-edge can potentially result in switching slope less than kT/q. Steep switching can lead to low turn on voltage and this opens opportunity for aggressive supply voltage scaling.

0.0 0.1 0.2 0.3 0.4 0.510-1110-910-710-510-310-1101103

InSb TFET InAs TFET In0.53Ga0.47As TFET Si TFET Si MOSFET

Drai

n Cu

rren

t, I DS

[µA/µm

]

Gate Voltage, VGS [V]

VDS=0.5V

60mV/dec

Low Ion in HomJ TFETs

Silicon

In0.53Ga0.47As

InAs

InSb IOFF ION

Eb

Wb

Both ION and IOFF increase with reducing band-gap

LG=32nm EOT=0.5nm Tb=7nm

Simulations Gate

Gate

i-channel P++

Source N+

Drain

high-k

high-k

Tb

TOX

Simulation

Presenter

Presentation Notes

In this plot we show Id-Vg characteristics for various homj TFETs simulated at drain to source bias of 500mV. Si homj TFET shows switching slope less than kT/q, however corresponding current levels are very low and the drive current is orders in magnitude lower compared to Si MOSFET. Now we need MOSFET like drive currents in order to perform high speed logic. Drive current can be increased by moving to smaller band-gap systems such as InGaAs, InAs and InSb. As we move from InGaAs to InSb, drive current increases and is approaching MOSFET like on current level, which is what we want however on the flip side the off current has now increased dramatically affecting the on/off ratio.

100 101 102 103101103105107109

1011

Si MOSFET

Si TFET

In0.53Ga0.47As TFET

InAs TFET

InSb TFET

ION [µA/µm]

I ON/

I OFF

VCC=0.5V

Can HomJ TFET beat MOSFET?

-None of the HomJ TFETs are superior at higher ION -Need higher ION/IOFF @ MOSFET like ION

Simulations

Presenter

Presentation Notes

In this graph we plot on/off ratio vs on current for different homoj TFETs and compare it with Si MOSFET. It is clear that InSb homj TFET cannot beat Si MOSFET. InAs TFET does show higher ion/ioff , however the current levels are low and un-acceptable for high performance logic . Now the question arises can we do some tunnel junction engineering to the homoj TFET and shift these family of curves to right so that we get higher on/off at a higher drive current.

Tunnel Junction Engineering

with Staggered Hetero-junction

Maximize stagger to get maximum enhancement in ION

HomJ TFET

Eg

Eg Source

channel

))(( 5.1

exp beffET βα −

High Stagger HetJ TFET

∆Ec

Eg

Eg Source

channel

cgbeff EEE ∆−≈

Tunneling Device Architecture

TUD

Ultrathin geometry for robust electrostatics

Drain-Gate underlap to minimize ambi-polar leakage

Gate

Gate

i-channel P++

Source N+

Drain

high-k

high-k

Tb

TOX

LG

Electric Field

Abrupt tunneling junction

Source Channel

λ2 λ1

III-V / high-k interface with low Dit

Source

Channel Source

Channel

Drain

Presenter

Presentation Notes

Proper structural design should complement hetero tunnel junction engineering. Quality III-V high-k interface with low Dit to avoid SS dilution. Utlra-thin device geometry for robust gate control and low parasitic leakage. Drain gate underlap structure to minimize ambipolar conduction and finally abrupt tunnel junction with low source gate overlap to maximize junction electric field.

Vertical Tunnel FET

Mo

i N+

Gate

ILD

Drain

Gate

III-V / high-k interface with low Dit

Pillar based ultrathin Tb

In situ doped Molecular Beam Epitaxially grown

junctions

Drain-Gate underlap structure

Presenter

Presentation Notes

This particular schematic is for a vertical nano-pillar hetj TFET. A vertical device has the advantage of using MBE grown abrupt junctions. Nano-pillar geometry can provide thin body dimensions needed at ultimate device scaling limits.

Vertical Nano-pillar TFET 3. Dry etch Mo and InGaAs

6. ILD and Drain Contact 5. Gate and Source contact 4. ALD high-k after wet etch

2. Cr/Ti hard etch mask 1. Blanket deposit Mo

1nmAl2O3/3.5nmHfO2

Presenter

Presentation Notes

This is the vertical nanopillar TFET process flow that we optimized with InGaAs. TFET layers are grown at IQE using solid source MBE. We blanked deposit Mo and lift-off Cr/Ti etch mask. Mo and InGaAs are then dry etched. Dry etch is followed by wet etch undercut to remove side wall damage, native oxide removal and high–k deposition using ALD technique. This is followed by gate and bottom source contact formation. The device is then planarized with ILD and top contact is formed after ILD etchback until Mo.

39

Tunnel Barrier Engineering

39

Reduce Eg

Mod. Stagger H

igh

Stag

ger

N+

i

P++ In0.53Ga0.47As

Mo high-k

Pt ILD

Au Pd

Ti

Homo-junction and Hetero-junction Tunnel FETs

Cross-section TEM image of the fabricated devices

350nm

450nm

Ti

350nm

Large Eg HomJ High HetJ TFET

Presenter

Presentation Notes

Here we show cross section Transmission electron microscopy images of the fabricated devices on the large Eg homj and high heterojunction TFEt samples.

-0.50 -0.25 0.00 0.25 0.50 0.750102030405060

Drai

n Cu

rren

t, I DS

[ µA/µm

]

Drain Voltage, VDS [V]

Vgs=0V to 2.5Vat steps of 0.5V

-0.50 -0.25 0.00 0.25 0.50 0.750

20

40

60

Drai

n Cu

rren

t, I DS

[µA/µm

]


Vgs=0V to 2.5Vat steps of 0.5V

-0.50 -0.25 0.00 0.25 0.50 0.750

50

100

150

200

Drai

n Cu

rren

t, I DS

[ µA/µm

]Drain Voltage, VDS [V]

Vgs=0V to 2.5V at steps of 0.5V

Measured Id-Vd @ 300K

Mod. Stagger (ION ↑ 2.5x)

With High HetJ TFET, ION increases by 660%

-0.50 -0.25 0.00 0.25 0.50 0.750

5

10

15

20

25

Drai

n Cu

rren

t, I DS

[µA/µm

]


Vgs=0V to 2.5Vsteps of 0.5V

Mod. Stagg. HetJ

Small Eg HomJ

Large Eg HomJ

High Stagg. HetJ

Lg=100nm EOT=1.5nm

Lg=100nm EOT=1.5nm

Lg=150nm EOT=1.5nm Lg=150nm

EOT=1.5nm

Presenter

Presentation Notes

Now I am going to present electrical results on the fabricated devices. The output characteristic are assymetric for each of them and shows Negative differential resistance behavior typical for a TFET. Moving from large Eg homj TFET to the moderate stagger hetj, 150% enhancement in Ion is observed @ vds=0.75V. With further increase in stagger, 660%enhancement is observed for the high hetj TFET confirming that staggered heterojunction engineering can result in significant increase in drive current.

-0.5 0.0 0.5 1.0 1.5 2.0 2.510-410-310-210-1100101102

Drai

n Cu

rren

t, I DS

[ µA/µm

]


Vds=50mV Vds=250mV Vds=500mV

-0.5 0.0 0.5 1.0 1.5 2.0 2.510-610-510-410-310-210-1100101102

Drai

n Cu

rren

t, I DS

[µA/µm

]


VDS=50mVVDS=250mV VDS=500mV

-0.5 0.0 0.5 1.0 1.5 2.010-610-510-410-310-210-1100101102

Drai

n Cu

rren

t, I DS

[µA/µm

]


VDS=500mV VDS=250mV VDS=50mV

-0.5 0.0 0.5 1.0 1.5 2.0 2.510-610-510-410-310-210-1100101102

Drai

n Cu

rren

t, Id

[µA/µm

]

Gate Voltage,VGS [V]

VDS=50mV VDS=250mV VDS=500mV

Measured Id-Vg @ 300K

Experimental IOFF is increasing with stagger

Mod. Stagg. HetJ

Small Eg HomJ

Large Eg HomJ

High Stagg. HetJ

Lg=100nm EOT=1.5nm

Lg=100nm EOT=1.5nm

Lg=150nm EOT=1.5nm

Lg=150nm EOT=1.5nm

Presenter

Presentation Notes

Unfortunatley Ioff also increases with stagger. We do not expect this as we are reducing tunneling barrier locally. The high leakage can be related to the interface issues with growing InGaAs on GaAsSb and is a definite opportunity for further research.

10-8 10-6 10-4 10-2 100 102050

100150200250300350

60mV/dec

SS (m

V/d

ecad

e)Drain Current, IDS [µA/µm]

77K 300K

15.4mV/dec

-0.5 0.0 0.5 1.0 1.5 2.010-1010-810-610-410-2100102

BTBTTAT

T=300K T=77K

Drai

n Cu

rren

t, I DS

[µA/µm

]


VDS=50mV,500mV

SRH

Temperature Dependent Switching Slope (SS)

Measured Id-Vg Switching Slope

-Switching slope improves at low temperature -Quality of high-k/ III-V interface needs investigation

Source

Channel

Presenter

Presentation Notes

Switching slope in the fabricated devices are diluted at room temperature due to the poor quality of the high-k/semiconductor interface and due to traps within the oxide. High Dit near the interface result in gap state assisted tunneling followed by thermionic emission diluting the switching slope. This phenomena however gets significantly suppressed at low temperature, improving the switching slope vs Id characteristics.

-2.0-1.5-1.0-0.50.0 0.5 1.0 1.5 2.00.000.250.500.751.001.251.501.75

f=75kHzDue to Dit

1nmAl2O3/3.5nmHfO2

CET=2.3nm

Cap

acita

nce,

C [µ

F/cm

2 ]


Ideal

n-In0.53Ga0.47As

-Mid-gap states have characteristic response time between 1ms and 1µs -Can we avoid gap state assisted tunneling using pulsed I-V?

High-k/Channel Interface Quality

Measured

Presenter

Presentation Notes

We performed CV measurements on n-InGaAs MOSCAPs to characterize the high-k/III-V interface quality. The Al2O3/InGaAs interface shows higher capacitance within the depletion region compared to the ideal CV signifying large presence of mid-gap Dit. The characteristics response time corresponding to a distribution of Dit about the mid-gap lies between 1ms and 1us as shown by the window. IF the switching slope is really diluted by trap assisted tunneling, ultra fast pulsing should be able to prevent a majoiroity of their response.

0.0 0.5 1.0 1.510-8

10-7

10-6

10-5

10-4 Simulations DC pulsed (tr=600ns) pulsed (tr=200ns)

VDS=300mVDrai

n Cu

rren

t [A]

VGS-VON [V]

Vcc

+

- D

S

G

50Ω

To Oscilloscope

Switching slope improves with ramp rate and appears approaching ideal swing

R1

Gain=100,000

***Pulsed IV measurements conducted at NIST (John Suehle)

Can we improve SS using Ultrafast Pulsed I-V Technique?

tr

Presenter

Presentation Notes

We pulsed our devices at sub-microsec rise times using the simplified pulsed IV circuit on the left. The drain current was sampled at the leading edge of the drain current vs time curve. Figure on the right compares pulsed IV curves for rise times of 200 and 600ns and compared with DC measurements and the ideal expected curve. The trend looks promising as the swing is improving with faster and faster pulse speeds, confirming the concept that Trap assisted tunneling followed by thermionic emission really dilutes the SS.

10-9 10-8 10-7 10-6 10-50

50100150200250300

Simulations DC Pulsed (tr=600ns) Pulsed (tr=200ns)

SS [m

v/de

c]Drain Current [A]

60mV/dec

VDS=0.3V

Can We Improve SS using Ultrafast Pulsed I-V Technique?

Point switching slope approaches kT/q @ 300K

***Pulsed IV measurements conducted at NIST (John Suehle)

Vcc

+

- D

S

G

50Ω

To Oscilloscope

R1

Gain=100,000

tr

0.3 0.4 0.5 0.6 0.7100

101

102

103

High HetJ

Small Eg HomJ

Mod. Stagg. Hetj

Drai

n Cu

rren

t, I DS

[µA/µm

]


Strained Si MOSFET (VT=0.2V)

Large Eg Homj

Tunnel FET vs MOSFET

For Vcc less than 300mV, BTBT can potentially deliver MOSFET like on current

Experimental (EOT=1.5nm, Tb=200nm)

0.5 1.0 1.5 2.010-210-1100101102103

Large Eg HomJ Small Eg HomJ Mod. HetJ High HetJ

Measured Simulations

Drai

n Cu

rren

t, I DS

[µA/µm

]

VGS-VON [V]

VDS=0.5V

EOT=1.5nmTP=200nm

Modeling Measured Id-Vg

Junction Ebeff (eV)

mR (mO)

In0.53Ga0.47As (Large Eg homJ)

0.74 0.023

In0.7Ga0.3As (Small Eg homJ)

0.59 0.019

GaAs0.5Sb0.5/In0.53Ga0.47As (Moderate stagger hetJ)

0.5 0.025

GaAs0.35Sb0.65/In0.7Ga0.3As (High stagger hetJ)

0.25 0.022

-Further geometry scaling required in order to reduce Vcc

Projection

Need for Extremely Staggered / Nearly Broken InAs/GaAs0.1Sb0.9 tunnel junction to replace MOSFET @ Vcc=300mV

100 101 102 103100

102

104

106

Strained SiMOSFET

Large Eg Nearlybroken

I ON

/I OFF

ION [µA/µm]

VCC=0.3V

High HetJ

Simulations (EOT=0.5nm, Tb=7nm, LG=32nm)

101 102 103100

102

104

106

108

VCC=0.5V

I ON/

I OFF

ION [µA/µm]

Large EgNearlybrokenHigh HetJ

Strained SiMOSFET

Si

New

Mat

eria

ls

Electrostatics

Planar Tri-Gate Gate-All-Around

Motivation

SiGe

1D strained QW nanowire

New opportunity: 0D QD

III-V

Vout(mV)

Vin(mV)

300

0 300

sub 500mV CMOS Logic

Vg(V)

0 0.1 0.2 0

10

Id (nA)

sub 250mV BDD Logic

Presenter

Presentation Notes

In the transistor scaling trend, new materials such as SiGe III-V are used to enhance channel mobility. Better electrostatic is achieved by changing the device structure from planar to tri gate and gate all around. As a natural result of these two scaling trend, the quantum confinement of channel electrons go from 2D to 1D and ultimately 0D QD. In this talk, we will focus on a 1D transistor in high mobility III-V stainted QW system, as well as possible 0D QD transistor using weak coupling between s/d and channel. Also we need to explore low power circuit desgin using the feather of these transistors in the ultra confined systems.

Classical III-V MuQFET Fabrication

QW epitaxy Fin definition and etching (BCl3/Ar)

S/D contact (Au/Ge/Ni)

High-K deposition (1nm Al2O3+3.5nmHfO2)

Metal gate stack (Au/Pd)

S/D Contact Opening

QW

Presenter

Presentation Notes

To fabricate the 1D classical MuQFET, we start from the Molecule beam epitaxial wafer. The fins are defined by ebeeam lithography and etched by Bcl3/Ar plasma. Au/Ge/Ni are deposited on S/D and make alloy contact to QW after annealing. Composite High-K and Au/Pd are used for gate stack. S/D contacts are opened by Cl2 plasma thru oxide.

52

Fabrication of MuQFETs

• 40 nm wide electron waveguides fabricated using top-down pattern and etch process • Split Gate architecture allows going from classical FET mode to Coulomb Blockade

mode

InP 2 nm

In0.52Al0.48As 2nm

In0.53Ga0.47As 14nm

In0.52Al0.48As 2nm

δ-doping 2E12 cm-2

InAlAs virtual substrate

L. Lu, V. Saripalli, V. Narayanan S. Datta, IEDM, Dec 2011

Gate

Classical III-V MuQFET Characterization

• SS is improved to 120mV/decade with scaling fin width to 10nm.

WFIN decreases

WFIN =10nm WFIN =40nm WFIN =100nm WFIN =500nm

WFIN decreases

WFIN =10nm WFIN =40nm WFIN =100nm WFIN =500nm

Presenter

Presentation Notes

the transfer charaterization gives a postively shifted Vt when the fin width becomes smaller. this is a good trend implying enhancement mode MuQFEt is possible by engineering the fin width. Also short channel effect is improved for smaller fin width, SS is improved to 120mV/dec for W=10nm. Change it to wfin, use capitacl and subscript for Vt whatever

54

Ballistic Mean Free Path

Mob

ility

(cm

2 /V-

sec)

Room temperature mean free path ~ 120 nm extracted for the fabricated structures

Gate length dependence of extracted mobility reflects quasi-ballistic transport

Sheet charge density NS (cm-2)

300K 300K

Non-Classical (NC) MuQFET

SG 80nm

40nm

• The split gate (SG) bias determines the strength of coupling between S/D contact and channel.

• Top control gate (CG) controlling the channel potential may result in coulomb oscillation.

CG SG

source

Drain

Control gate (CG)

CG Split Gate (SG) High-K

Presenter

Presentation Notes

Unlike the classical MuQFET, two split gate with a narrow separation was patterned instead of one single wrap gate. The SG bias determine the coupling strength between S/D fermi sea and channel. When the coupling is weak, top control gate modulate the channel potential, which arises coulomb oscillation.

Beyond CMOS

With VDD approaching 4kBT (~100mV), the CMOS inverter gain drops In BDD logic, path switching function and passive transmission of

messenger do not require devices with “transfer gain” and “current drivability”

Need to program tree with open, short paths and actual decision nodes

Binary Decision Diagram (BDD) Logic CMOS Logic

open

short

Beyond CMOS

• ASSIST will explore reconfigurable Single Electron Transistor device architecture and implement low voltage combinational logic circuits with such elements

Reconfigurable SET

Demonstrated reconfigurable, split gate single electron transistor (SET) exhibiting open, short and Coulomb Blockade mode of operation

Source: L. Lu, V. Narayanan, S. Datta IEDM, Dec 2011 Supported by NSF

Summary

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.00.81.01.21.41.61.82.02.22.4

Tran

sisto

r Gat

e Dela

y (n

orm

alize

d)

Operating Voltage (V)

Planar Si MOSFET Silicon MuGFET InGaAs MuQFET III-V TFET SET

0.1 1 Switching Energy [x10-16 J]

• III-V nanoelectronics provides a promising landscape for energy efficient information processing, but needs serious $$ investment

0.01 x10-16 J

Si Planar (32nm)

Si MuGFET (14/22nm)

III-V MuGFET

III-V Tunnel FET

III-V SET

60

New Nano Facility at Penn State

www.mri.psu.edu/facilities/Nanofab

Device Research Conference, DRC 2012 June 18-20 ; Abstract Submission Deadline: March 07, 2012

61

Datta Research Group

www.mri.psu.edu/facilities/Nanofab

iii-v nanoelectronics for energy efficient...

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