how to design programs using vhdl

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HOW TO DESIGN PROGRAM USING VHDL

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What is VHDL?

VHDL stands for

VHSIC (Very High Speed Integrated Circuits) Hardware Description Language.

How To Design Using VHDL


What is VLSI?

VLSI stands for "Very Large Scale Integration"

It is the process of integrating millions of transistors on tiny silicon chips to perform a multitude of logic operations.

Now a days all the handy and electronic instruments are ASIC / PLD’s based.

Have u ever used an ASIC or a PLD’s ????



IMPORTANCE OF VLSI

Integrating millions of transistors on a single Silicon Chip – reducing area and cost of silicon

Very less time to Market for product

Efficient integration of several designs

Testing functionality much before the actual fabrication of the chip

Design reuse

System on chip



The world of VLSI

VLSI family

- PLD’s

- ASIC’s EDA Tools have changed the VLSI Design

scenario.



IC TECHNOLOGY….. Development phases

TYPE GATES YEAR FUNCTIONS

SSI 1-100 1960 Gates, OpAmpsMSI 100-1K 1965 FiltersLSI 1K-10K 1970 Ps, A/DVLSI 10K-2M 1975 Mem.,DSP



IC Size

Is measured in terms of the no. of logic gates and transistors.

Gate implies a 2-i/p NAND gate i.e. 100K-gate IC contains 100,000 2-i/p NAND gates.

4-CMOS Transistors in a 2-i/p NAND gate.

To convert gates to transistors, multiply gates by 4 to obtain number of transistors.



Power,Clock Frequencies & Voltage

Power Consumption, Clock frequency, Supply Voltage are related as follows:-

P = FCV

where, C = Capacitance V = Supply voltage F = Clock frequency



Moore’s Law

In 1969, Gorden Moore (of Intel technologies)stated that Silicon Technology will double the number of transistors per chip every 18 months.

The recent developments have proved that Moore's law has become self sustaining.



Feature Size

The term “micron technology” speaks about the Feature size of a chip

Is given by the width of the smallest transistor. Deep Sub micron technology has arrived - 0.5u, 0.35u, 0.25u,

0.18u….



DESIGN FLOW



DESIGN ENTRY



DESIGN ENTRY

Schematic entry



DESIGN ENTRY

STATE MACHINE ENTRY


S1 S3

S2

S4

S5S6

Reset

T=1

T=1

T=0

S=1

S=1

T=1

G=1

s=1

T=2


HDL coding

library ieee;

use ieee.std_logic_1164.all;

entity adder is

port (a, b, cin :in std_logic;

sum, cout :out std_logic);

end adder;

architecture behave of adder is

begin

sum <= (a xor b) xor cin;

cout <= (a and b) or (a and cin) or (b and cin);

end behave;



Simulation

It uses software model to replicate Design performance in terms of Timing and Result.

Functional simulation eliminates the time-consuming need for constant physical prototyping.

Simulation is the process of applying stimuli to a model over time and producing the corresponding responses from the model.

Types Functional Simulation. Static Timing Analysis. Gate Level Simulation. Post Layout Simulation.

I.e. Back Annotation.



Simulation

Purpose:

Analyze a Design/Test bench for Correct Syntax

Elaborate the Design for Integrity

Run the Test bench and

Observe that the HDL Design Behaves as Expected



Synthesis

Synthesis is the process of creating a representation of a system at a lower level of design abstraction from a higher level (more abstract) representation.

The synthesized representation should have the same function as the higher level representation.

Optimization –Area and Timing.

Mapping

Synthesis results are Target Technology dependent.



Synthesis


Synthesis

Tool

TechnologyLibrary

HDL Code

Constraint

Netlist (Schematic)


Implementation

Is the process of, Placing the design to the specified Target

Technology.

Optimizing the usage of logic cells and Interconnects.

Routing



BASIC FEATURES OF VHDL

1. CONCURRENCY.

2. SUPPORTS SEQUENTIAL STATEMENTS.

3. CAN PRODUCE NET-LIST.

4. SUPPORTS FOR TEST & SIMULATION.

5. STRONGLY TYPED LANGUAGE.

6. SUPPORTS HIERARCHIES

7. SUPPORTS FOR VENDOR DEFINEED LIBRARIES.

8. SUPPORTS MULTIVALUED LOGIC



1.CONCURRENCY

VHDL is a concurrent language.

HDL differs with Software languages with respect to Concurrency only.

VHDL executes statements at the same time in parallel,as in Hardware.



1.CONCURRENCY (contd)

B<=A+E;

A<=C+D;

D A

C B

E


+ +


2.SUPPORTS SEQUENTIAL STATEMENTS

VHDL supports sequential statements also, it executes one statement at a time in sequence only.

As the case with any conventional languages. E.g. if a=‘1’ then

y<=‘0’;

else

y<=‘1’;

end if;



3.CAN PRODUCE NET-LIST

VHDL produces the file which gives the format of inter connection of different gates and components of the higher level design. This format is known as Net-list.

It gives you different industry std format.

Ex.EDIF (Electronic Design Interchange Format).



4.SUPPORTS FOR TEST & SIMULATION.

To ensure that design is correct as per the specifications, the designer has to write another program known as “TEST BENCH”.

It generates a set of test vectors and sends them to the design under test(DUT).

Also gives the responses made by the DUT against a specifications for correct results to ensure the functionality.



5.STRONGLY TYPED LANGUAGE VHDL allows LHS & RHS operators of same type.

Different types in LHS & RHS is illegal in VHDL.

Allows different type assignment by conversion.



5.STRONGLY TYPEDLANGUAGE(contd.).

Examples--

A :in std_logic_vector(3 downto 0).

B : out std_logic_vector(3 downto 0).

C : in bit_vector(3 downto 0).

D : in std_logic_vector(2 downto 0).

B <= A; --perfect.

B <= C; --type miss match,syntax error.

B <= D; --size mismatch ( syntax error ).



6.SUPPORTS HIRERCHIES

Hierarchy can be represented using VHDL.

Consider example of a Full-adder which is the top-level module, being composed of three lower level modules I.e. Half-Adder and OR gate.



6.SUPPORTS HIRERCHIES(contd.)



HISTORY OF VHDL

In 1981 the Institute for Defense Analysis (IDA) arranged a workshop to study various Hardware Description Methods needs for a standard language Features required by such a standard.

A group of three companies, IBM, Texas Instruments and Intermatrics were awarded contract by American Department of Development (DoD) to develop a language and the first version was released.



HISTORY OF VHDL(contd.)

Next Version of VHDL was released along with language Reference Manual (LRM) in 1985.

Standardized by IEEE in 1987 as IEEE Std 1076-1987.

Again the revised version was Standardized by IEEE in 1993 as IEEE Std 1076-1993.



DIFFERENT DESIGN UNIT OF VHDL

1.ENTITY.

2.ARCHITECTURE.

3.CONFIGURATION.

4.PACKAGE.

5.LIBRARY.



LEVELS OF ABSTRACTION

Gate level.

Data Flow level.

Behavioral level.



VHDL Identifiers

Identifiers are used to name items in a VHDL model.

A basic identifier may contain only capital ‘A’-’Z’

‘a’-’z’

‘0’-’9’

underscore character ‘_’

Must start with a alphabet.

May not end with a underscore character.

Must not include two successive underscore characters.

Reserved word cannot be used as identifiers.

VHDL is not case sensitive.



Objects

There are three basic object types in VHDL

Signal -represents interconnections that connect components and ports.

Variable -used for local storage within a process. Constant -a fixed value.

The object type could be a scalar or an array.



Objects( contd… )Signals Syntax:

signal signal_name : type := initial_value;

Equivalent to wires. Connect design entities together and

communicate changes in values within a design.

Each signal has a history of values.

Computed value is assigned to signal after a specified delay called as Delta Delay.



Objects( contd… )Signals

Signals can be declared in an entity (it can be seen by all the architectures), in an architecture (local to the architecture), in a package (globally available to the user of the package) or as a parameter of a subprogram (I.e. function or procedure).

Signals have three properties attached to it.

Type and Type attributes.

value.

Time (It has a history)



Objects( contd… )Signals Signal assignment operator : ‘<=‘.

Signal assignment is concurrent outside a process & sequential within a process.

Sequential (inside process)

count<= count - ‘1’;



Count decrements only once



Objects( contd… )Signals

Concurrent statements are executed when at least one signal in the sensitivity list changes its value (i.e. an event occurs).

Signal updates can have a delay specified in there assignment statements.



Objects( contd… )Variables Are objects with single current values.

Syntax :variable variable_name : type := initial_value;

Can be declared and used inside a process statement or in subprogram.

Variable assignment occurs immediately.



Objects( contd… )Variables

Variables retain their values throughout the entire simulation.

Example :process ( a )

variable a_int : integer := 1;

begina_int := a_int + 1;

end process;

Note : a_int contains the total number of events that occurred on signal a



Objects( contd… )VariablesSequential (inside process)

count:= count - ‘1’;

count:= count - ‘1’;

count:= count - ‘1’;thus count decrement three times.Variable have only type and value attached to it. They don’t have past history unlike signal.

Require less memory & results in fast simulation



Objects( contd… )Constants Constants:

Are identifiers with a fixed value. Should not be assigned any values by the simulation process.

Syntax :constant constant_name : type := value;

Constants improve the clarity and readability of a project.

(It is used in place of the value to make the code more readable)

Example:

constant BusWidth, QueueLength : Integer := 16;

constant CLKPeriod : Time := 15 ns;

constant pi: real := 3.1347592;



Objects( contd… )Alias Alias is an alternative name assigned to part of an object simplifying

its access.

Syntax

alias alias_name : subtype is name;

Examples:

signal inst : std_logic_vector(7 downto 0);

alias opcode : std_logic_vector(3 downto 0) is inst (7 downto 4);

alias srce : std_logic_vector(1 downto 0) is inst (3 downto 2);

alias dest : std_logic_vector(1 downto 0) is inst (1 downto 0);



Data Types And Operators.

Type Is a name which is associated with a set of values and a

set of operations.

Major types: Scalar Types Composite Types



Data types( contd… )Scaler types

Std_logic_type Is a data type defined in the std_logic_1164 package of IEEE library. Is an enumerated type and is defined as type std_logic is (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’,’-’)

‘u’ unspecified

‘x’ unknown

‘0’ strong zero

‘1’ strong one

‘z’ high impedance

‘w’ weak unknown

‘l’ weak zero

‘h’ weak one

‘-’ don’t care



Data types( contd… )Scaler typesScalar Types:

Integer Example:-4e-2,16#3ed2#e+2 Type integer is range implementation_defined

Constant loop_no : integer := 345;

Signal my_int : integer range 0 to 255; Maximum range of integer is tool dependent (typ 32bit) I.e. –2147483648 to 2147483647

Floating point Example:3.23, -3.23, 16#1.23ed#e-2 Can be either positive or negative. exponents have to be integer. Type real is range implementation_defined

Constant loop_no : real := 16#1.23ed#e-2;




Physical Predefined type “Time” used to specify delays. Example:

type TIME is range -2147483647 to 2147483647 units

fs; (femto seconds) --(base unit)

ps = 1000 fs;

ns = 1000 ps;

us = 1000 ns;

end units; Other types are current, distance etc.




Enumeration

Example: type alu is ( pass, add, subtract, multiply, divide )

Values are defined in ascending order.



Data types( contd… )Composite type

There are two composite types

a) Array :Contain many elements of the same type.

b) Records :Contain elements of different types.

Array-- Array can be either single or multidimensional. Single dimensional array are synthesizable. The synthesis of multidimensional array depends upon the synthesizer

being used.

For synthesizers which do not accept multidimensional arrays, we can define two one dimensional arrays.



Data types( contd… )Composite type

Examples : signal A: std_logic_vector(7 downto 0) := “01010111” ;

signal B: std_logic_vector(0 to 3) := “1010” ; signal C : std_logic_vector (6 downto 0);

Assignment to the Arrays : A<= (‘1’,’0’, others => ‘0’); -- aggregation A<= (‘1’,’0’,’1’,’0’,’1’,’0’,’0’,’1’); A<= c(5 downto 2) & B ; --concatenation A(2 downto 1) <= c(6 downto 5); -- slicing



Signal Array(contd…)

A set of signals may also be declared as a signal array which is a concatenated set of signals.

This is done by defining the signal of type bit_vector or std_logic_vector.

bit_vector and std_logic_vector are types defined in

the ieee.std_logic_1164 package.




Signal array is declared as<type>(<range>)

--e.g: bit_vector(1 downto 0)

The range specifies the number of signals in the array and the order of the counting of the signals. --examples:

signal data : std_logic_vector(7 down to 0);signal address : std_logic_vector(0 to 15);signal opcode : std_logic_vector(7 downto 5);signal select : std_logic_vector(2 to 5);




Each signal in the array can be addressed individually with an index as follows:

signal_name(index)

--eg:

signal data : std_logic_vector(7 downto 0);

data(5) – refers to the 6th lower order bit of data.



Subtype

Subtype Is a type with a constraint Useful for range checking and for imposing additional

constraints on types.

Syntax: Subtype

subtype_name is base_type range range_constraint;

Example: subtype DIGITS is integer range 0 to 9;



Subtype (Contd…)

Good Example : subtype

Type std_logic_vector is array(natural range <>)of std_logic;

Type A-type is array (3 downto 0) of std_logic;

Subtype b_type is std_logic_vector (5 downto 0);

Subtype natural is integer range 0 to integer' high;

Bad Example:subtype

Type byte3 is std_logic_vector (7 downto 0);

Subtype byte4 is array (7 downto 0) of std_logic;

Array can only be used to define new type and not subtype. Std_logic_vector cannot be used in new type declaration.



Multi-dimensional Arrays

Syntax

type array_name is array (index _ range , index_range) of element_ type; E.g; type memory is array (3 downto 0, 7 downto 0); -- 4 X 8 memory

· For synthesisers which do not accept multidimensional arrays, one can declare two uni- dimensional arrays. E.g : type byte is array (7 downto 0) of std_logic; type mem is array (3 downto 0) of byte;

Initialization and reference E.g. Constant ROM:=(“10101010”, “10101010”,“10101010”,“10101010”); rom_bit <= ROM(3, 4); one_more_bit <=ROM (3) (0);



OPERATORS



OPERATORS (Contd…)


precedence Operator class OperatorsLow

High

Logical and or nand nor Xor xnor

Relational = /= < <= > >=

Shift sll srl sla sra rol ror

Add + - &

Sign + -

Multiply * / mod rem

Miscella-neous

** abs not


OPERATORS (Contd…)

REM and MOD operators :- Operate on operands of the integer types and the result is also of the

same type

- The result of the REM operator (reminder operation) has the sign of its first operand

- The result of the MOD operator has the sign of the second operand and is defined as :

ex:

7 mod 4 -- has the value 3

(-7) rem 4 -- has the value –3

7 mod (-4) -- has the value –3

(-7) rem (-4) -- has the value –3



ENTITY

Entity describes the design interface.

The interconnections of the design unit with the external world are enumerated.

The properties of these interconnections are defined.



ENTITY(contd…)entity declaration

entity <entity_name> is

port ( <port_name> : <mode> type>;

….

);

end <entity_name>;



ENTITY (contd…) Example of a VHDL entity

entity andgate is

port (c : out bit;

a : in bit;

b : in bit

);

end andgate; -- or just end entity (VHDL 1993)



ENTITY (contd…) Modes in VHDL

There are four modes for the ports in VHDLin

out

inout

buffer

These modes describe the different kinds of interconnections that the port can have with the external circuitry.



ENTITY (contd…) Modes in VHDL



ENTITY (contd…) Type

The type describes to properties of an object in VHDL.

In the example program the type bit has been used.

Bit defines that the port under question can take on one of two values ‘0’ and ‘1’.



2.Architecture



2.ARCHITECTUREarchitecture declaration

Architecture defines the functionality of the entity.

It forms the body of the VHDL code.An architecture belongs to a specific entity.Various constructs are used in the description of the architecture.



2.ARCHITECTURE(contd…)architecture declaration

architecture <architecture_name> of <entity_name> is

<declarations>

begin

<VHDL statements>

end <architecture_name> ;


entity_name

architecture_name


2.ARCHITECTURE(contd.).Example of a VHDL architecture

entity andgate is

port (c : out bit;

a : in bit;

b : in bit

);

end andgate;

architecture arc_andgate of andgate is

begin

c <= a and b;

end arc_andgate;


ca

b

andgate


2.ARCHITECTURE (contd…) Signals Signals are VHDL objects that are used to represent

interconnections in the circuit.

They are interpreted as wires and carry all the properties of a wire in hardware.

Signals have to declared of a particular type.



2.ARCHITECTURE (contd…) Assignments The “<=“ operator is used to assign signals a value.

Only values of the same type can be assigned to a signal.

Ports are also considered as signals and are assigned values using the same operator.



2.ARCHITECTURE (contd…) Another example code

entity exorgate is

port ( c : out bit;

a : in bit;

b : in bit

);

end exorgate;

architecture arc_exorgate of exorgate is

begin

c <= a xor b;

end arc_exorgate;



2.ARCHITECTURE (contd…) Logical operators VHDL defines a set of logical operators for expressing

logical functions.

The set of logical operators includes:ANDORNANDNORXORXNOR -- Supported by VHDL ‘93 NOT



2.ARCHITECTURE (contd…) Explicit signal declarations

When an interconnection is required,a signal may be declared to represent an interconnection in the circuit.

The syntax for signal declaration is

signal <signal_name> : <type> := <initial_value>;

The initial value is optional.



2.ARCHITECTURE (contd…) Example code using signal assignment

entity exorgate is

port (c : out std_logic;

a : in std_logic;

b : in std_logic

);

end exorgate;


exorgate

a

bc



architecture arc_exorgate of exorgate is

signal temp1, temp2 : std_logic;

begin

temp1 <= a and (not b); a

temp2 <= b and (not a);

c <= temp1 or temp2;

end arc_exorgate; b


c



entity halfadd is

port(a, b : in bit;

sum, carry : out bit

);

end halfadd;

architecture v1 of halfadd is

begin

sum <= a xor b after 10 ns;

carry <= a and b after 10 ns;

end architecture v1;



2.ARCHITECTURE (contd…) The std_logic type

Std_logic is a standard type which is used to closely represent hardware.

It defines 9 values that an object can take.They are as follows:



2.ARCHITECTURE (contd…) The std_logic type

‘u’ unspecified

‘x’ unknown

‘0’ strong zero

‘1’ strong one

‘z’ high impedance

‘w’ weak unknown

‘l’ weak zero

‘h’ weak one

‘-’ don’t care



2.ARCHITECTURE (contd…) Hierarchical designs

A larger design entity can call a smaller design unit in it.

This forms a hierarchical structure.

This is allowed by a feature of VHDL called component instantiation.

A component is a design entity in

itself which is instantiated in the

larger entity.


larger entity

component


2.ARCHITECTURE (contd…) Declaring a component

Components must be declared in the declarative part of the architecture.

Syntax:

component <comp_name>

port (<port_name : <mode> <type>

);

end component;



2.ARCHITECTURE (contd…) Component instantiation

The instance of a component in the entity is described as follows:

<instance_name>:<comp_name>

port map (<association list>);



2.ARCHITECTURE (contd…) Example of 3-input and gate by instantiation of 2-input and gates


u1

u2

i1i2

i3

temp1

o

entity and3gate is

port (o : out std_logic;

i1 : in std_logic;

i2 : in std_logic;

i3 : in std_logic

);

end and3gate;


2.ARCHITECTURE (contd…) Example of 3-input and gate by instantiation of 2-input and gates

architecture arc_and3gate of and3gate is

component andgate is


a : in std_logic;

b : in std_logic);

end component;

signal temp1 : std_logic;

begin

u1: andgate

port map(temp1, i1, i2);

u2: andgate

port map(o, temp1, i3);

end arc_and3gate;



2.ARCHITECTURE (contd…) Components The component name identifies the entity which is

being used as a lower level unit in the design.

The instance name specifies the specific occurrence of the component.

The port map connects signals in the higher level design unit and the component.

The connections in the association list may be declared in two ways:

Positional association Named association



2.ARCHITECTURE (contd…)Positional association

The names of the signals in the higher level entity are written in the port map statement and each signal is mapped with port in the component declaration in the order in which they are declared.

The order in which the signals are written has to match with the order of the ports of the component to which they should be connected.



2.ARCHITECTURE (contd…) Named association

The signals of the higher level entity are connected to the ports of the components by explicitly stating the connections.

e.g: The 3 input and gate may be re-written as

architecture arc_and3gate of and3gate is

component andgate is


a : in std_logic;

b : in std_logic);

end component;



2.ARCHITECTURE (contd…) Named association

signal temp1 : std_logic;

beginu1: andgate

port map (c => temp1,

b => i2,

a => i1);

u2: andgate

port map(a => temp1,

b => i3,

c => o);

end arc_and3gate;

Here, the order in which the signals are written in not important.



3.Configuration

Note: Architecture can have only one entity



3.Configuration (contd..)

This statement selects one of several Architectures for a single entity.

Components within Architectures can also be chosen.

This allows use of different Algorithms and levels of Abstractions for an entity by defining different architectures.




Unless specified, the last compiled Architecture is used for simulation.

Synthesis tool ignores configurations.

Configuration saves re-compile time when some components need substitution in a large design.




Configuration declaration is used to select one of the many architectures that an entity may have.

Syntax:


configuration configuration_name of entity_name is

for architecture_name

for instantiation:component_name

use library_name. entity_name(architecture_name);

end for;

end for;

end configuration_name;



entity half_adder is

Port (A,B : in bit;

Sum, carry : out bit);

end half_adder;

architecture ha_stru of half_adder is

component xor_2

Port (c,d:in bit,

e:out bit);

end component;

Component and_2

Port(l,m:in bit,

n:out bit);

end component;

begin

X1: xor_2 port map (A,B,Sum);

A1: and_2 port map(A,B,Carry);

end ha_stru;




Configuration for Half-adder entity :

Library CMOS_LIB, MY_LIB;

configuration HA_BINDING of half_adder is

for HA_stru

for X1:xor_2

use entity cmos_lib.xor_gate(dataflow);

end for;

for A1 : and_2

use configuration MY_LIB.and_config;

end for;

end for;

end HA_BINDING;




Configuration for the architecture body with no components (e.g. Dataflow Model)

configuration DEC_CONFIG of DECODER2X4 is

for DEC_DATAFLOW

end for;

end DEC_CONFIG;

“DEC_CONFIG defines a configuration that selects the DEC_DATAFLOW architecture body for the DECODER2X4 entity”




library TTL, Work ;

configuration V4_27_87 of Processor is

use Work.all ;

for Structure_View

for A1: ALU use configuration ALU_Desi ;

end for ;

for M1,M2,M3: MUX

use entity Multiplex4 (Behavior) ;

end for ;

for all: Latch

-- use defaults

end for ;

end for ;

end configuration V4_27_87 ;



Concurrent Constructs(contd…) All concurrent statements in an architecture are executed

simultaneously.

Concurrent statements are used to express parallel activity as is the case with any digital circuit.

Concurrent statements are executed with no predefined order by the simulator. So the order in which the code is written doesn’t have any effect on its function.

They can be used for dataflow , behavioral and structural descriptions.

Process is the only concurrent statement in which sequential statements are allowed.



Concurrent Constructs (contd…)

All processes in an architecture are executed simultaneously. Current statements are executed by simulator when one of

the signals in its sensitivity list changes. This is called occurrence of an ’event’.

e.g. C<= A or B;

Is executed when either signal A or B changes. Process(clk, reset)….

is executed when either ‘clk’ or ‘reset’ changes. Signals are concurrent , where as variables are sequential

objects.



Concurrent Constructs(contd…) Concatenation This is the process of combining two signals into a single set

which can be individually addressed.

The concatenation operator is ‘&’.

A concatenated signal’s value is written in double quotes whereas the value of a single bit signal is written in single quotes.



Concurrent Constructs (contd…) with-select


• The with-select statement is used for selective signal assignment.

• It is a concurrent statement.

• Syntax

with expression select:

target <= expression1 when choice1

expression2 when choice2

expressionN when others;


Concurrent Constructs (contd…) with-select

All possible choices must be enumerated in the statement.

when others choice takes care of all the remaining alternatives

Each choice should be unique.

Since no two choices can be same, no question of priority.

Limited choice provided by with expression.



Concurrent Constructs (contd…) with-select Example1


a b c

0 0 0

0 1 0

1 0 0

1 1 1

Truth table of and gate


Concurrent Constructs (contd…) With select- Example2


a(2) a(1) a(0) c

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1


Concurrent Constructs(contd…) With select- Example 3

Using with-select to describe a MUX



Concurrent Constructs (contd…) When-Else

when-else(Conditional signal assignment)

Syntax :-

Signal_name<= Expression1 when condition1 else

expression2 when condition2 else

expression3;



Concurrent Constructs (contd…) When-Else

This type of assignment has one target but multiple expressions.

This statement assigns value based on the priority of the condition.

Each choice itself can be a separate equation.

Since each choice is separate expression, more than one condition can be true.

When statement is prioritized.

More choices….. Any number of Expressions



Concurrent Constructs (contd…) When-Else Example1

entity tri_state isport (a, enable : in std-logic; b : out std_logic);end tri_state;

architecture beh of tri_state is beginb <= a when enable =‘1’ else ‘Z’;end beh;




entity my_nand isport (a, b: in std-logic; c : out std_logic);end my_nand;

architecture beh of my_nand is beginc <= ‘0’ when a =‘1’ and b = ‘1’ else ‘1’;end beh;




entity my_mux is

port (A,B,C,D,:in std_logic;

CONTROL: in std_logic_vector (1 downto 0)

Z: out std_logic);

end my_mux ;

architecture beh of my_mux is

begin

Z<= A when CONTROL=”00” else

B when CONTROL=”01” else

C when CONTROL=”10” else

D ;

end beh;




architecture when_grant of bus_grant isbegindata_buss<= d1 when e1= ‘1’ else d2 when e2= ‘1’ else d3 when e3= ‘1’ else ‘Z’;end when_grant; -- Priority considered



Concurrent Constructs (contd…) When-Else Example5 Example of a MUX using when-else



Concurrent construct(contd…) When-else vs. with-select

Compared to the ‘when’ statement, in the ‘with’ statement, choice is limited to the choices provided by the with ‘expression’, whereas for the ‘when’ statement each choice itself can be a separate expression.

The when statement is prioritized (since each choice can be a different expression, more than one condition can be true at the same time, thus necessitating a priority based assignment) whereas the with statement does not have any priority (since choices are mutually exclusive) .



Concurrent Constructs (contd…) Process

Process defines the sequential behavior of entire or some portion of the design.

Syntax----

process (sensitivity list)

declarations

begin

sequential statements;

end process;

Process is synchronized with the other concurrent statements using the sensitivity list or wait statement.




Statements, which describe

the behavior in a process,

are executed sequentially.

All processes in an archite-

cture behave concurrently.

Simulator takes Zero simula-

tion time to execute all

statements in a process.




Statements are executed sequentially in zero simulation time.

Process repeats forever, unless suspended.




Process can be in waiting or executing.

start

Once the process has started it takes time delta ‘t’ (the simulator’s minimum resolution) for it to be moved back to waiting state. This means that no simulation time is taken to execute the process.


executing

waiting




• All processes executes at start-up until they reach first wait statement.

• For a wait statement the simulator runs it after the wait is over.


Concurrent Constructs (contd…) Process Simulator runs a process

when any one of the signals in the sensitivity list changes.

Process should either have a “sensitivity list” or a “wait” statement at the end; but not both.

Only signal names are allowed in the sensitivity list.




Wait ”statement at the end of the process is equivalent to the “sensitivity list” at the beginning of the process.

-----Why?

Example:




Wait statement Suspends the execution of a process or procedure until

some conditions are met.

Three basic forms:

Syntax:

wait on sensitivity clause

wait until condition clause

wait for timeout clause

Wait on sensitivity list until condition for time expression;



Concurrent Constructs (contd…) ProcessExamples:

wait on A, B, C :

suspended until event occurs on A, B or C.

wait until clk = ‘1’:

suspended until event occurs on clk and clk = ‘1’;

wait for 10 ns :

suspended till 10ns.

wait on clk until count < 30 :

suspended until event occurs on clk and count < 30.

wait until count < 30 :

suspended forever since event is never going to occur.



Concurrent Constructs (contd…) Process If no explicit sensitivity list, then at least one wait

statement is must, else process never suspends.

Wait for ‘0’ ns?

-- Means wait for 1 delta.

-- This statement is useful when you want process to be delayed so that delta delayed signal assignment within a process can take effect.




Wait0 :



Processes: Types

There can be two types of processes in VHDL -- Combinational process. -- Clocked process.

Combinational process:-- Generates purely combinational logic-- All the inputs must be present in sensitivity list.-- Latches could be inferred by the synthesizer to retained the

old value, if an output is not assigned a value under all possible condition.

-- To avoid inference of latches completely specify the values of output under all conditions and include all ‘read’ signals in the sensitivity list.



Processes: Types (contd…)

a out1

b c

Why latches are undesirable

In combinational process?


Incomplete output specification

Latch inferred!



--- Aim of combinational process is to generate pure combinational circuit.

--- If Latch is inferred,

Timing will deteriorate.

Number of gates will increase

Latch will break the test rules for generating ATPG (Automatic test Pattern Generator)




Omission of signal from the sensitivity list:-

-- In combinational process if input signal is not contained in a sensitivity list than the process will not behave like combinational logic in hardware, Why?

-- The process will not be activated when the value of the omitted input signal is changed with no new value assigned to the output.

(which is not the case with actual hardware)

Thus VHDL Simulation and synthesized hardware will behave differently.(This is called Synthesis – Simulation mismatch )




Example (Bad) – Incomplete sensitivity list.




Clocked Process:-Clocked processes are synchronous and several such processes can be joined with the same clock.

Generates sequential and combinational logic.All signals assigned within clock detection are registered (I.e. resulting flip-flop)




Any assignment within clock detection will generate a Flip-flop and all other combinational circuitry will be created at the ‘D’ input of the Flip-flop.




A

B Q

C

clk

reset


DFF



d

output

clk

pass

reset


DFF


Concurrent Constructs (contd…) Drivers


• Are created by signal assignment statements

• Concurrent signal assignment produces one driver for each signal assignment




Suppose a signal has multiple drivers as shown




Signals with multiple sources can be found in numerous applications.

– Ex. : Computer data bus may receive data from the processor, memory, disks, and I/o devices.

– Each of the above devices drives the bus and each bus signal line may have multiple drivers.

- Such multiple source signals require a method for determining the resulting value when several sources are concurrently feeding the same signal line.


Concurrent Constructs (contd…) Signals within process

Process places only one driver on a signal.

Value that the signal is updated with is the last value assigned to it within the process execution.

Signals assigned to within a process are not updated with their new values until the process suspends.



Sequential Constructs

The final output depends on the order of the statements, unlike concurrent statements where the order is inconsequential .

Sequential statements are allowed only inside process.

The process statement is the primary concurrent VHDL statement used to describe sequential behavior.

Sequential statements can be used to generate both combinational logic and sequential logic.



Sequential Constructs (contd…)

Sequential logic can be described using both concurrent and sequential constructs.

Sequential logic is implemented in hardware using flip-flops.

Flips-flops are essentially edge-triggered devices.

To detect the edge, the ‘event signal attribute is used.



Sequential Constructs (contd…) if-elsif-else statement


• An if-elsif-else statement selects one or none of a sequence of events to execute.

• The choice depends on one or more conditions.

• if – else corresponds to when else command in the concurrent part.

• if statements can be used to generates prioritised structure.

• if statements can be nested.


Sequential Constructs (contd…) if In the if statement, outputs should be specified for all possible

values of the input.

Incomplete specification of outputs will result in the circuit creating latch to retain the original value of the output.

eg: process (a, b, c )

begin

if ( c = ‘1’ ) then

out1 <= a and b ;

end if;

end process;

The outputs have not been specified for the condition c=‘0’ When c becomes 0, the old value of out1 is retained.



Sequential Constructs (contd…) if-elsif-else statement

Syntax:

if <condition1> then

<statements>;

[elsif <condition2> then

<statements>;]

….

[else

<statements>;]

end if ;


priority


Sequential Constructs(contd…) if-elsif-else statement



sequential process to model JK flip-flop



Sequential Constructs (contd…) case The case statement corresponds to with-select in

concurrent statements.

The case statement selects, for execution one of a number of alternative sequences of statements depending on the value of the select signals.

All choices must be enumerated. ‘others’ should be used for enumerating all remaining choices which must be the last choice.

A range of values can be specified as a choice.

Multiple target assignment is possible



Sequential Constructs (contd…) case

Case statement results in a parallel structure.

The choices for the case statement must not overlap.i.e. each choice of the expression must be covered in one and only one clause



Sequential Constructs (contd…) case



Sequential Constructs (contd…) null

The null statement is used to describe no action.

In the example of the mux, when the select lines assume a value other than those described, the output retains it’s previous value.

Note: When using std_logic, the input combination for all nine value have to be considered in the case statement.




Does not perform any action

Can be used to indicate that when some conditions are met no action is to be performed

Example:





MUX with tri-state output enable


Sequential Constructs (contd…) null (contd..)


MUX with tri-state output enable


Sequential Constructs (contd…) D flip-flop



D flip-flop (reset)



Concurrent and Sequential Data Processing…. At A Glance….


Concurrent VHDL Constructs

• Process statement• When-Else statement• With-select statement• Signal declaration• Block statement

Sequential VHDL Constructs• If-then-else statement• Case statement• Loop statement• Return statement• Null statement• Wait statement• Variable Declaration• Variable Assignment

Both• Signal assignment• Type and constant declaration• Function and procedure calls• Assert statement.• After delay• Signal attributes.


Signal Vs. Variable

Signal It connects design entities

together (acts as a wire).

Signals can be declared both inside and out side of the process (sequential inside process, concurrent outside process)

Signals have 3 properties attached1. Type & Type Attributes.

2. Value.

3. Time.(it has a history)

Signal is assigned it’s value after a delta delay.

Signals require more memory & showers simulation.

Variable These are identifiers within

process or subprogram.

Variables can only be declared inside a process. These cannot be used to communicate between two concurrent statements.

Variables have only1) Type.

2) Value.

3) It doesn’t have history.

Variable is assigned its value immediately.

Variable require less memory & enables fast simulation.



Signal Vs. Variable

Signal

Time sum1 sum2

0 0 0

10 0 0

10+1delta 1 1

20 1 1

20+1 delta 2 2

30 2 2

30+1delta 3 3

Variable

Time sum1 sum2

0 0 0

10 1 2

10+1delta 1 2

20 2 3

20+1 delta 2 3

30 3 4

30+1delta 3 4



Signal Vs.Variable (cont…)

What will be the value of Y & Z ?



Signal Vs. Variable (contd…)



Sequential Constructs (contd…) loop statement

Loop Statement

Used to iterate through a set of sequential statements.No declaration is required explicitly for Loop identifier.Loop identifier cannot be assigned any value within

Loop.Identifier outside the loop with the same name as loop

identifier has no effect on loop execution.




While loop

Syntax:

loop_label: while condition loopsequence_of_statementsend loop loop_label

Statements are executed continuously as long as condition is true.

Has a Boolean Iteration Scheme.

Condition is evaluated before execution.




For loop

Syntax:

loop_label: for loop_parameter in discrete_range loopsequence_of_statementsend loop loop_label;

Has an Integer Iteration Scheme

Number of repetitions is determined by an Integer range

The loop is executed once for each value in the range

Labels should be used for nested loops.

Next statement to skip the current iteration and go to next iteration




Example :

factorial := 1;for number in 2 to N loop

factorial := factorial * number;end loop;

-- N is a generic number




Next Statement Syntax:

next;

next loop_label when condition;

Skips the remaining statements in the current iteration of the specified loop.

Execution resumes with the first statement in the next iteration of the loop.




Exit Statement

Syntax:

Entirely terminates the execution of the loop in which it is located.




Note: Exit : Causes the specified loop to be terminated. Next :Causes the current loop iteration of the specified loop to be

prematurely terminated; execution resumes with the next iteration



State machine in VHDL Only one state machine per module.

Separate out any structural logic, e.g. muxes, counters, etc., from the state machine. Ideally only random logic should be included.

Make your state machine completely synchronous.

Asynchronous state machine need extra care when they are designed

All the flip-flop should be clocked at the same clock. Having multiple clocks will complicate the design and optimization to a great extent.



State machine in VHDL Always use dedicated clock and reset .

Similarly it is extremely important that all the flip-flops recover from reset simultaneously.

Choose an optimum encoding for the state vector.(Binary and One Hot)

To improve design performance, you may divide large state machines into several small state machines and use appropriate encoding style for each.

Every state machine should have a control signal ensuring the machine in known state.



State machine in VHDL To implement a state machine in VHDL, the State

diagram is the only requirement..

In VHDL, each State of FSM is translated into a case in a “case-when” construct. and is simply one of the case statement branches.

State transitions are specified using “if-then-else” statements.



State machine in VHDL State assignment problem is definitely a coding problem.

Choice of State Assignment has a significant effect on the amount of hardware required for NSD and Output Decoder. and, therefore should aim at minimizing this hardware.

No general technique is available to guarantee optimal State assignment. The techniques are arbitrary and based upon Trial and Error.

Special code assignment for certain exclusive states . Ex:- Assignment of code ZERO to the INITIAL DEFAULT State.

This allows an asynchronous RESET into this initial state and machine can be made to start from the initial state.



State machine in VHDL

To specify a FSM fully, we have to completely define the specification.

Specification of inputs () and outputs (Z) is done with the VHDL entity declaration itself.



State machine in VHDL

The set of states is generally defined as an enumerated type:

type device_states is (idle, grant_to_zero, S5,error);

A state vector is created to take the state values:

signal state_v: device_states;

This completely specifies Q, the state set.

What still remains to be specified is d, the next state function, and l, the output function.

Both of these are specified in the architecture, in different ways



State machine in VHDL… style1

In this style, only one process is created, and both the outputs and next state are specified in it. It gives rise to registered outputs.




This consists of two processes:

A combinatorial process to generate the output function and next state function.

The other to synchronize next state assignments with the clock. This model follows the hardware analogy of a combinatorial part and a memory part.




This style is similar to style 1, but the output assignments are made outside the process (or in a block statement).

The circuit generated will be similar to that of style 2



Delay’s in VHDL

VHDL allows signal assignments to include delay specifications, in the form of an ‘after’ clause.

The ‘after’ clause allows you to model the behavior of gate and delays.

Delay’s are useful in simulation models to estimate delays in synthesizable design.

Two fundamental delay are Inertial delay. Transport Delay.



Delay’s in VHDL (contd…) Inertial

1.Inertial Delay:- Inertial Delay models the delays often found in switching circuits (component delays).

These are default delays.Spikes are not propagated if after clause is used.

An input value must be stable for an specified pulse rejection limit duration before the value is allowed to propagate to the output.



Delay’s in VHDL (contd…) Inertial In addition value appears at output after specified

inertial delay.

If input is not stable for the specified limit than no output change occurs

Often used to filter out unwanted spike and transients on signals.

E.g. Z<= reject 4ns inertial A after 10ns; Z<= inertial A after 10ns;

--inertial key word is by- default as this delay is default.


In reject statementInertial is must


Delay’s in VHDL (contd…) InertialReject in inertial delay model: Inertial delay is used to model component delay.

Spike of 2ns in cmos component with delay of 10ns is normally not seen at the output.

Problem arises if we want to model a component with delay of 10ns, but all spikes at input > 5 ns are visible output.

Above problem can be solved by introducing reject & modeling as follows:

oup<= reject 5 ns inertial Inp after 10 ns;



Delay’s in VHDL (contd…) Transport Transport delay models the behavior of a wire, in which

all pulses (events) are propagated.

Pulses are propagated irrespective of width.

Good for interconnect delays.

Models delays in hardware that does not exhibit any inertial delay.



Delay’s in VHDL (contd…) Transport This delay represents pure propagation delay I.e. any

change on input, no matter how small, are propagated to output after specified delay.

Spikes are also propagated.

Routing delays can be modeled using transport delay

Z<= transport a after 10ns;



Delay’s in VHDL (contd…) Example



Delay’s in VHDL (contd…) Delta It is used to achieve Concurrency & order independence in zero

delay models using event scheduling.

A delta delay is an infinitesimal interval that never accumulated to an absolute unit.

To better understand the delta time concept, you should think of simulation time to be two-dimensional.

The following graph depicts the simulation activity of a hypothetical VHDL model.



Delay’s in VHDL (contd…) Delta





Thus the code sequence does not change the Output Result & order independencei.e. concurrency is achieved.


Test Benches in VHDL…

To test a circuit we will design another circuit (test bench) which will generate the signal required to test our circuit.

Interestingly this new circuit is also described in VHDL.


TestProcess

Ip1

DUT op1

ip2



Contd…..


Library work

My_design

My_design_beh

Design_w_sig




BeginU1 : my_designPort map(ip1=> ip1_s, ip2=> ip2_s, op1=>op2_s); ………………….End my_test_a;

Test_p : processBeginFor i in 0 to 20 loop ip1<= not( ip1); wait for 10 ns; ip2<= not(ip20);wait for 10 ns;End forEnd process;

Ip1,= ‘0’—initialization Ip2<=‘0’ —initialization Ip1 <= not ip1 after 10 ns;Ip2 not ip2 after 15 ns;

Test_p : processBeginIp1<=‘0’;Ip2<= ‘0’;Wait for 10 ns;Ip1<=‘0’;Ip2<= ‘0’;Wait for 10 ns;Ip1<=‘0’;Ip2<= ‘0’;Wait for 10 ns;


Resolution Function

VHDL uses a Resolution Function to determine the actual output.

For a multiple driven signal, values of all drivers are resolved together to create a single value for the signal.

This is known as “Resolution Function” Examines the values of all of the drivers and returns a single

value called the resolved value of the signal.

std_logic and std_logic_vector are resolved types. The de facto industrial standard types.



The Assert statement… Error Management in VHDL

Used for reporting errors when a condition is FALSE.

Syntax

assert <condition>

report <message>

severity <level> ;

If condition for an assert is not met, a message with severity level is sent to user in simulator command window.

Using Assert you can,

1) Test prohibited signal combinations.

2) Test whether time constraint is being met or not.

3) Test if any unconnected inputs are present for the component.




Severity levels are

1) Note: Used as a message for debugging.

2) Warning: For timing violations, invalid data.

3) Error: Error in the behavior of the model

4) Failure: Catastrophic failure. Simulation is halted.

Default Severity level at which VHDL simulator should abort simulation is “ERROR” level, though it can be set.

Assert is both a sequential as well as a concurrent

statement




1. Testing-prohibited input combination




process (a,b)

begin

if (a=‘1’ and b=‘1’) then

assert false

report ” a=‘1’ and b=‘1’ ”;

end if;

end process;

-- VHDL-87

process (a,b)

begin

assert not(a=‘1’ and b=‘1’)

report ” a=‘1’ and b=‘1’ ”;

end process;

-- VHDL-93


--Testing-prohibited input combinationUsing process



2. Testing unconnected inputs

begin assert in(0 ) /=‘X’ and in(1) /= ‘X’ report “in is not connected” Severity warning;end




3. Check for Simulation time



Generate Statement

This is a type of loop, which can be used outside the process.

Label for the loop is must.

Concurrent statements can be conditionally selected or replicated using “generate” statement.

Used to create multiple copies of components or blocksFor ex: Provides a compact description of regular

structures such as memories, registers, and counters.



Generate Statement (contd…) Two forms of “generate” statement

for…generate Number of copies is determined by a discrete range

Syntax: label: for identifier in range generate {concurrent_statement} end generate [ label ] Range must be a computable integer, in either of these

forms: integer_expression to integer_expression integer_expression downto integer_expression



Generate Statement (contd…) Example1 :-



Generate Statement (contd…) Example1 (contd…)



Generate Statement (contd…)

Identifier is assigned the first value of range, and each concurrent statement is executed once.

Identifier is assigned the next value in range, and each concurrent statement is executed once more.

Above step is repeated until identifier is assigned the last value in range. Each concurrent statement is then executed for the last time, and execution continues with the statement following end generate. The loop identifier is then deleted.



Generate Statement (contd…)


– if…generate

–Zero or one copy is made, conditionally


Generate Statement (contd…) Example2



Generate Statement (contd…) Example2 (contd…)



Block Statement

Main purpose of block statement is organizational only or for partitioning the design.

Syntax:block_label : block

declarations begin concurrent statements

end block block_label;

Introduction of a Block statement does not directly affect the execution of a simulation model.



Block Statement Block construct only separates part of the code without adding any functionality.

Code 1: exactly the same way during simulation.

A1: OUT1 <= '1' after 5 ns;

LEVEL1 : block

begin



end block LEVEL1;

Code 2:






Block Statement (Guarded)

If block has Guard Expression Boolean signal called guard is defined explicitly for this block.

Guard Expression can enable and disable drivers inside the block (enables when true & disables when false).

Guarded Block statement controls the assignment of values to guarded signals within a block.

Guarded blocks are used when there are multiple drivers for one signal.(The guard should be such that there is only one active driver at any point of time).



Block Statement (Guarded)



Block Statement (Guarded)3 Bit Counter using Block



Generic Statement….

It allows to pass certain parameters into a design description from its environment.

--e.g.Rise & Fall Delays, Size of Ports, Etc……

Are specified in entities inside the generic clause.

Syntax :

generic ( constant_name : type [ := value ] constant_name : type [ := value ] );




Applications of generics

Can be used anywhere in a code where a static value is needed.

Use of generics facilitates easy design changes. For modeling ranges of subtypes subtype ALUBUS is integer range TOP downto 0;

-- TOP is a Generic Used in behavioral modeling of components.

For example : Timing parameters such as delays, Set-up times, Hold times can be modeled using Generics.




Generics vs. Constants

Generics Are specified in entities. Hence, any change in the value of a generic affects all

architectures associated with that entity.

Constants Are specified in architectures. Hence, any change in the value of a constant will be localized to

the selected architecture only.



Generic in Component Instantiation.

Syntax:

-- component declaration :

component component-name is

generic (list-of-generics) ;

port (list-of-interface-ports);

end component ;

-- component instantiation statement:

component-label: component-name

generic map (generic-association-list)

port map (port association-list);



Generic in Component Instantiation



Attributes

Attributes can be used to for modeling hardware characteristics.

An attribute provides additional information about an object (such as signals, arrays and types) that may not be directly related to the value that the object carries.

Attributes can be broadly classified as :1. Predefined - as a part of 1076 std.2. Vendor Defined.



1. Predefined Attributes: Value kind attributes

1. Value kind attributes: Left, Right, High, Low, Length, Ascending

- ‘left : returns left most value of type or subtype

e.g. type bit_array is array (1 to 5) of bit; variable L : integer := bit_array ‘left;

-- L takes left most bound I.e. 1

- ‘right : returns right most value of type or subtype e.g. type bit_array is array (1 to 5) of bit;

variable R : integer:= bit_array ‘right;

-- R takes the right most bound I.e. 5- ‘high : returns upper bound of type or subtype

e.g. type bit_array is array (-15 to +15) of bit;

variable H : integer:= bit_array 'high;

-- H takes the value of 15



Predefined Attributes: Value kind attributes

- ‘low : returns lower bound of type or subtype

e.g. type bit_array is array (15 to 0) of bit;

variable L : integer:= bit_array 'low;

-- L has a value of 0

- ‘length : returns the length of an array

e.g. type bit_array is array (0 to 31) of bit;

variable len : integer:= bit_array 'length;

-- len has a value of 32



Predefined Attributes: Value kind attributes

‘ascending : returns a Boolean true value of the type or subtype which is declared with an ascending range

e.g. type asc_array is array (0 to 31) of bit; type desc_array is array (36 downto 4) of bit; variable A1: boolean := asc_array ’ascending; --A1 has a value ‘true’ variable A2: boolean := desc_array ’ascending; --A2 has a value ‘false’

NOTE:- Value Kind attributes return an explicit value and are applied to a type or subtype.



2. Predefined Attributes: Function kind attributes-1

2. Function kind attributes return information about a given type,signal, or array value .

Function kind attributes: ’Pos,’Val,’Succ,’Pred,’Leftof,’Rightof. - pos (a) : returns the position number of ‘a’ e.g. type state_type is (init, hold, strobe,read, idle); variable p : integer := state_type ’pos(read); -- ’p’ has the value of 3.

- val (a) : returns the type value at position ‘a’ e.g. type state_type is (init, hold, strobe,read, idle); variable v : state_type := state_type ’val(3); -- ’v’ has the value of read.

- succ (a) : returns next value of a; e.g. type state_type is (init, hold, strobe,read, idle); variable v : state_type := state_type ’succ(init); --’v’ has the value of hold.




- pred (a) returns previous value of a e.g. type state_type is (init, hold, strobe,read, idle); variable v: state_type := state_type ’pred(hold); --’v’ has the value of init.

-- leftof (a) : returns value to the left of a e.g. type state_type is (init, hold, strobe,read, idle); variable v: state_type := state_type ’leftof(idle); --’v’ has the value of read.

-- rightof (a) : returns value to the right of a e.g. type state_type is (init, hold, strobe,read, idle); variable v: state_type := state_type ’rightof(read); --’v’ has the value of idle.




Case where ‘Leftof & ‘Pred are different e.g.

type state_type is (init, hold, strobe,read, idle); subtype reverse_state_type is state_type range idle downto init;

variable v1: reverse_state_type := reverse_state_type ’lefttof(hold); --v1 has the value of strobe.

variable v2: reverse_state_type := reverse_state_type ’pred(hold); --v2 has the value of init.




’event, ’active, ’last_event, ’last_value, ’last_active ’event

e.g. clk’event : returns true if an event occurred on clk.

’active Return true if any transaction (scheduled event) occurred on the

signal in the current simulation delta cycle. e.g.




’last_event Returns time elapsed since the last event on the signal. Very useful for implementing Set_up time checks, Hold time checks, and Pulse

width checks. Example :




’last_value Returns the previous value of the signal before the last event

occurred. Ex.: Most full proof way of writing as the event will always be a

transition from ‘0’ to ‘1’




’last_active Returns the time elapsed since the last transaction (scheduled

event) of the signal.

e.g.;

Note: It can be used to check whether q is alive or dead (stuck at ground..)



2. Predefined Attributes: Signal kind attributes

Signal kind attributes when invoked,create special signals that have values and types based on other signals.

’delayed(time) Creates a delay signed that is identical in waveform to the signal the

attribute is applied to.

(The time parameter is optional and may be omitted.) e.g.;




‘stable(time) Creates a signal of type boolean that becomes true when

the signal is stable (has no event) for some given period of time.

e.g. s1’stable (5ns) : creates a boolean signal that is true if s1 has not changed in the last 5ns. If no time parameter is specified, then s1 has not changed in the current simulation time.




’transaction

e.g. s1’transaction Creates a signal of type bit that toggles its value for every

transaction that occurs s1.

’quiet Creates a boolean signal that is true whenever the signal it is

attached to has not had a transaction or event for the time expression specified.

Note: It is used to detect the signal whether alive or dead




e.g. Use of a Transaction attribute over an event attribute(Such as for memory modeling)

The same data may be getting repeated over the data line This does not trigger any event and hence data may be lost. By waiting on a transaction, the process is executed whenever a value (same or new) is assigned to data.



2. Predefined Attributes: Range kind attributes Range Kind attributes return a special value that is a range,

such as you might use in a declaration or looping scheme.

’range Returns the range value for a constrained array. e.g. function parity (d: std_logic_vector) return

std_logic is

variable result:std_logic:=‘0’;

begin

for i in d’range loop

result:= result xor d(i)

end loop;

return result;

end parity;



2. Predefined Attributes: Signal kind attributes ‘Reverse_range

Returns the reverse of the range value for a constrained array. e.g. STRIPX:

for i in d’reverse_range loop

if d(i)= ‘x’ then

d(i):= ‘0’;

else

exit; -- only strip the terminating Xs.

end if;

end loop;



Packages

Packages It is a collection of commonly used subprograms,

data types, constants,attributes and components. It allows designer to use shared constant or function

or data type. Packages are stored in libraries for convenience

purposes. “USE” statement is used to access the package.



Packages Package consists of two parts :

1. Declaration &

2. Body.

Package declaration: Syntax:

package <Package_name> is

{set of declarations}declarations;

end package_name;_name; Defines the interface for the package similar as

entity(e.g.behavior of function does not appear here, only functional interface).

Can be shared by many design units. Contains a set of declarations such as subprogram, type,

constant, signal, variable, etc.



Packages STANDARD and TEXTIO are provided in the STD library which

defines useful data types and utilities.

Example : library IEEE; use IEEE.Std_Logic_1164.all; Use IEEE.std_Logic_unsigned.all; Use IEEE.std_Logic_signed.all; Use IEEE.std_Logic_arith.all; Use IEEE.numeric_std.all;

Library design_lib; Use design_Lib.Ex_pack.D_FF;


Selective importing package

declaration


Packages

2) Package body: Syntax:

package body package_name is

declarations;

sub program body;

end package_name;

Specifies the actual behavior of the package Similar as architecture. A Package Declaration can have only one Package body, both having

the same names. (Contrast to entity architecture)

Only one-to-one association


Packagedeclaration

PackageBody


PackagesPackage body

Contains the hidden details of a package. Completes constant declarations for deferred constant. (Deferred constant: constant declaration without value

specified) Is used to store private declarations that should not be

visible. If Package declaration has no function or procedure or

deferred constant declaration than no package body is required.



Packages

Example Package Declaration:



Packages



Library It is an implementation-dependent storage facility for

previously analyzed design units.

Compiled VHDL design unit is saved in the work library as default.

In order to use components and packages from a particular library, the library and packages must be specified in VHDL code using

Library <library_name>;

use <library_name>.<package_name>.all;



Library-Default

Following lines are always present by-default in each piece of VHDL code. library work; library std; use std.standard.all;

-- work and std are default libraries(no specification required)

-- Package standard defines data types:bit,bit_vector, character, time & integer.



Library-IEEE

Following line must always be included before each entity.

Library IEEE;

Use IEEE.std_logic_1164.all;

-- package includes definitions for data types:

std_logic, std_ulogic, std_logic_vector,

std_ulogic_vector,



Subprogram

There are two types of subprograms in VHDL FUNCTION --Returns a single value PROCEDURE --Can return multiple values

Although subprograms can be defined either in a package, architecture or process it is usually defined in a package so that they can be reused.

VHDL code is sequential inside subprograms.



Subprogram

Subprograms are termed impure if they modify or depend on parameters not defined in their formal parameter list. ONLY VHDL’93 SUPPORTS IMPURE FUNCTION.

Subprograms can be called sequentially within a process or concurrently in the architecture

A function has to be on the right hand size of a signal assignment whereas a procedure can be called independently.



Subprogram

Syntax: (procedure)

- procedure <procedure _ name> ( parameter list) is

declarations;

begin

statements;

end procedure procedure_ name;

Syntax: (function)

- function<function_name > ( parameter list ) return < return_type> is

declarations;

begin

statements;

end function function_name;



Subprogram

Parameter list specification consists of:

Class definition (signal, variable, constant)

Name of the parameter,

Mode of the parameter (in, out, inout)

Subtype indication

Optional initial value



Procedure

A procedure is subroutine which performs operations using all the parameters and objects, and which can change one or more of the parameters and objects in accordance with rules governing those parameters and objects.

A concurrent procedure has an implied wait statement at the end of the procedure on the signal whose mode has been declared as IN or INOUT.

A sequential procedure has no implied wait.



ProcedureSyntax:

procedure name ( parameter_list ) is declarations begin statements end name; parameter: variable name:mode type :=default value; signal name:mode type; constant name:in type :=default value; Mode :

in | out | inout



ProcedureE.g.:-



Functions

Unlike procedure, a function cannot change its argument and can only return a value.

Function parameters can only be of type constant or signal. The mode is always in. Default class is constant.

An impure function may return different values even if the parameters are the same. Whereas a pure function always returns the same values as parameters.

A function has to have a return statement with an expression the value of the expression defines the result returned by the function



Functions

The resolution function The resolution function resolves the value to be

assigned to a signal when there are multiple drivers for the given signal.

The simulator implicitly invokes the resolution function.

The resolution function



FunctionsSyntax:



Functions

E.g.:


260

VITALVHDL Initiative Towards ASIC Libraries

How To Design Using VHDLEutectics.blogspot.in


Using VITAL Models in VHDL Simulation

Introduction

VITAL stands for the ‘VHDL Initiative Toward ASIC Libraries’.

By defining naming conventions for cells & generics and an 'acceleratable' set of logic primitives VITAL has set the stage

for a dramatic increase in the portability of ASIC VHDL Libraries. ASIC Foundries Provide Library Representations that

Comply with the Specification Comprised of VITAL Primitives

CAD Vendors Provide Simulators that can: Accelerate the Primitives Import an SDF 2.1 (Standard Delay File ) Map the SDF Information into Timing Generics in the VHDL library.



What is VITAL?

Charter: Accelerate the Availability of ASIC Libraries Across industry VHDL Simulators

Top Priorities:

(1) High Accuracy for Sub-micron ASICs;

(2) Fast Simulation Performance;

(3) Aggressive Schedule

VITAL is Being Endorsed by over 60 Companies Worldwide

VITAL Consists of Standardized: Timing Routines Primitives Instance Delay Loading Mechanism Model Development Guidelines Document



Origins of VITAL



Benefits

For ASIC designers• Improved portability of designs and libraries across EDA tools• Fast simulation performance without leaving VHDL design• environment (speedups are in the order of 10-15x already!!)• Ability to use standard VITAL routines in user-written models

For Semiconductor Suppliers• Single library supports all major EDA simulation environments• High-accuracy timing support for deep sub-micron• Reduced development and maintenance costs

For EDA Vendors• Focus on tool and design issues, not libraries• Standard modeling techniques allow improved optimization and• reduced complexity



Technical Features Flexible Specification of Functionality

· Table lookup primitives (w/ multiple outputs)

· Boolean primitives (specific # inputs or programmable)

· Behavioral or concurrent style

Accurate Specification of Timing Delays

· Pin-to-pin or distributed

· State-dependent

· Conditional

Accurate Timing Check Support

· Setup and hold (including negative constraints!)

· Recovery/Removal checks

· Minimum pulse width , period checks

· Glitch on Event, Glitch on Detect, No Glitch



Technical Features (cont’d) 2-Level Performance Optimization

Primitives and Timing Checks "built-in" to simulators SDF format read directly by EDA tools Level 1 defines consistent modeling style for

acceleration

Leverages from existing industry standards IEEE 1076-87 and 1076-93 (VHDL) IEEE standard_logic_1164 (MVL9 logic value system) OVI SDF v2.1



Design Flow Architecture



Concepts Of "Level 0" & "Level 1”

Level 0 Defines The External Model Interface (Entity): Allowed I/O Data types, Generic Naming Conventions Access To VITAL Primitive/Timing Package Routines

Level 1 Defines An Internal Modeling Methodology (Architecture): Builds on The Basic Level 0 Constraints Additional Constraints For Performance Optimization



How Does Level 1 Work? Reduces Variations Allowed For Interconnection Of VHDL and VITAL Constructs

Restricts The Use Of Arbitrary VHDL and VITAL Constructs

VHDL Tools Can Recognize This Consistent Structure For Wholesale Replacement With Internal Simulator Routines

Internal Routines Can Avoid The Generality Of VHDL



VITAL Level 1 Model Architecture



Benefit To IC, System Designers Individual VITAL Routines Are Available to ALL Users

(In IEEE Library Soon)

Standardized Packages Help Ensure Standard Behavior Across

Multiple Tools and Platforms

VITAL Primitives Can Ease VHDL Modeling Burden

VITAL Pin-Pin Timing Delay Routines Can Ease Addition Of

Timing To Behavioral Models

VITAL Timing Checks May Be Used To Catch Design Requirement

Violations



Benefit To IC, System Designers

SDF Back-Annotation Is Optional -- Timing May Be Self-Contained

in Model

Most Miscellaneous User Models Are Expected To Be "Level 0"

A "Level 1" User Model Could Run Up To 15-20x Faster!!

System Designers Using ASICs and/or FPGAs Get Fast, Accurate

Simulation, With User Control of Timing Checks, Back-Annotation,

Message Levels (Unit Delay Mode Also Available)

VITAL Level 1 (Accelerated) Fault Simulation Now Available!!



VITAL



Tool And Library Support EDA Vendors Actively Supporting VITAL:

Cadence Leapfrog

Exemplar Logic Galileo

IBM EDA (internal?)

Ikos Systems Voyager

Intergraph ??

Mentor Graphics Quick VHDL

Meta-Software Master Toolbox

Model Technology V-System

Synopsys Library Compiler, (VSS Expert)

Synplicity Synplify

Veda Design Automation Vulcan, Verdict

Viewlogic ALEX Verilog-to-Vital

VHDL Technology Group SledgeHammer

Vantage Optium

Zycad Paradigm



Tool And Library SupportIC Suppliers Actively Supporting VITAL: AMI

AT&T Microelectronics

Fujitsu

Hewlett-Packard*

Honeywell

IBM Microelectronics

LSI Logic

NEC Electronics

Oki Semiconductor

Orbit Semiconductor*

Philips Semiconductors

SGS Thomson

Sharp Electronics

Texas Instruments*

Toshiba/Vertex

United Technologies (UTMC)

VLSI Libraries

VLSI Technology

Xilinx

(*) = sign-off libraries completed

(as of 6/95)



VITAL Member Companies

Ryan & RyanSharp ElectronicsSummit DesignSGS ThomsonSiemens SemiconductorSimone EnterprisesSimQuestSMOS/SeikoSunrise Test SystemsSynopsysTexas InstrumentsThomsonThomson-CSFToshiba/Vertex SemiconductorVantage/ViewlogicVeda (formerly Genrad)VHDL Technology GroupXilinxZycadi-Logix

LSI LogicLogic Modeling GroupMagnati Marelli ElectronicsMahtra MHS SAMentor GraphicsMitsubishiMississippi State UniversityModel TechnologyMotorolaNational SemiconductorNCR MicroelectronicsNEC ElectronicsNextwave Design AutomationNorth Oaks EDA ConsultingOki SemiconductorOrbit SemiconductorOrCADPhilips SemiconductorsActelAltera

Alcatel Bell TelephoneARCAD S.A.Bell Northern ResearchCadence Design SystemsCompass DesignDesign Automation SolutionsEpsonElectronic Design AutomationEricsson Telecom ABFrance TelecomFujitsuGEC Plessey SemiconductorHarris SemiconductorHewlett PackardIBM MicroelectronicsIkos SystemsIntergraph Electronics


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