vhdl lab programs

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FULL ADDER

AIM:

Design and verify full adder by using dataflow style with select statement.

PROGRAM:

Library ieee;use ieee.std_logic_1164.all;entity fa_select isport(a:in bit_vector(2 downto 0); s:out bit_vector(1 downto 0));end fa_select ;architecture beh of fa_select isbeginwith a select

s<=("00")when"000", ("10")when"001", ("10")when"010", ("01")when"011", ("10")when"100", ("01")when"101", ("01")when"110", ("11")when"111"; end beh;

SIMULATION OUTPUT:

RESULT: Full adder using dataflow style with select statement is simulated and Verified.

NARASARAOPET ENGINEERING COLLEGE -NARASARAOPET

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FULL SUBTRACTOR

AIM: Design and verify full subtractor by using dataflow style with select statement.

PROGRAM:

library ieee;use ieee.std_logic_1164.all;entity flsub_select isport(a:in bit_vector(2 downto 0);s:out bit_vector(1 downto 0));end flsub_select;architecture beh of flsub_select isbeginwith a select

s<=("00") when "000", ("11") when "001", ("11") when "010", ("01") when "011",

("10") when "100", ("00") when "101", ("00") when "110", ("11") when "111";

end beh;

SIMULATION OUTPUT:

RESULT: Full subtractor using dataflow style with select statement is simulated and verified.


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FULL ADDER

AIM: Design and verify full adder by using dataflow style with select statement

PROGRAM:

Library ieee;use ieee.std_logic_1164.all;entity fa_select1 isport(a,b,c:in bit; sum,carry:out bit);end fa_select1;architecture df of fa_select1 isbeginwith bit_vector'(a,b,c) select(sum,carry)<=bit_vector'("00") when "000" ,bit_vector'("10") when "001",bit_vector'("10") when "010",bit_vector'("10") when "100",bit_vector'("01") when "110",bit_vector'("01") when "011",bit_vector'("01" )when "101",bit_vector'("11") when "111";end df;

SIMULATION OUTPUT:

RESULT: Full adder is simulated and verified


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FULL ADDER

AIM: Design and verify full adder by using behavioural model with if,elsif& then statements.

PROGRAM:

library ieee;use ieee.std_logic_1164.all;entity fulladder isport(a:in std_logic_vector(2 downto 0); s,ca:out std_logic);end fulladder;architecture fulladder of fulladder isbeginprocess(a)beginif a="000" then s<='0';ca<='0';elsif a="001" then s<='1';ca<='0';elsif a="010" then s<='1';ca<='0';elsif a="011" then s<='0';ca<='1';elsif a="100" then s<='1';ca<='0';elsif a="101" then s<='0';ca<='1';elsif a="110" then s<='0';ca<='1';else s<='1';ca<='1'; end if;end process;end fulladder;

SIMULATION OUTPUT:



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FULL SUBTRACTOR

AIM:

Design and verify full subtractor by using behavioural model with if,elsif& then statements.

PROGRAM:

library ieee;use ieee.std_logic_1164.all;entity fullsub isport(a:in std_logic_vector(2 downto 0);d,b:out std_logic);end fullsub;architecture fullsub of fullsub isbeginprocess(a)beginif a="000" then d<='0';b<='0';elsif a="001" then d<='1';b<='1';elsif a="010" then d<='1';b<='1';elsif a="011" then d<='0';b<='1';elsif a="100" then d<='1';b<='0';elsif a="101" then d<='0';b<='0';elsif a="110" then d<='0';b<='0';else d<='1';b<='1'; end if;end process;end fullsub;

SIMULATION OUTPUT:



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FULL ADDER(DATAFLOW STYLE)

AIM:

Design and verify full adder by using dataflow style .

PROGRAM:

Library ieee;use ieee.std_logic_1164.all;entity fa1 isport(a,b,c:in bit;s,cout:out bit);end fa1;architecture fa1 of fa1 isbegins<=a xor b xor c;cout<=(a and b)or(a and c)or (b and c);end fa1;

SIMULATION OUTPUT:



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HALF ADDER ( DATAFLOW STYLE)

AIM:

Design and verify half adder by using dataflow style .

PROGRAM:

Library ieee;use ieee.std_logic_1164.all;entity ha1 isport(a,b:in bit;s,c:out bit);end ha1;architecture ha1 of ha1 isbegins<=a xor b;c<=a and b;end ha1;

SIMULATION OUTPUT:

RESULT: Half adder is simulated and verified


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HALF SUBTRACTOR ( DATAFLOW STYLE )

AIM:

Design and verify half subtractor by using dataflow style .

PROGRAM:

Library ieee;use ieee.std_logic_1164.all;entity hs1 isport(a,b:in bit;d,bo:out bit);end hs1;architecture hs1 of hs1 isbegind<=a xor b;bo<=(not a) and b;end hs1;

SIMULATION OUTPUT:

RESULT: Half subtractor is simulated and verified


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FULL SUBTRACTOR ( DATAFLOW STYLE )

AIM:

Design and verify full subtractor by using dataflow style .

PROGRAM:

library ieee;use ieee.std_logic_1164.all;entity fs1 isport(a,b,c:in bit;d,bo:out bit);end fs1;architecture fs1 of fs1 isbegind<=a xor b xor c;bo<=((not a)and b)or(b xor c);end fs1;

SIMULATION OUTPUT:

RESULT: Full subtractor is simulated and verified


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AND GATE

AIM:

Simulation and verification of various logic gates.

PROGRAM:

Library ieee;use ieee.std_logic_1164.all;entity and2 isport(a,b:in bit;y:out bit);end and2;architecture and2 of and2 isbeginy <= a and b;end and2;

SIMULATION OUTPUT:

RESULT: AND gate is simulated and verified


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OR GATE

AIM:


PROGRAM:

Library ieee;use ieee.std_logic_1164.all;entity or2 isport(a,b:in bit;y:out bit);end or2;architecture or2 of or2 isbeginy<=a or b;end or2;

SIMULATION OUTPUT:

RESULT: OR gate is simulated and verified.


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XOR GATE

AIM:


PROGRAM:

Library ieee;use ieee.std_logic_1164.all;entity xor2 isport(a,b:in bit;y:out bit);end xor2;architecture xor2 of xor2 isbeginy<=a xor b ;end xor2;

SIMULATION OUTPUT:

RESULT: XOR gate is simulated and verified


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NAND GATE

AIM:


PROGRAM:

Library ieee;use ieee.std_logic_1164.all;entity nand2 isport(a,b:in bit;y:out bit);end nand2;architecture nand2 of nand2 isbeginy<=a nand b;end nand2;

SIMULATION OUTPUT:

RESULT: NAND gate is simulated and verified.


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NOR GATE

AIM:


PROGRAM:

library ieee;use ieee.std_logic_1164.all;entity nor2 isport(a,b:in bit;y:out bit);end nor2;architecture nor2 of nor2 isbeginy<=a nor b;end nor2;

SIMULATION OUTPUT:

RESULT: NOR gate is simulated and verified


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XNOR GATE

AIM:


PROGRAM:

library ieee;use ieee.std_logic_1164.all;entity xnor2 isport(a,b:in bit;y:out bit);end xnor2;architecture xnor2 of xnor2 isbeginy<=a xnor b;end xnor2;

SIMULATION OUTPUT:

RESULT: NOR gate is simulated and verified


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NOT GATE

AIM:


PROGRAM:

library ieee;use ieee.std_logic_1164.all;entity not1 isport(x:in bit;y:out bit);end not1;architecture df of not1 isbeginy<=not x;end df;

SIMULATION OUTPUT:

RESULT: NOT gate is simulated and verified


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3-INPUT NAND GATE

AIM:

Simulation and verification of 3-Input NAND gate.

PROGRAM:

library ieee;use ieee.std_logic_1164.all;entity nand3 isport(a,b,C:in bit;y:out bit);end nand3;architecture nand3 of nand3 isbeginy <= not(a and b and C);end nand3;

SIMULATION OUTPUT:

RESULT: 3-INPUT NAND gate is simulated and verified


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4-INPUT NAND GATE

AIM:

Simulation and verification of 4-Input NAND gate.

PROGRAM:

library ieee;use ieee.std_logic_1164.all;entity nand4 isport(a,b,C,d:in bit;y:out bit);end nand4;architecture nand4 of nand4 isbeginy <= not(a and b and C and d);end nand4;

SIMULATION OUTPUT:

RESULT: 4-INPUT NAND gate is simulated and verified.


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FUNCTION VERIFICATION

AIM:

Design and verification of function F(a,b,c) = (0,2,4,5,6).

PROGRAM

library ieee;use ieee.std_logic_1164.all;entity function1 isport(a,b,c:in bit;y:out bit);end function1;architecture fun1 of function1 isbeginy<= (a and (not b))or (not c);end fun1;

SIMULATION OUTPUT:

RESULT: Function F(a,b,c) = (0,2,4,5,6) is simulated and verified.


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AIM:

Design and verification of function F(a,b,c) = (1,2,3,5,7).

PROGRAM:

library ieee;use ieee.std_logic_1164.all;entity function2 isport(a,b,c:in bit;y:out bit);end function2;architecture fun2 of function2 isbeginy<= ((not a)and b)or c;end fun2;

SIMULATION OUTPUT:

RESULT: Function F(a,b,c) = (1,2,3,5,7) is simulated and verified.


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AIM:

Design and verification of function F(a,b,c,d ) = (0,1,2,4,5,6,8,9,12,13,14).

PROGRAM:

library ieee;use ieee.std_logic_1164.all;entity function3 isport(a,b,c,d:in bit;y:out bit);end function3;architecture fun3 of function3 isbeginy<= (not c)or ((not a)and (not d))or( b and (not d ));end fun3;

SIMULATION OUTPUT:

RESULT: Function F(a,b,c,d) = (0,1,2,4,5,6,8,9,12,13,14) is simulated and verified.


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AIM:

Design and verification of function F(a,b,c,d) = (0,2,4,6,9,13,21,23,25,29,31).

PROGRAM:

library ieee;use ieee.std_logic_1164.all;entity function4 isport(a,b,c,d,e:in bit;y:out bit);end function4;architecture fun4 of function4 isbeginy<= ((not a)and (not b)and (not e))or( b and (not d )and e) or (a and c and e );end fun4;

RESULT:Function F(a,b,c,d) =(0,2,4,6,9,13,21,23,25,29,31) is simulated and verified


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HALF ADDER (STRUCTURAL MODEL)

AIM:

Simulation and verification of Half Adder using structural model.

PROGRAM:

Library ieee;use ieee.std_logic_1164.all;use vamsi.all;entity hfadder isport(A,B:in bit;S,C:out bit);end hfadder;architecture struct of hfadder iscomponent xor1 is port(a,b:in bit;c:out bit);end component;component and1 is port(a,b:in bit;c:out bit);end component;Begin

X1:xor1 port map(A,B,S);X2:and1 port map(A,B,C);

end struct;

SIMULATION OUTPUT: :

RESULT: Half Adder is simulated and verified.


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FULL ADDER (STRUCTURAL MODEL)

AIM:

Simulation and verification of Full Adder using structural model.

PROGRAM:

Library ieee;use ieee.std_logic_1164.all;entity fa2 isport(a1,b1,c1:in bit;sum,cout1:out bit);end fa2;use vamsi.all;architecture struc of fa2 iscomponent xor2port(a,b:in bit; y:out bit);end component;component and2port(a,b:in bit;y:out bit);end component;component or2port(a,b:in bit;y:out bit);end component;signal s1,s2,s3,s4,s5:bit;begin

d1:exor1 port map(a1,b1,s1);d2:exor1 port map(s1,c1,sum);d3:and1 port map(a1,b1,s2);d4:and1 port map(a1,c1,s3);d5:and1 port map(b1,c1, s4);d6:or1 port map(s2,s3,s5);d7:or1 port map(s4,s5,cout1);

end struc;

SIMULATION OUTPUT:

RESULT: Full Adder is simulated and verified.


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HALF SUBTRACTOR (STRUCTURAL MODEL)

AIM:

Simulation and verification of Half Subtractor using structural model.

PROGRAM:

Library ieee;use ieee.std_logic_1164.all;use vamsi.all;entity hfsub isport(A,B:in bit;D,B0:out bit);end hfsub;architecture struct of hfsub iscomponent xor2 is port(a,b:in bit;y:out bit);end component;component and2 is port(a,b:in bit;y:out bit);end component; component not1 is port(a:in bit;y:out bit);end component;signal s:bit;Begin

X1:xor1 port map(A,B,D);X2:not1 port map(A,s);X3:and1 port map(s,B,B0);

end struct;

SIMULATION OUTPUT:

RESULT: Half Subtractor is simulated and verified.


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FULL SUBTRACTOR (STRUCTURAL MODEL)

AIM:

Simulation and verification of Full Subtractor using structural model.

PROGRAM:

Library ieee;use ieee.std_logic_1164.all;use vamsi.all;entity fulsub isport(A,B,C:in bit;D,Bo:out bit);end fulsub;architecture struct of fulsub iscomponent and2 is port(a,b:in bit;y:out bit);end component;component xor2 is port(a,b:in bit;y:out bit);end component; component or2 is port(a,b:in bit;c:out bit);end component; component not1 is port(a:in bit;y:out bit);end component;signal S0,S1,S2,S3,S4,S5:bit;Begin

X1:xor1 port map(A,B,S1);X2:xor1 port map(S1,C,D); X3:not1 port map(A,S0);X4:and1 port map(S0,B,S2);X5:and1 port map(S0,C,S3);X6:or1 port map(S2,S3,S5);X7:and1 port map(B,C,S4);X8:or1 port map(S5,S4,Bo);

end struct;


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SIMULATION OUTPUT :

RESULT: Full Subtractor is simulated and verified.


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2 TO 4 DECODER (DATAFLOW STYLE )

AIM:

Simulation and verification of 2 x 4 AND gate decoder.

PROGRAM:

library ieee;use ieee.std_logic_1164.all;entity dec24 isport(a,b,e:in std_logic; z:out std_logic_vector(0 to 3));end dec24;architecture data of dec24 isbeginz(0)<= NOT((not a) AND (not b) AND e);z(1)<= NOT (B AND (not a) and e);z(2)<= NOT(a and (not b) and e);z(3)<= NOT(a and b and e);end data;

SIMULATION OUTPUT:

RESULT: 2 to 4 Decoder is simulated and verified.


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2 TO 4 DECODER (BEHAVIOURAL MODEL )

AIM:

Simulation and verification of 2 to 4 NAND gate decoder.

PROGRAM:

library ieee;use ieee.std_logic_1164.all;entity dec isport(a,b,e:in bit;z0,z1,z2,z3:out bit);end dec;architecture bm3 of dec isbeginprocess(a,b,e)variable abar,bbar:bit;beginabar:=not a;bbar:=not b;if e='1' thenz3<=not(a and b);z0<=not(abar and bbar);z2<=not(a and bbar);z1<=not(abar and b);end if;end process;end bm3;




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4 TO 1 MULTEPLXER (DATA FLOW STYLE )

AIM:

Simulation and verification of 4 x 1 NAND gate decoder.

PROGRAM:

Library ieee;use ieee.std_logic_1164.all;entity mu4to1 isport(i0,i1,i2,i3:in bit;s:in bit_vector(1 downto 0);z:out bit);end mu4to1;architecture df1 of mu4to1 issignal t0,t1,t2,t3,t4:bit;begint0<=(i0 and not s(1) and not s(0));t1<=(i1 and not s(1) and s(0));t2<=(i2 and s(1) and not s(0));t3<=(i3 and s(1) and s(0));z<=t0 or t1 or t2 or t3;end df1;


RESULT: 4 to 1 Multiplexer is simulated and verified.


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9 BIT PARITY GENERATOR (STRUCTURAL MODEL)

AIM:Simulation and verification of 9-bit parity generator using structural model.

PROGRAM:

Library ieee;use ieee.std_logic_1164.all;use vamsi.all;entity pg isport(d0,d1,d2,d3,d4,d5,d6,d7,d8:in bit;od:out bit);end pg;architecture str of pg iscomponent xor2port(a,b:in bit;y:out bit);end component;component not1port(a:in bit;y:out bit);end component; signal e0,e1,e2,e3,f0,f1,a0,ev:bit;beginx1:xor2 port map(d0,d1,e0);x2:xor2 port map(d2,d3,e1);x3:xor2 port map(d4,d5,e2);x4:xor2 port map(d6,d7,e3);x5:xor2 port map(f0,f1,a0);x6:xor2 port map(a0,d8,ev);x7:not1 port map(ev,od);end str;


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SIMULATION OUTPUT:

RESULT: 9 bit Priority encoder is simulated and verified.


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17 BIT PARITY GENERATOR (STRUCTURAL MODEL)

AIM:

Simulation and verification of 17-bit parity generator using structural model.

PROGRAM:

Library ieee;use ieee.std_logic_1164.all;use vamsi.all;entity pg1 isport(d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15,d16:in bit;od:buffer bit;ev:buffer bit);end pg1;architecture str of pg1 iscomponent xor2port(a,b:in bit;y:out bit);end component;component xor2port(a,b:in bit;y:buffer bit);end component;component not1port(a:in bit;y:buffer bit);end component; signal e0,e1,e2,e3,e4,e5,e6,e7,a0,a1,a2,a3,b0,b1,f0:bit;beginx1:xor2 port map(d0,d1,e0);x2:xor2 port map(d2,d3,e1);x3:xor2 port map(d4,d5,e2);x4:xor2 port map(d6,d7,e3);x5:xor2 port map(d8,d9,e4);x6:xor2 port map(d10,d11,e5);x7:xor2 port map(d12,d13,e6);x8:xor2 port map(d14,d15,e7);x9:xor2 port map(e0,e1,a0);x10:xor2 port map(e2,e3,a1);x11:xor2 port map(e4,e5,a2);x12:xor2 port map(e6,e7,a3);x13:xor2 port map(a0,a1,b0);x14:xor2 port map(a2,a3,b1);x15:xor2 port map(b0,b1,f0);x16:xor2 port map(f0,d16,od);x17:not1 port map(od,ev);end str;


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RESULT: 17- bit Priority encoder is simulated and verified


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ALU (ARITHMATIC OPERATIONS)

AIM: simulation and verification of arithmetic operations.

PROGRAM:

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity arithmatic isport(a,b:in std_logic_vector(3 downto 0);q1:out std_logic_vector(4 downto 0);q2:out std_logic_vector(3 downto 0);q3:out std_logic_vector(7 downto 0));end arithmatic;architecture df of arithmatic isbeginq1<=('0'&a)+('0'&b);q2<=a-b;q3<=a*b;end df;


RESULT: ALU is simulated and verified.


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ALU(1’s&2’s COMPLEMENTATION)

AIM: simulation and verification of 1’s 2’s complement arithmetic operations.

PROGRAM:

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity complement isport(a:in std_logic_vector(4 downto 0);c2:out std_logic_vector(4 downto 0));end complement;architecture beh of complement issignal c1:std_logic_vector(4 downto 0);begin c1<=(not a);c2<=c1 + 1;end beh;


RESULT:ALU is simulated and verified.


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BCD TO EXCESS-3 CODE CONVERSION

AIM: simulation and verification of BCD to Excess – 3 code.

PROGRAM:

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity bin2ex3 isport(d: in std_logic_vector(3 downto 0);q: out std_logic_vector(3 downto 0);p:out std_logic);end bin2ex3; architecture bin2ex3 of bin2ex3 issignal s:std_logic_vector(4 downto 0);begins<=('0'& d)+"0011";q<=s(3 downto 0);p<=s(4);end bin2ex3;


RESULT: BCD TO EXCESS-3 CODE CONVERSION is simulated and verified


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2 TO 4 DECODER (STRUCTURAL MODEL)

AIM:

Simulation and verification of 2 x 4decoder.

PROGRAM:

Library ieee;use ieee.std_logic_1164.all;use soujanya.all;entity twoto4dec isort(A,B,E:in bit;Z0,Z1,Z2,Z3:out bit);end twoto4dec;architecture struct of twoto4dec iscomponent nand2 is port(a,b,c:in bit;y:out bit);end component;component not1 is port(a:in bit;y:out bit);end component;signal A0,B0:bit;Begin

X1:not1 port map(A,A0);X2:not1 port map(B,B0); X3:nand2 port map(A0,B0,E,Z0);X4:nand2 port map(A0,B,E,Z1);X5:nand2 port map(A,B0,E,Z2);X6:nand2 port map(A,B,E,Z3);

end struct;




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BINARY TO GRAY CODE CONVERSION AIM:

simulation and verification of binary to gray code conversion.

PROGRAM:

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity bi_to_g isport(b:in std_logic_vector(3 downto 0);g:out std_logic_vector(3 downto 0));end bi_to_g;architecture df of bi_to_g isbeging(3)<=b(3);g(2)<=b(3) xor b(2);g(1)<=b(2) xor b(1);g(0)<=b(1) xor B(0);end df;


RESULT: BINARY TO GRAY CODE CONVERSION is simulated and verified.


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GRAY TO BINARY CODE CONVERSION

AIM: simulation and verification of gray to binary code conversion.

PROGRAM:

library ieee;use ieee.std_logic_1164.all;entity gryb2 isport(d: in std_logic_vector(3 downto 0);q: out std_logic_vector(3 downto 0));end gryb2; architecture gryb2 of gryb2 isbeginq(3)<=d(3);q(2)<=d(3) xor d(2);q(1)<=d(1) xor d(2) xor d(3);q(0)<=d(1) xor d(0) xor d(2) xor d(3); end gryb2;


RESULT: GRAY TO BINARY CODE CONVERSION is simulated and verified.


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RS LATCH (BEHAVIOURAL MODEL )

AIM: Simulation and verification of RS-latch using behavioural model

PROGRAM:

Library ieee;use ieee.std_logic_1164.all;entity rslatch isport(r,s,clk:in bit;q,nq:inout bit);end rslatch;architecture beh of rslatch issignal temp:bit;beginb1: block(clk='1')begintemp<=guarded(r nand q);nq<=temp;q<=s nand nq after 5 ns;end block b1;end beh;


RESULT: RS LATCH is simulated and verified.


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T -FLIP FLOP (BEHAVIOURAL MODEL) AIM:

Simulation and verification of T- FLIP FLOP using behavioural model

PROGRAM:

Library ieee;use ieee.std_logic_1164.all;entity tff isport(t,clk:in std_logic;q:inout std_logic:='0');end tff;architecture beh of tff is beginprocess(clk)beginif (clk' event and clk='1') thenif(t='1') thenq<= not (q);elseq<=q;end if;end if; end process;end beh;


RESULT: T FLIP FLOP is simulated and verified.


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D-LATCH (BEHAVIOURAL MODEL WITH DATA ,ENABLE )

AIM: Simulation and verification of D- LATCH using behavioural model

PROGRAM:

Library ieee;use ieee.std_logic_1164.all;entity dl2 isport(d,e:in bit; q:out bit);end dl2;architecture beh of dl2 isbeginprocess(d,e)beginif e='1' thenq<=d;end if;end process;end beh;


RESULT: D- LATCH is simulated and verified.


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POSITIVE LEVEL TRIGGERED D-FLIP FLOP .

AIM: Simulation and verification of positive level triggered D-FLIP FLOP using behavioural model

PROGRAM:

library ieee;entity dff2 isport(d,clk:in bit;q:out bit);end dff2;architecture dff of dff2 isbeginprocess(d,clk)beginif clk='1' thenq<=d;end if;end process;end dff;


RESULT: positive level triggered D-FLIP FLOP using behavioural model is simulated


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POSITIVE EDGE TRIGGERED D-FLIP FLOP.

AIM: Simulation and verification of positive edge triggered D-FLIP FLOP using behavioural model

PROGRAM:

library ieee;entity dff3 isport(d,clk:in bit;q:out bit);end dff3;architecture dfn of dff3 isbeginprocess(clk)beginif clk'event and clk='1' thenq<=d;end if;end process;end dfn;


RESULT: Positive edge Triggered D-FLIP FLOP using behavioural model is simulated and verified.


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D-LATCH WITH GATED ENABLE

AIM: Simulation and verification of D-LATCH with gated enable using behavioural model

PROGRAM:

library ieee;use ieee.std_logic_1164.all;entity dl1 isport(d,en,g:in bit;q:out bit);end dl1;architecture beh of dl1 isbeginprocess(d,en,g)beginif ((en and g)='1') thenq<=d;end if;end process;end beh;


RESULT: D-LATCH with gated enable using behavioural model is simulated and verified.


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JK FLIP FLOP ( BEHAVIOURAL MODEL).

AIM: Simulation and verification of JK FLIP FLOP using behavioural model.

PROGRAM:

Library ieee;use ieee.std_logic_1164.all;entity jkff1 isport (s,r,j,k,clk:in bit;q:inout bit;qn:out bit:='1');end jkff1;architecture jkff of jkff1 isbeginprocess(s,r,clk)beginif r='0' then q<='0' after 10ns;elsif s='0' then q<='1' after 10ns;elsif clk='0' and clk' event thenq<=(j and not q) or (not k and q) after 10ns;end if;end process;qn<=not q;end jkff;


RESULT: JK-FLIP FLOP using behavioural Model is simulated and verified.


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2 TO 4 DECODER

AIM: Simulation and verification of 2 To 4 Decoder using NAND gates.

PROGRAM:

library ieee;use ieee.std_logic_1164.all;entity dec24 isport(a,b,e:in std_logic; z:out std_logic_vector(0 to 3));end dec24;architecture data of dec24 isbeginz(0)<= NOT((not a) AND (not b) AND e);z(1)<= NOT (B AND (not a) and e);z(2)<= NOT(a and (not b) and e);z(3)<= NOT(a and b and e);end data;

SIMULATION OUTPUT:



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3 TO 8 DECODER

AIM: Simulation and verification of 3 to 8 decoder using NAND gates.

PROGRAM:

library ieee;use ieee.std_logic_1164.all;entity dec38 isport(a,b,c,e:in std_logic; z:out std_logic_vector(0 to 7));end dec38;architecture beh of dec38 isbegin

z(0)<=not((not a)and(not b)and (not c)and e); z(1)<=not((not a)and(not b)and c and e);

z(2)<=not((not a)and b and(not c)and e);z(3)<=not((not a) and b and c and e);z(4)<=not(a and(not b)and(not c) and e);z(5)<=not(a and(not b)and c and e);z(6)<=not(a and b and(not c) and e);z(7)<=not(a and b and c and e);end beh;



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2 TO 1 MULTIPLEXER

AIM: Simulation and verification of 2 to1 Multiplexer.

PROGRAM:

library ieee;use ieee.std_logic_1164.all;entity mux21 isport(a,b,s:in bit;f:out bit);end mux21;architecture beh of mux21 isbeginf<= (a and (not s)) or (b and s);end beh;

SIMULATION OUTPUT:

RESULT: 2 to 1 Multiplexer is simulated and verified.


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3 TO 8 DECODER

AIM: Simulation and verification of 3 to 8 Decoder.

PROGRAM:

library ieee;use ieee.std_logic_1164.all;entity dec38 isport(a,b,c,e:in std_logic; z:out std_logic_vector(0 to 7));end dec38;architecture beh of dec38 isbegin

z(0)<=(not a)and(not b)and (not c)and e; z(1)<=(not a)and(not b)and c and e;

z(2)<=(not a)and b and(not c)and e; z(3)<=(not a) and b and c and e;

z(4)<=a and(not b)and(not c) and e;z(5)<=a and(not b)and c and e;z(6)<=a and b and(not c) and e;z(7)<=a and b and c and e;end beh;

SIMULATION OUTPUT:



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3 TO 8 DECODER (STRUCTURAL MODEL)AIM:

Simulation and verification of 3 to 8 Decoder Using Structural Model.

PROGRAM:

library ieee;use ieee.std_logic_1164.all;use dsce04.all;entity dec37 isport(a,b,c,e:in bit; z0,z1,z2,z3,z4,z5,z6,z7:out bit);end dec37;architecture struc of dec37 iscomponent and4 isport(g,h,i,j:in bit; k:out bit);end component;component not1 isport(a:in bit; b:out bit);end component;signal s1,s2,s3:bit;begin

x1:not1 port map(a,s1);x2:not1 port map(b,s2);x3:not1 port map(c,s3);x4:and4 port map(s1,s2,s3,e,z0);x5:and4 port map(s1,s2,c,e,z1);x6:and4 port map(s1,b,s3,e,z2);x7:and4 port map(s1,b,c,e,z3);x8:and4 port map(a,s2,s3,e,z4);x9:and4 port map(a,s2,c,e,z5);x10:and4 port map(a,b,s3,e,z6);x11:and4 port map(a,b,c,e,z7);

end struc;


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SIMULATION OUTPUT:

RESULT: 3 to 8 Decoder Using Structural Model is simulated and verified.


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4 BIT FULL ADDER (STRUCTURAL MODEL)

AIM: Simulation and verification of 4 Bit Full Adder Using Structural Model.

PROGRAM:

Library ieee;use ieee.std_logic_1164.all;use dsce04.all;entity adder1 isport(x0,x1,x2,x3,y0,y1,y2,y3:in std_logic;c:in std_logic;cout:out std_logic;s0,s1,s2,s3:out std_logic);end adder1;architecture str of adder1 issignal c1,c2,c3:std_logic;component fa3port(x,y,c:in std_logic;s,cout:out std_logic);end component ;beginn1:fa3 port map(x0,y0,c,s0,c1);n2:fa3 port map(x1,y1,c1,s1,c2);n3:fa3 port map(x2,y2,c2,s2,c3);n4:fa3 port map(cout=>cout,c=>c3,x=>x3,y=>y3,s=>s3);end str;


RESULT: 4 Bit Full Adder Using Structural Model is simulated and verified.


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4 TO 16 DECODER (STRUCTURAL MODEL)

AIM: Simulation and verification of 4 to 16 Decoder Using Structural Model.

PROGRAM:

library ieee;use ieee.std_logic_1164.all;use dsce04.all;entity dec416 isport(w0,w1,w2,w3,e:in std_logic; q:out std_logic_vector(0 to 15));end dec416;architecture struc of dec416 iscomponent dec24 isport(a,b,e:in std_logic; z0,z1,z2,z3:out std_logic);end component;signal p0,p1,p2,p3: std_logic;begin

x1:dec24 port map(w0,w1,e,p0,p1,p2,p3);x2:dec24 port map(w2,w3,p0,q(0),q(1),q(2),q(3));x3:dec24 port map(w2,w3,p1,q(4),q(5),q(6),q(7));x4:dec24 port map(w2,w3,p2,q(8),q(9),q(10),q(11));x5:dec24 port map(w2,w3,p3,q(12),q(13),q(14),q(15));end struc;


RESULT: 4 to 16 Decoder Using Structural Model is simulated and verified.


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D-FLIP FLOP

AIM: Simulation and verification of D-Flip Flop Using Behavioural Model

PROGRAM:

library ieee;entity dff2 isport(d,clk:in bit;q:out bit);end dff2;architecture dff of dff2 isbeginprocess(d,clk)beginif clk='1' thenq<=d;end if;end process;end dff;


RESULT: D-FLIP FLOP Using Behavioural Model is simulated and verified.


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FUNCTION VERIFICATION (STRUCTURAL MODEL)

AIM:

Design and verification of function F(a,b,c,d) = (0,1,2,4,5,6,8,9,12,13,14) Using Structural ModelPROGRAM:

library ieee;use ieee.std_logic_1164.all;use dsce04.all;entity kmap1 isport(w,x,y,z:in bit; f:out bit);end kmap1;architecture struc of kmap1 iscomponent or2 isport(a,b,c:in bit;d:out bit);end component;component and1 isport(g,h:in bit; i:out bit);end component; component not1 isport(a:in bit; b:out bit);end component;signal s1,s2,s3,s4,s5:bit;begin

x1:not1 port map(w,s1);x2:not1 port map(z,s2);x3:not1 port map(y,s3);x4:and1 port map(s1,s2,s4);x5:and1 port map(s2,x,s5);x6:or2 port map(s3,s4,s5,f);

end struc;


RESULT: Function F(a,b,c,d) = (0,1,2,4,5,6,8,9,12,13,14)Using Structural Model is simulated and verified.


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