Priority EncodersVHDLFollowing is the VHDL code for a 3-bit 1-of-9 Priority Encoder.library ieee;use ieee.std_logic_1164.all;entity priority isport ( sel : in std_logic_vector (7 downto 0);code :out std_logic_vector (2 downto 0));end priority;architecture archi of priority isbegincode <= "000" when sel(0) = '1' else"001" when sel(1) = '1' else"010" when sel(2) = '1' else"011" when sel(3) = '1' else"100" when sel(4) = '1' else"101" when sel(5) = '1' else"110" when sel(6) = '1' else"111" when sel(7) = '1' else"---";end archi;VHDL (One-Hot)Following is the VHDL code for a 3 to 8 line decoder.library ieee;use ieee.std_logic_1164.all;entity dec isport (sel: in std_logic_vector (2 downto 0);res: out std_logic_vector (7 downto 0));end dec;architecture archi of dec isbeginres <="00000001" when sel = "000" else"00000010" when sel = "001" else"00000100" when sel = "010" else"00001000" when sel = "011" else"00010000" when sel = "100" else"00100000" when sel = "101" else"01000000" when sel = "110" else"10000000";end archi;

VHDL (One-Cold)Following is the VHDL code for a 3 to 8 line decoder.library ieee;use ieee.std_logic_1164.all;entity dec isport (sel: in std_logic_vector (2 downto 0);res: out std_logic_vector (7 downto 0));end dec;architecture archi of dec isbegin

res <="11111110" when sel = "000" else"11111101" when sel = "001" else"11111011" when sel = "010" else"11110111" when sel = "011" else"11101111" when sel = "100" else"11011111" when sel = "101" else"10111111" when sel = "110" else"01111111";end archi;IO pins Descriptions[2:0] SelectorresData OutputVHDLFollowing is the VHDL code.library ieee;use ieee.std_logic_1164.all;entity dec isport (sel: in std_logic_vector (2 downto 0);res: out std_logic_vector (7 downto 0));end dec;architecture archi of dec isbeginres <="00000001" when sel = "000" else-- unused decoder output"XXXXXXXX" when sel = "001" else"00000100" when sel = "010" else"00001000" when sel = "011" else"00010000" when sel = "100" else"00100000" when sel = "101" else"01000000" when sel = "110" else"10000000";end archi;IO pins Description

s[2:0] SelectorresData OutputVHDLFollowing is the VHDL code.library ieee;use ieee.std_logic_1164.all;entity dec isport (sel: in std_logic_vector (2 downto 0);res: out std_logic_vector (7 downto 0));end dec;architecture archi of dec isbegin

res <="00000001" when sel = "000" else"00000010" when sel = "001" else"00000100" when sel = "010" else"00001000" when sel = "011" else"00010000" when sel = "100" else"00100000" when sel = "101" else-- 110 and 111 selector values are unused"XXXXXXXX";end archi;VHDL CodeFollowing is the VHDL code for a 4-to-1 1-bit MUX using an If statement.library ieee;use ieee.std_logic_1164.all;entity mux isport (a, b, c, d : in std_logic;s : in std_logic_vector (1 downto 0);o : out std_logic);end mux;architecture archi of mux isbeginprocess (a, b, c, d, s)beginif(s = "00") then o <= a;elsif (s = "01") then o <= b;elsif (s = "10") then o <= c;else o <= d;end if;end process;end archi;

4-to-1 MUX Using CASE StatementThe following table shows pin definitions for a 4-to-1 1-bit MUX using a Case statement.IO PinsDescriptiona, b, c, dData Inputss[1:0]MUX selectoroData OutputVHDL CodeFollowing is the VHDL code for a 4-to-1 1-bit MUX using a Case statement.library ieee;use ieee.std_logic_1164.all;entity mux is

port (a, b, c, d : in std_logic;s : in std_logic_vector (1 downto 0);o : out std_logic);end mux;architecture archi of mux isbeginprocess (a, b, c, d, s)begincase s iswhen "00" => o <= a;when "01" => o <= b;when "10" => o <= c;when others => o <= d;end case;end process;end archi;4-to-1 MUX Using Tristate BuffersThis section shows VHDL and Verilog examples for a 4-to-1 Mux using tristate buffersThe following table shows pin definitions for a 4-to-1 1-bit MUX using tristate buffers.IO PinsDescriptiona, b, c, dData Inputss[3:0]MUX Selector

oData OutputVHDL CodeFollowing is the VHDL code for a 4-to-1 1-bit MUX using tristate buffers.library ieee;use ieee.std_logic_1164.all;entity mux isport (a, b, c, d : in std_logic;s : in std_logic_vector (3 downto 0);o : out std_logic);end mux;architecture archi of mux isbegino <= a when (s(0)='0') else 'Z';o <= b when (s(1)='0') else 'Z';o <= c when (s(2)='0') else 'Z';o <= d when (s(3)='0') else 'Z';end archi;No 4-to-1 MUX

The following example does not generate a 4-to-1 1-bit MUX, but 3-to-1 MUX with 1-bitlatch. The reason is that not all selector values were described in the If statement. It issupposed that for the s=11 case, "O" keeps its old value, and therefore a memory elementis needed.The following table shows pin definitions for a 3-to-1 1-bit MUX with a 1-bit latch.IO PinsDescriptiona, b, c, dData Inputss[1:0]SelectoroData OutputVHDL CodeFollowing is the VHDL code for a 3-to-1 1-bit MUX with a 1-bit latch.library ieee;use ieee.std_logic_1164.all;entity mux isport (a, b, c, d : in std_logic;s : in std_logic_vector (1 downto 0);o : out std_logic);end mux;architecture archi of mux isbeginprocess (a, b, c, d, s)beginif(s = "00") then o <= a;elsif (s = "01") then o <= b;elsif (s = "10") then o <= c;end if;end process;end archi;Logical ShiftersExample 1The following table shows pin descriptions for a logical shifter.IO pinsDescriptionD[7:0] Data InputSELshift distance selectorSO[7:0] Data OutputVHDL

Following is the VHDL code for a logical shifter.library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity lshift isport(DI : in unsigned(7 downto 0);SEL : in unsigned(1 downto 0);SO : out unsigned(7 downto 0));end lshift;architecture archi of lshift isbeginwith SEL selectSO <= DI when "00",DI sll 1 when "01",DI sll 2 when "10",DI sll 3 when others;end archi;

Example 2XST willnot infer a Logical Shifter for this example, as not all of the selector values arepresented.IO pinsDescriptionD[7:0] Data InputSELshift distance selectorSO[7:0] Data OutputVHDLFollowing is the VHDL code.library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity lshift isport(DI : in unsigned(7 downto 0);SEL : in unsigned(1 downto 0);SO : out unsigned(7 downto 0));end lshift;architecture archi of lshift isbeginwith SEL selectSO <= DI when "00",DI sll 1 when "01",DI sll 2 when others;end archi;Example 3

XST willnot infer a Logical Shifter for this example, as the value is not incremented by 1for each consequent binary value of the selector.IO pinsDescriptionD[7:0] Data InputSELshift distance selectorSO[7:0] Data Output

VHDLFollowing is the VHDL code.library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity lshift isport(DI : in unsigned(7 downto 0);SEL : in unsigned(1 downto 0);SO : out unsigned(7 downto 0));end lshift;architecture archi of lshift isbeginwith SEL selectSO <= DI when "00",DI sll 1 when "01",DI sll 3 when "10",DI sll 2 when others;end archi;Arithmetic OperationsXST supports the following arithmetic operations:•Adders with:o Carry Ino Carry Outo Carry In/Out•Subtractors•Adders/subtractors•Comparators (=, /=,<, <=, >, >=)•Multipliers•Dividers

Adders, Subtractors, Comparators and Multipliers are supported for signed and unsignedoperations.Please refer to the "Signed/Unsigned Support" section of this chapter for moreinformation on the signed/unsigned operations support in VHDL.Moreover, XST performs resource sharing for adders, subtractors, adders/subtractors andmultipliers.Adders, Subtractors, Adders/SubtractorsThis section provides HDL examples of adders and subtractorsUnsigned 8-bit AdderThis subsection contains a VHDL and Verilog description of an unsigned 8-bit AdderThe following table shows pin descriptions for an unsigned 8-bit Adder.IO pinsDescriptionA[7:0], B[7:0]Add OperandsSUM[7:0]Add ResultVHDLFollowing is the VHDL code for an unsigned 8-bit Adder.library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder isport(A,B : in std_logic_vector(7 downto 0);SUM : out std_logic_vector(7 downto 0));end adder;architecture archi of adder isbeginSUM <= A + B;end archi;Unsigned 8-bit Adder with Carry InThis section contains VHDL and Verilog descriptions of an unsigned 8-bit adder withCarry In.The following table shows pin descriptions for an unsigned 8-bit adder with carry.IO pinsDescriptionA[7:0], B[7:0]Add OperandsCI

Carry InSUM[7:0]Add ResultVHDL

Following is the VHDL code for an unsigned 8-bit adder with carry in.library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder isport(A,B : in std_logic_vector(7 downto 0);CI: in std_logic;SUM : out std_logic_vector(7 downto 0));end adder;architecture archi of adder isbeginSUM <= A + B + CI;end archi;Unsigned 8-bit Adder with Carry OutThe following table shows pin descriptions for an unsigned 8-bit adder with carryIO pinsDescriptionA[7:0], B[7:0]Add OperandsSUM[7:0]Add ResultCOCarry OutVHDLFollowing is the VHDL code for an unsigned 8-bit adder with carry out.library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity adder isport(A,B : in std_logic_vector(7 downto 0);SUM : out std_logic_vector(7 downto 0);CO: out std_logic);end adder;architecture archi of adder issignal tmp: std_logic_vector(8 downto 0);begintmp <= conv_std_logic_vector((conv_integer(A) +conv_integer(B)),9);

SUM <= tmp(7 downto 0);CO<= tmp(8);end archi;

In the preceding example, two arithmetic packages are used:•std_logic_arith. This package contains the integer to std_logic conversionfunction, that is, conv_std_logic_vector.•std_logic_unsigned. This package contains the unsigned "+" operation.Unsigned 8-bit Adder with Carry In and Carry OutThis section contains VHDL and Verilog code for an unsigned 8-bit adder with Carry Inand Carry Out.The following table shows pin descriptions for an unsigned 8-bit adder with carry.IO pinsDescriptionA[7:0], B[7:0]Add OperandsCICarry InSUM[7:0]Add ResultCOCarry OutVHDLFollowing is the VHDL code for an unsigned 8-bit adder with carry in and carry out.library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity adder isport(A,B : in std_logic_vector(7 downto 0);CI: in std_logic;SUM : out std_logic_vector(7 downto 0);CO: out std_logic);end adder;architecture archi of adder issignal tmp: std_logic_vector(8 downto 0);begintmp <= conv_std_logic_vector((conv_integer(A) +

conv_integer(B) +conv_integer(CI)),9);SUM <= tmp(7 downto 0);CO<= tmp(8);end archi;Simple Signed 8-bit AdderThe following table shows pin descriptions for a simple signed 8-bit adder.IO pinsDescriptionA[7:0], B[7:0]Add OperandsSUM[7:0]Add ResultVHDLFollowing is the VHDL code for a simple signed 8-bit adder.library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity adder isport(A,B : in std_logic_vector(7 downto 0);SUM : out std_logic_vector(7 downto 0));end adder;architecture archi of adder isbeginSUM <= A + B;end archi;Unsigned 8-bit SubtractorThe following table shows pin descriptions for an unsigned 8-bit subtractor.IO pinsDescriptionA[7:0], B[7:0]Sub OperandsRES[7:0]Sub ResultVHDLFollowing is the VHDL code for an unsigned 8-bit subtractor.library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity subtr isport(A,B : in std_logic_vector(7 downto 0);RES : out std_logic_vector(7 downto 0));end subtr;architecture archi of subtr is

beginRES <= A - B;end archi;Unsigned 8-bit Adder/SubtractorThe following table shows pin descriptions for an unsigned 8-bit adder/subtractor.IO pinsDescriptionA[7:0], B[7:0]Add/Sub OperandsOPERAdd/Sub SelectSUM[7:0]Add/Sub ResultVHDLFollowing is the VHDL code for an unsigned 8-bit adder/subtractor.library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity addsub isport(A,B : in std_logic_vector(7 downto 0);OPER: in std_logic;RES : out std_logic_vector(7 downto 0));end addsub;architecture archi of addsub isbeginRES <= A + B when OPER='0'else A - B;end archi;endmoduleComparators (=, /=,<, <=, >, >=)This section contains a VHDL and Verilog description for an unsigned 8-bit greater orequal comparator.Unsigned 8-bit Greater or Equal ComparatorThe following table shows pin descriptions for a comparator.IO pinsDescriptionA[7:0], B[7:0]Add/Sub Operands

CMPComparison ResultVHDL

Following is the VHDL code for an unsigned 8-bit greater or equal comparator.library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity compar isport(A,B : in std_logic_vector(7 downto 0);CMP : out std_logic);end compar;architecture archi of compar isbeginCMP <= '1' when A >= Belse '0';end archi;MultipliersWhen implementing a multiplier, the size of the resulting signal is equal to the sum of 2operand lengths. If you multiply A (8-bit signal) by B (4-bit signal), then the size of theresult must be declared as a 12-bit signal.Unsigned 8x4-bit MultiplierThis section contains VHDL and Verilog descriptions of an unsigned 8x4-bit multiplier.The following table shows pin descriptions for an unsigned 8x4-bit multiplier.IO pinsDescriptionA[7:0], B[3:0]MULT OperandsRES[7:0]MULT ResultVHDLFollowing is the VHDL code for an unsigned 8x4-bit multiplier.library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mult isport(A : in std_logic_vector(7 downto 0);B : in std_logic_vector(3 downto 0);RES : out std_logic_vector(11 downto 0));end mult;architecture archi of mult isbeginRES <= A * B;end archi;Dividers

Divisions are only supported, when the divisor is a constant and is a power of 2. In thatcase, the operator is implemented as a shifter; otherwise, an error message will be issuedby XST.Division By Constant 2This section contains VHDL and Verilog descriptions of a Division By Constant 2divider.The following table shows pin descriptions for a Division By Constant 2 divider.IO pinsDescriptionDI[7:0] DIV OperandsDO[7:0] DIV ResultVHDLFollowing is the VHDL code for a Division By Constant 2 divider.library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity divider isport(DI : in unsigned(7 downto 0);DO : out unsigned(7 downto 0));end divider;architecture archi of divider isbeginDO <= DI / 2;end archi;Resource SharingThe goal of resource sharing (also known as folding) is to minimize the number ofoperators and the subsequent logic in the synthesized design. This optimization is based

on the principle that two similar arithmetic resources may be implemented as one singlearithmetic operator if they are never used at the same time. XST performs both resourcesharing and, if required, reduces of the number of multiplexers that are created in theprocess.XST supports resource sharing for adders, subtractors, adders/subtractors and multipliers.Related ConstraintThe related constraint isresource_sharing.ExampleFor the following VHDL/Verilog example, XST will give the following solution:

The following table shows pin descriptions for the example.IO pinsDescriptionA[7:0], B[7:0], B[7:0]DIV OperandsOPEROperation SelectorRES[7:0]Data OutputVHDLFollowing is the VHDL example for resource sharing.library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity addsub isport(A,B,C : in std_logic_vector(7 downto 0);OPER: in std_logic;RES : out std_logic_vector(7 downto 0));end addsub;architecture archi of addsub isbeginRES <= A + B when OPER='0'else A - C;end archi;adderLIBRARY ieee ;USEieee.std_logic_1164.all ;USEieee.std_logic_arith.all ;ENTITY adder ISPORT(in1:INstd_logic_vector(15 DOWNTO 0) ;in2:INstd_logic_vector(15 DOWNTO 0) ;c_out:OUTstd_logic ;sum:OUTstd_logic_vector(15 DOWNTO 0)) ;END adder ;ARCHITECTURE synthesizable OF adder ISBEGINPROCESS(in1, in2)

VARIABLEtmp_in1:signed(16 DOWNTO 0) ;VARIABLEtmp_in2:signed(16 DOWNTO 0) ;VARIABLEoutput:signed(16 DOWNTO 0) ;VARIABLEc:std_logic ;BEGINtmp_in1 := signed('0' & in1) ;tmp_in2 := signed('0' & in2) ;output := tmp_in1 + tmp_in2 ;IF (output(16) = '1') THENc := '1' ;ELSE c := '0' ;END IF ;sum <= std_logic_vector(output(15 DOWNTO 0)) ;c_out <= c ;END PROCESS ;END synthesizable ;--counterLIBRARY ieee ;USEieee.std_logic_1164.all ;USEieee.std_logic_arith.all ;ENTITY counter ISPORT(clk:INstd_logic ;input:INstd_logic_vector(11 DOWNTO 0) ;output: OUTstd_logic_vector(11 DOWNTO 0) ;ld:INstd_logic ;inc:INstd_logic ;clr:INstd_logic

) ;END counter ;ARCHITECTURE behavioral OF counter ISBEGINgeneric_counter: PROCESS(clk, input, ld, inc, clr)VARIABLEtmpvar:unsigned(11 DOWNTO 0) ;BEGIN IF (rising_edge(clk)) THENIF (clr = '1') THENtmpvar := (OTHERS => '0') ;ELSIF (ld = '1') THENtmpvar := unsigned(input) ;ELSIF (inc = '1') THENtmpvar := tmpvar + "000000000001" ;END IF ;output <= std_logic_vector(tmpvar) ;END IF ;END PROCESS ;END behavioral ;---- Design a 2-bit count-down counter--LIBRARY ieee ;USEieee.std_logic_1164.all ;USEieee.std_logic_arith.all ;USEieee.std_logic_signed.all ;USEieee.std_logic_unsigned.all ;ENTITY down_counter ISPORT(SIGNAL x:INstd_logic ;SIGNALcount :OUTstd_logic_vector(1 DOWNTO 0) ;SIGNAL reset:INstd_logic ;SIGNAL clk:INstd_logic) ;END down_counter ;ARCHITECTURE arch1 OF down_counter ISBEGINPROCESS(clk, x, reset)VARIABLEtmp_cnt:unsigned(1 DOWNTO 0) ;

BEGINIF (reset = '1') THENtmp_cnt := "00" ;ELSIF rising_edge(clk) THENIF (x = '1') THENtmp_cnt := tmp_cnt - "01" ;END IF ;END IF ;count <= std_logic_vector(tmp_cnt) ;END PROCESS ;END arch1 ;---- 8 to 3 priority encoder--LIBRARYieee ;USEieee.std_logic_1164.all ;ENTITY enc8to3 ISPORT(SIGNAL input:INstd_logic_vector(7 DOWNTO 0) ;SIGNAL output:OUTstd_logic_vector(2 DOWNTO 0)) ;END enc8to3 ;---- Here is a case where we really need the WHEN - ELSE-- I don't think the WITH select will work because-- we want a priority encoder--ARCHITECTURE arch1 OF enc8to3 ISBEGINoutput <= "111" WHEN (input(7) = '1') ELSE"110" WHEN (input(6) = '1') ELSE"101" WHEN (input(5) = '1') ELSE"100" WHEN (input(4) = '1') ELSE"011" WHEN (input(3) = '1') ELSE"010" WHEN (input(2) = '1') ELSE"001" WHEN (input(1) = '1') ELSE"000" ;END arch1 ;-- fa.vhd---- A 1-bit full-adder---- George L. Engel, SIUE--LIBRARY ieee ;USEieee.std_logic_1164.all ;

ENTITY fa ISPORT( a, b : in std_logic ;cin: in std_logic ;cout : out std_logic ;sum: out std_logic) ;END fa ;ARCHITECTURE arch1 OF fa ISBEGINsum<= (a XOR b) XOR cin ;cout <= (a AND b) OR ((a OR b) AND cin) ;END arch1 ;--REGISTERLIBRARY ieee ;USEieee.std_logic_1164.all ;ENTITY reg ISPORT(clk:INstd_logic ;input:INstd_logic_vector(15 DOWNTO 0) ;output: OUTstd_logic_vector(15 DOWNTO 0) ;ld:INstd_logic) ;END reg ;ARCHITECTURE behavioral OF reg ISBEGINgeneric_register: PROCESS(clk, input, ld)BEGIN IF (rising_edge(clk)) THENIF (ld = '1') THENoutput <= input ;END IF ;END IF ;END PROCESS ;END behavioral ;----------------------------------------------- D Flip-Flop (ESD book Chapter 2.3.1)-- by Weijun Zhang, 04/2001---- Flip-flop is the basic component in-- sequential logic design-- we assign input signal to the output-- at the clock rising edge

---------------------------------------------library ieee ;use ieee.std_logic_1164.all;use work.all;---------------------------------------------entity dff isport(data_in:in std_logic;clock:in std_logic;data_out:out std_logic);end dff;----------------------------------------------architecture behv of dff isbeginprocess(data_in, clock)begin-- clock rising edgeif (clock='1' and clock'event) thendata_out <= data_in;end if;end process;end behv;---------------------------------------------------------------------------------------------- JK Flip-Flop with reset-- (ESD book Chapter 2.3.1)-- by Weijun Zhang, 04/2001---- the description of JK Flip-Flop is based-- on functional truth table-- concurrent statement and signal assignment-- are using in this example----------------------------------------------library ieee;use ieee.std_logic_1164.all;----------------------------------------------entity JK_FF isport (clock:in std_logic;J, K:in std_logic;reset:in std_logic;Q, Qbar:

out std_logic);end JK_FF;-----------------------------------------------architecture behv of JK_FF is-- define the useful signals heresignal state: std_logic;signal input: std_logic_vector(1 downto 0);begin-- combine inputs into vectorinput <= J & K;p: process(clock, reset) isbeginif (reset='1') thenstate <= '0';elsif (rising_edge(clock)) then-- compare to the truth tablecase (input) iswhen "11" =>state <= not state;when "10" =>state <= '1';when "01" =>state <= '0';when others =>null;end case;end if;end process;-- concurrent statementsQ <= state;Qbar <= not state;end behv;------------------------------------------------------------------------------------------------------ n-bit Register (ESD book figure 2.6)-- by Weijun Zhang, 04/2001---- KEY WORD: concurrent, generic and range---------------------------------------------------library ieee ;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;---------------------------------------------------entity reg isgeneric(n: natural :=2);port(I:

in std_logic_vector(n-1 downto 0);clock:in std_logic;load:in std_logic;clear:in std_logic;Q:out std_logic_vector(n-1 downto 0));end reg;----------------------------------------------------architecture behv of reg issignal Q_tmp: std_logic_vector(n-1 downto 0);beginprocess(I, clock, load, clear)beginif clear = '0' then-- use 'range in signal assigmentQ_tmp <= (Q_tmp'range => '0');elsif (clock='1' and clock'event) thenif load = '1' thenQ_tmp <= I;end if;end if;end process;-- concurrent statementQ <= Q_tmp;end behv;-------------------------------------------------------------------------------------------------------- 3-bit Shift-Register/Shifter-- (ESD book figure 2.6)-- by Weijun Zhang, 04/2001---- reset is ignored according to the figure---------------------------------------------------library ieee ;use ieee.std_logic_1164.all;---------------------------------------------------entity shift_reg isport(I:in std_logic;clock:in std_logic;shift:in std_logic;Q:out std_logic);end shift_reg;

architecture behv of shift_reg is-- initialize the declared signalsignal S: std_logic_vector(2 downto 0):="111";beginprocess(I, clock, shift, S)begin-- everything happens upon the clock changingif clock'event and clock='1' thenif shift = '1' thenS <= I & S(2 downto 1);end if;end if;end process;-- concurrent assignmentQ <= S(0);end behv;---------------------------------------------------------------------------------------------------------- VHDL code for n-bit counter (ESD figure 2.6)-- by Weijun Zhang, 04/2001---- this is the behavior description of n-bit counter-- another way can be used is FSM model.----------------------------------------------------library ieee ;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;----------------------------------------------------entity counter isgeneric(n: natural :=2);port(clock:in std_logic;clear:in std_logic;count:in std_logic;Q:out std_logic_vector(n-1 downto 0));end counter;----------------------------------------------------architecture behv of counter issignal Pre_Q: std_logic_vector(n-1 downto 0);begin-- behavior describe the counterprocess(clock, count, clear)beginif clear = '1' thenPre_Q <= Pre_Q - Pre_Q;elsif (clock='1' and clock'event) thenif count = '1' thenPre_Q <= Pre_Q + 1;end if;

end if;end process;-- concurrent assignment statementQ <= Pre_Q;end behv;-----------------------------------------------------

VHDL Code for Shift registers8-bit Shift-Left Register with Positive-Edge Clock, Serial In, and SerialOutNote For this example, XST will infer SRL16.The following table shows pin definitions for an 8-bit shift-left register with a positive-edge clock, serial in, and serial out.IO Pins DescriptionCPositive-Edge ClockSISerial InSOSerial OutputVHDL CodeFollowing is the VHDL code for an 8-bit shift-left register with a positive-edge clock,serial in, and serial out.library ieee;use ieee.std_logic_1164.all;entity shift isport(C, SI : instd_logic;SO : out std_logic);end shift;architecture archi of shift issignal tmp: std_logic_vector(7 downto 0);beginprocess (C)beginif (C'event and C='1') thenfor i in 0 to 6 looptmp(i+1) <= tmp(i);end loop;tmp(0) <= SI;end if;end process;SO <= tmp(7);end archi;

8-bit Shift-Left Register with Negative-Edge Clock, Clock Enable, SerialIn, and Serial OutNote For this example, XST will infer SRL16E_1.The following table shows pin definitions for an 8-bit shift-left register with a negative-edge clock, clock enable, serial in, and serial out.IO Pins DescriptionCNegative-Edge ClockSISerial InCEClock Enable (active High)SOSerial OutputVHDL CodeFollowing is the VHDL code for an 8-bit shift-left register with a negative-edge clock,clock enable, serial in, and serial out.library ieee;use ieee.std_logic_1164.all;entity shift isport(C, SI, CE : instd_logic;SO : out std_logic);end shift;architecture archi of shift issignal tmp: std_logic_vector(7 downto 0);beginprocess (C)beginif (C'event and C='0') thenif (CE='1') thenfor i in 0 to 6 looptmp(i+1) <= tmp(i);end loop;tmp(0) <= SI;end if;end if;end process;SO <= tmp(7);end archi;

8-bit Shift-Left Register with Positive-Edge Clock, Asynchronous Clear,Serial In, and Serial OutNote Because this example includes an asynchronous clear, XST will not infer SRL16.The following table shows pin definitions for an 8-bit shift-left register with a positive-edge clock, asynchronous clear, serial in, and serial out.IO Pins DescriptionCPositive-Edge ClockSISerial InCLRAsynchronous Clear (active High)SOSerial OutputVHDL CodeFollowing is the VHDL code for an 8-bit shift-left register with a positive-edge clock,asynchronous clear, serial in, and serial out.library ieee;use ieee.std_logic_1164.all;entity shift isport(C, SI, CLR : in std_logic;SO : out std_logic);end shift;architecture archi of shift issignal tmp: std_logic_vector(7 downto 0);beginprocess (C, CLR)beginif (CLR='1') thentmp <= (others => '0');elsif (C'event and C='1') thentmp <= tmp(6 downto 0) & SI;end if;end process;SO <= tmp(7);end archi;8-bit Shift-Left Register with Positive-Edge Clock, Synchronous Set, SerialIn, and Serial OutNote Because this example includes an asynchronous clear XST will not infer SRL16.

The following table shows pin definitions for an 8-bit shift-left register with a positive-edge clock, synchronous set, serial in, and serial out.IO Pins DescriptionCPositive-Edge ClockSISerial InSsynchronous Set (active High)SOSerial OutputVHDL CodeFollowing is the VHDL code for an 8-bit shift-left register with a positive-edge clock,synchronous set, serial in, and serial out.library ieee;use ieee.std_logic_1164.all;entity shift isport(C, SI, S : instd_logic;SO : out std_logic);end shift;architecture archi of shift issignal tmp: std_logic_vector(7 downto 0);beginprocess (C, S)beginif (C'event and C='1') thenif (S='1') thentmp <= (others => '1');elsetmp <= tmp(6 downto 0) & SI;end if;end if;end process;SO <= tmp(7);end archi;8-bit Shift-Left Register with Positive-Edge Clock, Serial In, and ParallelOutNote For this example XST will infer SRL16.

The following table shows pin definitions for an 8-bit shift-left register with a positive-edge clock, serial in, and serial out.IO Pins

DescriptionCPositive-Edge ClockSISerial InPO[7:0] Parallel OutputVHDL CodeFollowing is the VHDL code for an 8-bit shift-left register with a positive-edge clock,serial in, and serial out.library ieee;use ieee.std_logic_1164.all;entity shift isport(C, SI : instd_logic;PO : out std_logic_vector(7 downto 0));end shift;architecture archi of shift issignal tmp: std_logic_vector(7 downto 0);beginprocess (C)beginif (C'event and C='1') thentmp <= tmp(6 downto 0)& SI;end if;end process;PO <= tmp;end archi;8-bit Shift-Left Register with Positive-Edge Clock, Asynchronous ParallelLoad, Serial In, and Serial OutNote For this example XST will infer SRL16.The following table shows pin definitions for an 8-bit shift-left register with a positive-edge clock, asynchronous parallel load, serial in, and serial out.IO PinsDescriptionCPositive-Edge Clock

SISerial InALOADAsynchronous Parallel Load (active High)D[7:0]Data InputSO

Serial OutputVHDL CodeFollowing is VHDL code for an 8-bit shift-left register with a positive-edge clock,asynchronous parallel load, serial in, and serial out.library ieee;use ieee.std_logic_1164.all;entity shift isport(C, SI, ALOAD : in std_logic;D: in std_logic_vector(7 downto 0);SO: out std_logic);end shift;architecture archi of shift issignal tmp: std_logic_vector(7 downto 0);beginprocess (C, ALOAD, D)beginif (ALOAD='1') thentmp <= D;elsif (C'event and C='1') thentmp <= tmp(6 downto 0) & SI;end if;end process;SO <= tmp(7);end archi;8-bit Shift-Left Register with Positive-Edge Clock, Synchronous ParallelLoad, Serial In, and Serial OutNote For this example XST will not infer SRL16.The following table shows pin definitions for an 8-bit shift-left register with a positive-edge clock, synchronous parallel load, serial in, and serial out.IO PinsDescriptionCPositive-Edge ClockSISerial InSLOADSynchronous Parallel Load (active High)D[7:0]Data InputSOSerial OutputVHDL Code

Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock,synchronous parallel load, serial in, and serial out.library ieee;use ieee.std_logic_1164.all;entity shift isport(C, SI, SLOAD : in std_logic;D: in std_logic_vector(7 downto 0);SO : out std_logic);end shift;architecture archi of shift issignal tmp: std_logic_vector(7 downto 0);beginprocess (C)beginif (C'event and C='1') thenif (SLOAD='1') thentmp <= D;elsetmp <= tmp(6 downto 0) & SI;end if;end if;end process;SO <= tmp(7);end archi;8-bit Shift-Left/Shift-Right Register with Positive-Edge Clock, Serial In,and Parallel OutNote For this example XST will not infer SRL16.The following table shows pin definitions for an 8-bit shift-left/shift-right register with apositive-edge clock, serial in, and serial out.IO PinsDescriptionCPositive-Edge ClockSISerial InLEFT_RIGHTLeft/right shift mode selector

PO[7:0]Parallel OutputVHDL CodeFollowing is the VHDL code for an 8-bit shift-left/shift-right register with a positive-edgeclock, serial in, and serial out.

library ieee;use ieee.std_logic_1164.all;entity shift isport(C, SI, LEFT_RIGHT : in std_logic;PO : out std_logic_vector(7 downto 0));end shift;architecture archi of shift issignal tmp: std_logic_vector(7 downto 0);beginprocess (C)beginif (C'event and C='1') thenif (LEFT_RIGHT='0') thentmp <= tmp(6 downto 0) & SI;elsetmp <= SI & tmp(7 downto 1);end if;end if;end process;PO <= tmp;end archi;

Counters4-bit Unsigned Up Counter with Asynchronous ClearThe following table shows pin definitions for a 4-bit unsigned up counter withasynchronous clear.IO Pins DescriptionCPositive-Edge ClockCLRAsynchronous Clear (active High)Q[3:0] Data OutputVHDL CodeFollowing is VHDL code for a 4-bit unsigned up counter with asynchronous clear.library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter isport(C, CLR : instd_logic;Q : out std_logic_vector(3 downto 0));end counter;architecture archi of counter issignal tmp: std_logic_vector(3 downto 0);beginprocess (C, CLR)begin

if (CLR='1') thentmp <= "0000";elsif (C'event and C='1') thentmp <= tmp + 1;end if;end process;Q <= tmp;end archi;4-bit Unsigned Down Counter with Synchronous Set

The following table shows pin definitions for a 4-bit unsigned down counter withsynchronous set.IO Pins DescriptionCPositive-Edge ClockSSynchronous Set (active High)Q[3:0] Data OutputVHDL CodeFollowing is the VHDL code for a 4-bit unsigned down counter with synchronous set.library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter isport(C, S : instd_logic;Q : out std_logic_vector(3 downto 0));end counter;architecture archi of counter issignal tmp: std_logic_vector(3 downto 0);beginprocess (C)beginif (C'event and C='1') thenif (S='1') thentmp <= "1111";elsetmp <= tmp - 1;end if;end if;end process;Q <= tmp;end archi;4-bit Unsigned Up Counter with Asynchronous Load from Primary Input

The following table shows pin definitions for a 4-bit unsigned up counter withasynchronous load from primary input.IO PinsDescriptionCPositive-Edge Clock

ALOADAsynchronous Load (active High)D[3:0]Data InputQ[3:0]Data OutputVHDL CodeFollowing is the VHDL code for a 4-bit unsigned up counter with asynchronous loadfrom primary input.library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter isport(C, ALOAD : instd_logic;D : in std_logic_vector(3 downto 0);Q : out std_logic_vector(3 downto 0));end counter;architecture archi of counter issignal tmp: std_logic_vector(3 downto 0);beginprocess (C, ALOAD, D)beginif (ALOAD='1') thentmp <= D;elsif (C'event and C='1') thentmp <= tmp + 1;end if;end process;Q <= tmp;end archi;4-bit Unsigned Up Counter with Synchronous Load with a ConstantThe following table shows pin definitions for a 4-bit unsigned up counter withsynchronous load with a constant.IO PinsDescriptionC

Positive-Edge ClockSLOADSynchronous Load (active High)Q[3:0]Data OutputVHDL CodeFollowing is the VHDL code for a 4-bit unsigned up counter with synchronous load witha constant.library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter isport(C, SLOAD : instd_logic;Q : out std_logic_vector(3 downto 0));end counter;architecture archi of counter issignal tmp: std_logic_vector(3 downto 0);beginprocess (C)beginif (C'event and C='1') thenif (SLOAD='1') thentmp <= "1010";elsetmp <= tmp + 1;end if;end if;end process;Q <= tmp;end archi;4-bit Unsigned Up Counter with Asynchronous Clear and Clock EnableThe following table shows pin definitions for a 4-bit unsigned up counter withasynchronous clear and clock enable.IO Pins DescriptionCPositive-Edge ClockCLRAsynchronous Clear (active High)CEClock EnableQ[3:0] Data Output

VHDL Code

Following is the VHDL code for a 4-bit unsigned up counter with asynchronous clear andclock enable.library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter isport(C, CLR, CE : in std_logic;Q : out std_logic_vector(3 downto 0));end counter;architecture archi of counter issignal tmp: std_logic_vector(3 downto 0);beginprocess (C, CLR)beginif (CLR='1') thentmp <= "0000";elsif (C'event and C='1') thenif (CE='1') thentmp <= tmp + 1;end if;end if;end process;Q <= tmp;end archi;4-bit Unsigned Up/Down counter with Asynchronous ClearThe following table shows pin definitions for a 4-bit unsigned up/down counter withasynchronous clear.IO PinsDescriptionCPositive-Edge ClockCLRAsynchronous Clear (active High)UP_DOWNup/down count mode selectorQ[3:0]Data Output

VHDL CodeFollowing is the VHDL code for a 4-bit unsigned up/down counter with asynchronousclear.library ieee;use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;entity counter isport(C, CLR, UP_DOWN : in std_logic;Q : out std_logic_vector(3 downto 0));end counter;architecture archi of counter issignal tmp: std_logic_vector(3 downto 0);beginprocess (C, CLR)beginif (CLR='1') thentmp <= "0000";elsif (C'event and C='1') thenif (UP_DOWN='1') thentmp <= tmp + 1;elsetmp <= tmp - 1;end if;end if;end process;Q <= tmp;end archi;4-bit Signed Up Counter with Asynchronous ResetThe following table shows pin definitions for a 4-bit signed up counter withasynchronous reset.IO Pins DescriptionCPositive-Edge ClockCLRAsynchronous Clear (active High)Q[3:0] Data OutputVHDL CodeFollowing is the VHDL code for a 4-bit signed up counter with asynchronous reset.library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity counter isport(C, CLR : instd_logic;Q : out std_logic_vector(3 downto 0));end counter;architecture archi of counter issignal tmp: std_logic_vector(3 downto 0);beginprocess (C, CLR)begin

if (CLR='1') thentmp <= "0000";elsif (C'event and C='1')thentmp <= tmp + 1;end if;end process;Q <= tmp;end archi;RegistersFlip-flop with Positive-Edge ClockThe following figure shows a flip-flop with positive-edge clock.The following table shows pin definitions for a flip-flop with positive edge clock.IO Pins DescriptionDData InputCPositive Edge ClockQData OutputVHDL CodeFollowing is the equivalent VHDL code sample for the flip-flop with a positive-edgeclock.library ieee;use ieee.std_logic_1164.all;entity flop isport(C, D : in std_logic;Q : out std_logic);end flop;architecture archi of flop isbeginprocess (C)beginif (C'event and C='1') thenQ <= D;end if;end process;end archi;

Note When using VHDL, for a positive-edge clock instead of usingif (C'event and C='1') thenyou can also use

if (rising_edge(C)) thenand for a negative-edge clock you can useif (falling_edge(C)) thenFlip-flop with Negative-Edge Clock and Asynchronous ClearThe following figure shows a flip-flop with negative-edge clock and asynchronous clear.The following table shows pin definitions for a flip-flop with negative edge clock andasynchronous clear.IO Pins DescriptionDData InputCNegative-Edge ClockCLRAsynchronous Clear (active High)QData OutputVHDL CodeFollowing is the equivalent VHDL code for a flip-flop with a negative-edge clock andasynchronous clear.library ieee;

use ieee.std_logic_1164.all;entity flop isport(C, D, CLR: in std_logic;Q: out std_logic);end flop;architecture archi of flop isbeginprocess (C, CLR)beginif (CLR = '1')thenQ <= '0';elsif (C'event and C='0')thenQ <= D;end if;end process;end archi;Flip-flop with Positive-Edge Clock and Synchronous SetThe following figure shows a flip-flop with positive-edge clock and synchronous set.

The following table shows pin definitions for a flip-flop with positive edge clock andsynchronous set.IO Pins DescriptionDData InputCPositive-Edge ClockSSynchronous Set (active High)QData OutputVHDL CodeFollowing is the equivalent VHDL code for the flip-flop with a positive-edge clock andsynchronous set.library ieee;use ieee.std_logic_1164.all;entity flop isport(C, D, S: instd_logic;Q: out std_logic);end flop;architecture archi of flop isbeginprocess (C)beginif (C'event and C='1') thenif (S='1') thenQ <= '1';elseQ <= D;end if;end if;end process;end archi;Flip-flop with Positive-Edge Clock and Clock EnableThe following figure shows a flip-flop with positive-edge clock and clock enable.The following table shows pin definitions for a flip-flop with positive edge clock andclock enable.IO Pins DescriptionDData Input

CPositive-Edge Clock

CEClock Enable (active High)QData OutputVHDL CodeFollowing is the equivalent VHDL code for the flip-flop with a positive-edge clock andclock Enable.library ieee;use ieee.std_logic_1164.all;entity flop isport(C, D, CE: instd_logic;Q: out std_logic);end flop;architecture archi of flop isbeginprocess (C)beginif (C'event and C='1') thenif (CE='1') thenQ <= D;end if;end if;end process;end archi;4-bit Register with Positive-Edge Clock, Asynchronous Set and ClockEnableThe following figure shows a 4-bit register with positive-edge clock, asynchronous setand clock enable.The following table shows pin definitions for a 4-bit register with positive-edge clock,asynchronous set and clock enable.

IO Pins DescriptionD[3:0] Data InputCPositive-Edge ClockPREAsynchronous Set (active High)

CEClock Enable (active High)Q[3:0] Data OutputVHDL CodeFollowing is the equivalent VHDL code for a 4-bit register with a positive-edge clock,asynchronous set and clock enable.library ieee;use ieee.std_logic_1164.all;entity flop isport(C, CE, PRE : in std_logic;D : instd_logic_vector (3 downto 0);Q : out std_logic_vector (3 downto 0));end flop;architecture archi of flop isbeginprocess (C, PRE)beginif (PRE='1') thenQ <= "1111";elsif (C'event and C='1')thenif (CE='1') thenQ <= D;end if;end if;end process;end archi;Latch with Positive GateThe following figure shows a latch with positive gate.The following table shows pin definitions for a latch with positive gate.IO Pins DescriptionDData InputGPositive GateQData OutputVHDL CodeFollowing is the equivalent VHDL code for a latch with a positive gate.library ieee;use ieee.std_logic_1164.all;entity latch isport(G, D : instd_logic;Q

: out std_logic);end latch;architecture archi of latch isbeginprocess (G, D)beginif (G='1') thenQ <= D;end if;end process;end archi;

3-Bit 1-of-9 Priority EncoderNote For this example XST may infer a priority encoder. You must use thepriority_extract constraint with a value force to force its inference.Related ConstraintA related constraint ispriority_ext ract.VHDLFollowing is the VHDL code for a 3-bit 1-of-9 Priority Encoder.library ieee;use ieee.std_logic_1164.all;entity priority isport ( sel : in std_logic_vector (7 downto 0);code :out std_logic_vector (2 downto 0));end priority;architecture archi of priority isbegincode <= "000" when sel(0) = '1' else"001" when sel(1) = '1' else"010" when sel(2) = '1' else"011" when sel(3) = '1' else"100" when sel(4) = '1' else"101" when sel(5) = '1' else"110" when sel(6) = '1' else"111" when sel(7) = '1' else"---";end archi;Unsigned 8-bit Greater or Equal ComparatorThe following table shows pin descriptions for a comparator.IO pinsDescriptionA[7:0], B[7:0]Add/Sub Operands

CMPComparison ResultVHDLFollowing is the VHDL code for an unsigned 8-bit greater or equal comparator.library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity compar isport(A,B : in std_logic_vector(7 downto 0);CMP : out std_logic);end compar;architecture archi of compar isbeginCMP <= '1' when A >= Belse '0';end archi;