fft using vhdl

7/27/2019 FFT Using Vhdl

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DESIGN OF FFT

IMPLEMENTATION OF 16-POINT FFT BLOCKS

The FFT computation is accomplished in three stages. The x(0) until x(15)

variables are denoted as the input values for FFT computation and X(0) until X(15) are

denoted as the outputs. The pipeline architecture of the 16 point FFT is shown in Fig 4.1

consisting of butterfly schemes in it. There are two operations to complete the

computation in each stage.

Architecture of 16 point FFT.

The upward arrow will execute addition operation while downward arrow will

execute subtraction operation. The subtracted value is multiplied with twiddle factor


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value before being processed into the next stage. This operation is done concurrently and

is known as butterfly process.

The implementation of FFT flow graph in the VHDL requires three stages, final

computation is done and the result is sent to the variable Y (0) to Y (15). Equation in

each stage is used to construct scheduling diagram.

For stage one, computation is accomplished in three clock cycles denoted as S0 to

S2.The operation is much simpler compared with FFT. This is because FFT processed

both real and imaginary value. The result from FFT is represented in real and imaginary

value because of the multiplication of twiddle factor. Twiddle factor is a constant defined

by the number of point used in this transform. This scheduling diagram is derived from

the equations obtain in FFT signal flow graph. The rest of the scheduling diagrams can be

sketched in the same way as shown in figure 4.2. Thus each stage requires a clock cycle

and totally three clock cycles are needed. Scheduling diagrams are a part of behavioral

modeling and Synthesis steps to translate the algorithmic description into RTL (register

transfer level) in VHDL design.

DESIGN OF A GENERAL RADIX-2 FFT USING VHDL

As we move to higher-point FFTs, the structure for computing the FFT becomes

more complex and the need for an efficient complex multiplier to be incorporated within

the butterfly structure arises. Hence we propose an algorithm for an efficient complex

multiplier that overcomes the complication of using complex numbers throughout the

process.

A radix-2 FFT can be efficiently implemented using a butterfly processor which

includes, besides the butterfly itself, an additional complex multiplier for the twiddle

factors.

A radix-2 butterfly processor consists of a complex adder, a complex subtraction,

and a complex multiplier for the twiddle factors. The complex multiplication with the


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twiddle factor is often implemented with four real multiplications and 2 add / subtract

operations.

Normal Complex Operation:

(X+jY) (C+ jS) = CX + jSX + jCY - YS

= CX YS + j (SX + CY)

Real Part R = CX YS

Imaginary Part I = SX + CY

Using the twiddle factor multiplier that has been developed, it is possible to

design a butterfly processor for a radix-2 Cooley-Tukey FFT. Hence this basic structure

of radix-2 FFT can be used as a building block to construct higher N-point FFTs. This

structure has been developed as an extension to provide for the computation of higher

value index FFTs.


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VHDL IMPLEMENTATION

DESIGN SOFTWARE

The implementations have been carried out using the software, Xilinx ISE 9.2i.

The hardware language used is the Very High Speed Integrated Circuit Hardware

Description Language (VHDL). VHDL is a widely used language for register transfer

level description of hardware. It is used for design entry, compile and simulation of

digital systems.

INTERFACE

The architectural design consist of data inputs, control unit, clocks and the data

output. The register may be of the array of four or eight variable in the type of real. The

FFT implementation in VHDL consists of three states such as start, load and run.


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RESULTS

The simulation of this whole project has been done using the Xilinx ISE of

version 9.2i. Xilinx ISE is a simulation tool for programming {VLSI} {ASIC}s,

{FPGA}s, {CPLD}s, and {SoC}s. It provides a comprehensive simulation and debug

environment for complex ASIC and FPGA designs. Support is provided for multiple

languages including Verilog, SystemVerilog, VHDL and SystemC.

SIMULATION RESULT OBTAINED


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VHDL CODE

Top rtl synth_main.vhd

l i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use i eee. std_ l ogi c_ar i t h. al l ;use wor k. but t er _ l i b. al l ;use i eee. st d_l ogi c_unsi gned. al l ;

ent i t y synt h_mai n i spor t (

dat a_i o : i n st d_l ogi c_vect or ( 31 downt o 0) ;f i nal _op : out st d_l ogi c_vect or ( 31 downt o 0) ;cl ock_mai n, cl ock, enbl , r eset , i ni t : i n std_l ogi c) ;

end synt h_mai n ;

ar chi t ecture rt l of synt h_mai n i ssi gnal shf t , waves : st d_l ogi c_vect or ( 3 downt o 0) ;

component subt r act orport (

a : i n st d_l ogi c_vect or ( 31 downt o 0) ;b : i n st d_l ogi c_vect or ( 31 downt o 0) ;cl ock , r st _sub , sub_en : i n st d_l ogi c ;a_smal l er , f i n_sub , num_zer o : out st d_l ogi c ;zer o_det ect : out st d_l ogi c_vect or ( 1 downt o 0) ;sub : out st d_l ogi c_vect or ( 8 downt o 0) ;change : out st d_l ogi c ) ;

end component ;

component swapport (

a : i n st d_l ogi c_vect or ( 31 downt o 0) ;b : i n st d_l ogi c_vect or ( 31 downt o 0) ;c l ock : i n std_l ogi c ;r st _swap , en_swap : i n st d_l ogi c ;f i ni sh_swap : out st d_l ogi c ;d : out st d_l ogi c_vect or ( 31 downt o 0) ;l ar ge_exp : out st d_l ogi c_vect or ( 7 downt o 0) ;c : out st d_l ogi c_vect or ( 32 downt o 0 ) ) ;

end component ;

component shi f t 2port (

sub_cont r ol : i n st d_l ogi c_vect or ( 8 downt o 0) ;c_i n : i n st d_l ogi c_vect or ( 32 downt o 0) ;shi f t _out : out st d_l ogi c_vect or ( 31 downt o 0) ;cl ock , shi f t _en , rs t_shi f t : i n s td_ l ogi c ;


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f i ni sh_out : out std_l ogi c ) ;end component ;

component cont r ol _mai nport (

a_smal l , si gn_a , si gn_b : i n st d_l ogi c ;

si gn_out , add_sub , r eset _al l : out st d_l ogi c ;en_sub , en_swap , en_shi f t , addpul se , nor mal i se : out

st d_l ogi c ;f i n_sub , f i n_swap , f i ni sh_shi f t , add_f i ni sh , end_al l :

i n std_ l ogi c ;cl ock_mai n , cl ock , r eset , enbl , zer o_num , change : i n

std_ l ogi c ) ;end component ;

component summerport (

num1 , num2 : i n st d_l ogi c_vect or ( 31 downto 0) ;

exp : i n st d_l ogi c_vect or ( 7 downt o 0) ;addpul se_i n , addsub , r st _sum : i n st d_l ogi c ;add_f i ni sh : out st d_l ogi c ;sumout : out st d_l ogi c_vect or ( 32 downt o 0) ) ;

end component ;

component nor mal i zeport (

a , b : i n st d_l ogi c_vect or ( 31 downt o 0) ;numb : i n st d_l ogi c_vect or ( 32 downto 0) ;exp : i n st d_l ogi c_vect or ( 7 downt o 0) ;si gnbi t , addsub , c l ock , en_nor m , r st_norm : i n

st d_l ogi c ;zer o_det ect : i n st d_l ogi c_vect or ( 1 downt o 0) ;exi t _n : out std_l ogi c ;normal _sum : out st d_l ogi c_vect or ( 31 downt o 0) ) ;

end component ;

component but_genpor t (

add_i ncr , add_cl ear , st agedone : i n st d_l ogi c ;but _but t er f l y : out st d_l ogi c_vect or ( 3 downt o 0) ) ;

end component ;

component st age_gen

por t (add_st aged , add_cl ear : i n st d_l ogi c ;st _st age : out st d_l ogi c_vect or ( 1 downt o 0) ) ;

end component ;

component i od_st aged i spor t (

but _f l y : i n st d_l ogi c_vect or ( 3 downt o 0) ;st age_no : i n st d_l ogi c_vect or ( 1 downt o 0) ;


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add_i ncr , i o_mode : i n st d_l ogi c ;add_i od , add_st aged , add_f f t d : out st d_l ogi c ;but t er f l y_i od : out st d_l ogi c_vect or ( 3 downt o 0) ) ;

end component ;

component basei ndex

por t (i nd_but t er f l y : i n st d_l ogi c_vect or ( 3 downt o 0) ;i nd_st age : i n st d_l ogi c_vect or ( 1 downt o 0) ;add_f f t : i n std_ l ogi c ;f f t add_r d : out st d_l ogi c_vect or ( 3 downt o 0) ;c0 , c1 , c2 , c3 : i n st d_l ogi c ) ;

end component ;

component i oadd_genpor t (

i o_but t er f l y : i n st d_l ogi c_vect or ( 3 downt o 0) ;add_i omode , add_i p , add_op : i n st d_l ogi c ;

base_i oadd : out st d_l ogi c_vect or ( 3 downt o 0) ) ;end component ;

component mux_addpor t (

a , b : i n st d_l ogi c_vect or ( 3 downt o 0) ;sel : i n std_ l ogi c ;q : out st d_l ogi c_vect or ( 3 downt o 0) ) ;

end component ;

component r am_shi f tpor t (

dat a_i n : i n st d_l ogi c_vect or ( 3 downt o 0) ;cl ock_mai n : i n st d_l ogi c ;dat a_out : out st d_l ogi c_vect or ( 3 downt o 0) ) ;

end component ;

component cycl espor t (

cl ock_mai n , pr eset , c0_en , cycl es_cl ear : i n st d_l ogi c ;waves : out st d_l ogi c_vect or ( 3 downt o 0) ) ;

end component ;

component count erpor t (

c : out st d_l ogi c_vect or ( 2 downt o 0) ;di sabl e , cl ock_mai n , r eset : i n st d_l ogi c) ;

end component ;

component mul t _c l ockpor t (

cl ock_mai n , mul t 1_c0 , mul t 1_i omode , mul t _cl ear : i nst d_l ogi c ;


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mul t 1_addi ncr : out st d_l ogi c ) ;end component ;

component cont _genpor t (

con_st aged , con_i od , con_f f t d , con_i ni t : i n st d_l ogi c ;

con_i p , con_op , con_i omode , con_f f t : out st d_l ogi c ;con_enbw , con_enbor , c0_enabl e , con_preset : out

st d_l ogi c ;con_cl ear , di sabl e : out st d_l ogi c ;c0 , cl ock_mai n : i n st d_l ogi c ;en_r om , en_r omgen , r eset _count er : out st d_l ogi c ;con_cl kcount : i n st d_l ogi c_vect or ( 2 downt o 0) ) ;

end component ;

component and_gatespor t (

waves_and : i n st d_l ogi c_vect or( 3 downt o 0) ;

cl ock_mai n , c0_en : i n st d_l ogi c ;c0, c1, c2, c3 : out st d_l ogi c ;c0_c1, c2_c3, c0_c2, c1_c3 : out st d_l ogi c ) ;

end component ;

component r _bl ockpor t (

dat a : i n st d_l ogi c_vect or ( 31 downt o 0) ;t r i gger : i n std_ l ogi c ;r _out : out st d_l ogi c_vect or ( 31 downt o 0) ) ;

end component ;

component l _bl ockpor t (

dat a_l : i n st d_l ogi c_vect or ( 31 downt o 0) ;t r i gger_ l : i n s td_ l ogi c ;l _out : out st d_l ogi c_vect or ( 31 downt o 0) ) ;

end component ;

component l evel _edgeport (

dat a_edge : i n st d_l ogi c_vect or ( 31 downt o 0) ;t r i gger _edge : i n st d_l ogi c ;edge_out : out st d_l ogi c_vect or ( 31 downt o 0) ) ;

end component ;

component muxpor t (

d0 , d1 : i n st d_l ogi c_vect or ( 31 downt o 0) ;mux_out : out st d_l ogi c_vector( 31 downt o 0) ;choose : i n st d_l ogi c ) ;

end component ;

component negate


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por t (neg_i n : i n st d_l ogi c_vect or ( 31 downt o 0) ;neg_en , cl ock_mai n : i n st d_l ogi c ;neg_out : out st d_l ogi c_vect or ( 31 downt o 0) ) ;

end component ;

component mul t i pl ypor t (

num_mux , num_r om : i n st d_l ogi c_vect or ( 31 downto 0) ;cl ock : i n std_l ogi c ;mul t _out : out st d_l ogi c_vect or ( 31 downt o 0) ) ;

end component ;

component di vi depor t (

dat a_i n : i n st d_l ogi c_vect or ( 31 downt o 0) ;dat a_out : out st d_l ogi c_vect or ( 31 downt o 0) ) ;

end component ;

component r omadd_gen i spor t (

i o_r om, c0, c1, c2, c3 : i n st d_l ogi c ;st age_r om : i n st d_l ogi c_vect or ( 1 downt o 0) ;but t er f l y_r om : i n st d_l ogi c_vect or ( 3 downt o 0) ;r omadd : out st d_l ogi c_vector( 2 downt o 0) ;r omgen_en : i n st d_l ogi c ) ;

end component ;

component r eg_dpram i spor t (

dat a_f f t , dat a_i o : i n st d_l ogi c_vect or ( 31 downt o 0) ;q : out st d_l ogi c_vect or ( 31 downt o 0) ;cl ock , i o_mode : i n st d_l ogi c;we , r e : i n st d_l ogi c;waddr ess: i n st d_l ogi c_vect or ( 3 downt o 0) ;r addr ess: i n st d_l ogi c_vect or ( 3 downt o 0) ) ;

end component ;

component r om i spor t (

cl ock , en_rom : i n std_l ogi c ;r omadd : i n st d_l ogi c_vect or ( 2 downt o 0) ;r om_dat a : out st d_l ogi c_vect or( 31 downt o 0) ) ;

end component ;

COMPONENT pr i nt_r esul t i sPORT(

cl ock : I N std_l ogi c;op : I N st d_l ogi c;f i n_r es : OUT st d_l ogi c_vect or ( 31 downt o 0) ;r esul t : I N st d_l ogi c_vect or ( 31 downt o 0) ) ;

end component ;


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begi n

r esul t : pr i nt _r esul t por t map ( cl ock_mai n, op, f i nal _op, r am_dat a) ;but : but _gen por t map ( i ncr , cl ear , st aged , but t er f l y_i od) ;

st g : st age_gen port map ( st aged , cl ear , st age) ;i od_st gd : i od_st aged por tmap( but t er f l y_i od, st age, i ncr, i o_mode, i od, st aged, f f t d, but t er f l y) ;base : basei ndex por t map ( but t er f l y , st age , f f t _en , f f t add_r d, c0 , c1 , c2 , c3) ;i oadd : i oadd_gen por t map ( but t er f l y , i o_mode , i p , op ,i o_add) ;r am_shi f t 1 : r am_shi f t por t map ( f f t add_r d , cl ock_mai n , shi f t 1);r am_shi f t 2 : r am_shi f t por t map ( shi f t 1 , cl ock_mai n , shf t ) ;r am_shi f t 3 : r am_shi f t por t map ( shf t , cl ock_mai n , shi f t 3) ;r am_shi f t 4 : r am_shi f t por t map ( shi f t 3 , cl ock_mai n , shi f t 4) ;

r am_shi f t 5 : r am_shi f t por t map ( shi f t 4 , cl ock_mai n , shi f t 5) ;- - r am_shi f t 6 : r am_shi f t por t map ( shi f t 5 , cl ock_mai n , shi f t 6);mul t x1 : mux_add por t map ( shi f t 5 , i o_add , i o_mode , r am_wr ) ;mul t x2 : mux_add por t map ( f f t add_r d , i o_add , i o_mode , r am_r d);cyc : cycl es por t map ( cl ock_mai n , pr eset , c0_en , cyc_cl ear ,waves) ;gates : and_gat es portmap( waves, cl ock_mai n, c0_en, c0, c1, c2, c3, c0_c1, c2_c3, c0_c2, c1_c3) ;cnt : count er por t map ( cl k_count , di sabl e , cl ock_mai n ,r eset _count ) ;mux_cl ock : mul t _cl ock por t map ( cl ock_mai n , c0 , i o_mode ,cl ear , i ncr ) ;cont r ol : cont _gen por t map ( st aged , i od , f f t d , i ni t , i p , op, i o_mode , f f t _en ,enbw , enbor , c0_en , pr eset , cl ear , di sabl e , c0 , cl ock_mai n, r om_en, r omgen_en, r eset_count , cl k_count ) ;

r eg_r am : r eg_dpr am por t map( out _dat a, data_i o, r am_dat a, cl ock_mai n, i o_mode, enbw, enbor, r am_wr , ram_r d) ;

f 1 : r _bl ock por t map ( r am_dat a , c0 , d2) ;f 2 : l _bl ock por t map ( r am_dat a , c1 , d3) ;

f 3 : r _bl ock por t map ( r am_dat a , c2 , d4) ;f 4 : r _bl ock por t map ( r am_dat a , c3 , d5) ;f 5 : r _bl ock por t map ( d8 , c1_c3 , d9) ;f 6 : l _bl ock por t map ( d8 , c0_c2 , d10) ;f 7 : l _bl ock por t map ( d12 , c3 , d13) ;f 8 : l _bl ock por t map ( d12 , c1 , d14) ;f 9 : r _bl ock por t map ( d17 , cl ock_mai n , d18) ;f 10 : r _bl ock por t map ( dat a_r om , cl ock_mai n , r om_f f ) ;mux1 : mux por t map (d2 , d3 , d6 , c2_c3) ;


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mux2 : mux por t map (d4 , d5 , d7 , c1_c3) ;mux3 : mux por t map (d13 , d14 , d15 , c1_c3) ;neg1 : negat e port map ( d10 , c0_c1 , cl ock_mai n , d11) ;neg2 : negat e port map ( d15 , c0_c1 , cl ock_mai n , d16) ;mul t 1 : mul t i pl y por t map ( d6 , r om_f f , cl ock_mai n , d8) ;di v : di vi de por t map ( d18 , d19) ;

f 11 : l evel _edge por t map ( d19, cl ock_mai n, out _dat a) ;

r om_add1 : r omadd_gen por t map( i o_mode, c0, c1, c2, c3, st age, but t erf l y, r om_add, r omgen_en) ;r om1 : r om por t map ( cl ock , r om_en, r om_add, data_r om) ;

b11 : subt r act or por t map ( d16 , d7 , cl ock , r st b , ensubb ,a_smal l b , f i nsubb , numzerob , zerodet ect b , subb , changeb) ;b2 : swap port map ( a=>d16 , b=>d7 , cl ock=>cl ock ,r st _swap=>r st b , en_swap=>enswapb , f i ni sh_swap=>f i nswapb ,d=>swap_num2b , l ar ge_exp=>expb , c=>swap_num1b ) ;b4 : shi f t 2 por t map ( sub_cont r ol =>subb , c_ i n=>swap_num1b ,

shi f t _out =>shi f t _out b , cl ock=>cl ock , shi f t _en=>enshi f t b,r st _shi f t =>r st b , f i ni sh_out =>f i nshi f t b ) ;b5 : cont r ol _mai n port map ( a_smal l b , d16( 31) , d7( 31) ,si gnbi t b , addsubb , r st b , ensubb ,enswapb , enshi f t b , addpul seb , nor mal i seb , f i nsubb , f i nswapb, f i nshi f t b , f i ni sh_sumb , end_al l b ,cl ock_mai n , cl ock , r eset , enbl , numzer ob , changeb ) ;b6 : summer por t map ( shi f t _out b , swap_num2b , expb , addpul seb, addsubb , r st b , f i ni sh_sumb , sum_out b ) ;b7 : nor mal i ze por t map ( d16 , d7 , sum_out b , expb , si gnbi t b ,addsubb , cl ock , nor mal i seb , r st b , zer odet ect b , end_al l b ,d17) ;

a1 : subt r act or por t map ( d9 , d11 , cl ock , r st , ensub ,a_smal l , f i nsub , numzer o , zerodet ect , suba , changea) ;a2 : swap por t map ( d9 , d11 , cl ock , r st , enswap , f i nswap, swap_num2 , exp , swap_num1 ) ;a4 : shi f t 2 por t map ( suba , swap_num1 , shi f t _out a , cl ock ,enshi f t , r s t , f i nshi f t ) ;a5 : cont r ol _mai n por t map ( a_smal l , d9( 31) , d11( 31) , si gnbi t, addsub , r st , ensub ,enswap , enshi f t , addpul se , nor mal i se , f i nsub , f i nswap ,f i nshi f t , f i ni sh_sum , end_al l ,cl ock_mai n , cl ock , r eset , enbl , numzer o , changea ) ;a6 : summer por t map ( shi f t _out a , swap_num2 , exp , addpul se ,

addsub , r st , f i ni sh_sum , sum_out ) ;a7 : nor mal i ze por t map ( d9 , d11 , sum_out , exp , si gnbi t ,addsub , cl ock , nor mal i se , r st , zer odet ect , end_al l , d12) ;

end r t l ;

Testbench file synth_test.vhd

l i br ar y i eee;


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use i eee. st d_l ogi c_1164. al l ;use i eee. std_ l ogi c_ar i t h. al l ;use i eee. st d_l ogi c_unsi gned. al l ;l i br ar y wor k;use wor k. but t er _ l i b. al l ;USE I EEE. STD_LOGI C_TEXTI O. ALL;

USE STD. TEXTI O. ALL;

ENTI TY t b I SEND t b;

ARCHI TECTURE test bench_ar ch OF t b I SFI LE RESULTS: TEXT OPEN WRI TE_MODE I S "r esul t s. t xt " ;

COMPONENT synt h_mai nPORT (

dat a_i o : I n st d_l ogi c_vect or ( 31 DownTo 0) ;f i nal _op : Out st d_l ogi c_vect or ( 31 DownTo 0) ;

cl ock_mai n : I n st d_l ogi c;cl ock : I n st d_l ogi c;enbl : I n std_l ogi c;r eset : I n st d_l ogi c;i ni t : I n st d_ l ogi c

) ;END COMPONENT;

SI GNAL dat a_i o : st d_l ogi c_vector ( 31 DownTo 0) : ="00000000000000000000000000000000";

SI GNAL f i nal _op : st d_l ogi c_vect or ( 31 DownTo 0) : ="00000000000000000000000000000000";

SI GNAL cl ock_mai n : st d_l ogi c : = ' 0' ;SI GNAL cl ock : st d_l ogi c : = ' 0' ;SI GNAL enbl : st d_l ogi c : = ' 0' ;SI GNAL r eset : st d_l ogi c : = ' 0' ;SI GNAL i ni t : st d_l ogi c : = ' 0' ;

const ant PERI OD_cl ock : t i me : = 200 ns;const ant DUTY_CYCLE_cl ock : r eal : = 0. 5;const ant OFFSET_cl ock : t i me : = 100 ns;const ant PERI OD_cl ock_mai n : t i me : = 200 ns;const ant DUTY_CYCLE_cl ock_mai n : r eal : = 0. 5;const ant OFFSET_cl ock_mai n : t i me : = 0 ns;

BEGI NUUT : synt h_mai nPORT MAP (

data_i o => dat a_i o,f i nal _op => f i nal _op,cl ock_mai n => cl ock_mai n,cl ock => cl ock,enbl => enbl ,r eset => r eset ,


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i ni t => i ni t) ;

pr ocessvar i abl e i : i nt eger : = 0 ;begi n

f or i i n 1 t o 1000 l oopcl ock


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swap.vhd

- - SWAP UNI Tl i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use i eee. std_ l ogi c_ar i t h. al l ;

use wor k. but t er _ l i b. al l ;use i eee. st d_l ogi c_unsi gned. al l ;

ent i t y swap i spor t (

a : i n st d_l ogi c_vect or ( 31 downt o 0) ;b : i n st d_l ogi c_vect or ( 31 downt o 0) ;c l ock : i n std_l ogi c ;r st _swap , en_swap : i n st d_l ogi c ;f i ni sh_swap : out st d_l ogi c ;d : out st d_l ogi c_vect or ( 31 downt o 0) ;l ar ge_exp : out st d_l ogi c_vect or ( 7 downt o 0) ;c : out st d_l ogi c_vect or ( 32 downt o 0 ) ) ;

end swap ;

ar chi t ecture r t l of swap i sbegi npr ocess ( a , b , cl ock , r st _swap , en_swap)var i abl e x , y : st d_l ogi c_vect or ( 7 downt o 0) ;var i abl e p , q : st d_l ogi c_vect or ( 22 downt o 0) ;begi ni f ( r st _swap = ' 1' ) t henc


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l arge_exp


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summer.vhd

- - SUMMERl i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use i eee. std_ l ogi c_ar i t h. al l ;


ent i t y summer i spor t (

num1 , num2 : i n st d_l ogi c_vect or ( 31 downto 0) ;exp : i n st d_l ogi c_vect or ( 7 downt o 0) ;addpul se_i n , addsub , r st _sum : i n st d_l ogi c ;add_f i ni sh : out st d_l ogi c ;sumout : out st d_l ogi c_vect or ( 32 downt o 0) ) ;

end summer ;ar chi t ect ur e r t l of summer i sbegi nprocess ( num1 , num2 , addpul se_i n , r st _sum)var i abl e t emp_num1 , t emp_sum , t emp_num2 , t emp_sum2 , r es :st d_l ogi c_vect or ( 32 downt o 0) ;var i abl e t emp_exp : st d_l ogi c_vect or ( 7 downt o 0) ;begi ni f ( rs t_sum = ' 0' ) t heni f ( addpul se_i n = ' 1' ) t hent emp_num1 : = ' 0' & num1 ( 31 downt o 0) ; - - 0 t o f i nd whet hernor mal i sat i on i s r equi r ed.t emp_num2 : = ' 0' & num2 (31 downto 0) ; - - i f r equi r ed MSB wi l l be1 af t er addi t i on

i f ( addsub = ' 1' ) t hent emp_sum : = t emp_num1 + t emp_num2 ;sumout


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subtractor.vhd

- - SUBTRACTOR UNI Tl i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use i eee. std_ l ogi c_ar i t h. al l ;


ent i t y subt r actor i sport (

a : i n st d_l ogi c_vect or ( 31 downt o 0) ;b : i n st d_l ogi c_vect or ( 31 downt o 0) ;cl ock , r st _sub , sub_en : i n st d_l ogi c ;a_smal l er , f i n_sub , num_zer o : out st d_l ogi c ;zer o_det ect : out st d_l ogi c_vect or ( 1 downt o 0) ;sub : out st d_l ogi c_vect or ( 8 downt o 0) ;change : out st d_l ogi c ) ;

end subt r act or ;

ar chi t ectur e r t l of subt r act or i sbegi npr ocess ( a , b , cl ock , r st _sub , sub_en)var i abl e t emp , c , d : st d_l ogi c_vect or ( 7 downt o 0) ;var i abl e e , f : st d_l ogi c_vect or ( 22 downt o 0) ;begi ni f ( rst _sub = ' 0' ) t henc : = a ( 30 downt o 23) ;d : = b ( 30 downt o 23) ;e : = a ( 22 downt o 0) ;f : = b (22 downt o 0) ;

i f ( sub_en = ' 1' ) t heni f ( cl ock = ' 1' ) t heni f ( ( c=0) ) t henzer o_detect


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a_smal l er


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stage.vhd- - STAGE NUMBER GENERATOR.l i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use i eee. std_ l ogi c_ar i t h. al l ;use wor k. but t er _ l i b. al l ;

use i eee. st d_l ogi c_unsi gned. al l ;

ent i t y st age_gen i spor t (

add_st aged , add_cl ear : i n st d_l ogi c ;st _st age : out st d_l ogi c_vect or ( 1 downt o 0) ) ;

end st age_gen ;

ar chi t ecture r t l of st age_gen i s

begi npr ocess( add_st aged , add_cl ear )

var i abl e s_count : st d_l ogi c_vect or ( 1 downt o 0) ;begi ni f ( add_cl ear = ' 1' ) t henst _s t age


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shift2.vhd- - SHI FT UNI Tl i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use wor k. but t er _ l i b. al l ;use i eee. std_ l ogi c_ar i t h. al l ;


ent i ty shi f t 2 i spor t (

sub_cont r ol : i n st d_l ogi c_vect or ( 8 downt o 0) ;c_i n : i n st d_l ogi c_vect or ( 32 downt o 0) ;shi f t _out : out st d_l ogi c_vect or ( 31 downt o 0) ;cl ock , shi f t _en , rs t_shi f t : i n s td_ l ogi c ;f i ni sh_out : out std_l ogi c ) ;

end shi f t 2 ;ar chi t ecture r t l of shi f t2 i sbegi n

pr ocess( cl ock)var i abl e sub_t emp : st d_l ogi c_vect or ( 7 downt o 0) ;var i abl e t emp2 , t emp4 : st d_l ogi c_vector( 31 downt o 0) ;var i abl e t emp3 , t : st d_l ogi c ;begi ni f ( r st _ shi f t=' 0' ) theni f (shi f t _en = ' 1' ) t heni f ( t emp3 = ' 1' ) t heni f ( sub_cont r ol ( 8) = ' 1' ) t hensub_t emp : = sub_cont r ol ( 7 downt o 0) ;t emp2 : = ' 1' & c_i n ( 31 downt o 1) ; - - ' 1' f or i mpl i ci t onet emp3 : = ' 0' ;

end i f ;end i f ;end i f ;end i f ;

i f ( r st _ shi f t=' 0' ) theni f (shi f t _en = ' 1' ) t heni f ( t = ' 1' ) theni f ( sub_cont r ol ( 8) = ' 1' ) t heni f ( conv_i nt eger ( sub_t emp( 7 downto 0) ) = 0) t henshi f t _out


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t emp3 : = ' 1' ;f i ni sh_out


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romadd_gen.vhd- - ADDRESS GENERATOR FOR ROMl i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use wor k. but t er _ l i b. al l ;use i eee. st d_l ogi c_unsi gned. al l ;

ent i t y r omadd_gen i spor t (

i o_r om, c0, c1, c2, c3 : i n st d_l ogi c ;st age_r om : i n st d_l ogi c_vect or ( 1 downt o 0) ;but t er f l y_r om : i n st d_l ogi c_vect or ( 3 downt o 0) ;r omadd : out st d_l ogi c_vector( 2 downt o 0) ;r omgen_en : i n st d_l ogi c ) ;

end r omadd_gen ;

ar chi t ect ur e r t l of r omadd_gen i sbegi n

pr ocess( i o_r om, c0, c1, c2, c3, st age_r om, but t er f l y_r om)begi ni f ( r omgen_en = ' 1' ) t heni f ( i o_ rom = ' 0' ) t hencase st age_r om i s

when "00" =>i f ( c0=' 1' or c2=' 1' ) t henr omadd


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r omadd


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rom.vhd- - ROM TO STORE SI NE AND COSI NE VALUESl i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use i eee. std_ l ogi c_ar i t h. al l ;use wor k. but t er _ l i b. al l ;


ent i t y rom i spor t (

cl ock , en_rom : i n std_l ogi c ;r omadd : i n st d_l ogi c_vect or ( 2 downt o 0) ;r om_dat a : out st d_l ogi c_vect or( 31 downt o 0) ) ;

end r om ;

ar chi t ecture r t l of rom i sbegi npr ocess( cl ock, en_r om)

begi ni f ( en_rom= ' 1' ) t heni f (c l ock = ' 1' ) thencase r omadd i swhen "000" =>r om_dat a r om_dat a r om_dat a r om_dat a r om_dat a r om_dat a r om_dat a r om_dat a r om_dat a


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rblock.vhd- - NEGATI VE EDGE TRI GGERED FLI P FLOPSl i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use i eee. std_ l ogi c_ar i t h. al l ;use wor k. but t er _ l i b. al l ;


ent i t y r _bl ock i sport (

dat a : i n st d_l ogi c_vect or ( 31 downt o 0) ;t r i gger : i n std_ l ogi c ;r _out : out st d_l ogi c_vect or ( 31 downt o 0) ) ;

end r _bl ock ;

ar chi t ect ure rt l of r_bl ock i sbegi npr ocess( dat a , t r i gger )

begi ni f ( t r i gger =' 0' and t r i gger ' event ) t henr _out


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ram_shift.vhd- - PARALLE I N PARALLEL OUT SHI FTER I N THE ADDRESS GENERATI ONUNI T.- - REQUI RED BECAUSE FFT I S COMPUTED ON DATA AND WRI TTEN BACK I NTO

THE SAME- - LOCATI ON AFTER 5 CYCLES. SO THE READ ADDRESS I S SHI FTED

THROUGH 5 CYCLES- - AND GI VEN AS WRI TE ADDRESS.l i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use i eee. std_ l ogi c_ar i t h. al l ;use wor k. but t er _ l i b. al l ;use i eee. st d_l ogi c_unsi gned. al l ;

ent i t y r am_shi f t i spor t (

dat a_i n : i n st d_l ogi c_vect or ( 3 downt o 0) ;cl ock_mai n : i n st d_l ogi c ;

dat a_out : out st d_l ogi c_vect or ( 3 downt o 0) ) ;end r am_shi f t ;

ar chi t ectur e r t l of r am_shi f t i sbegi npr ocess( cl ock_mai n , dat a_i n)begi ni f ( cl ock_mai n' event and cl ock_mai n = ' 0' ) t hendat a_out


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ram.vhd- - Behavi or al descr i pt i on of dual - por t SRAM wi t h :- - Act i ve Hi gh wr i t e enabl e (WE)- - Act i ve Hi gh r ead enabl e ( RE)- - Ri si ng cl ock edge ( Cl ock)l i br ar y i eee;

use i eee. st d_l ogi c_1164. al l ;use I EEE. std_ l ogi c_ar i t h. al l ;use I EEE. st d_l ogi c_unsi gned. al l ;use wor k. but t er _ l i b. al l ;ent i t y r eg_dpr am i spor t (

dat a_f f t , dat a_i o : i n st d_l ogi c_vect or ( 31 downt o 0) ;q : out st d_l ogi c_vect or ( 31 downt o 0) ;cl ock , i o_mode : i n st d_l ogi c;we , r e : i n st d_l ogi c;waddr ess: i n st d_l ogi c_vect or ( 3 downt o 0) ;r addr ess: i n st d_l ogi c_vect or ( 3 downt o 0) ) ;

end r eg_dpram;ar chi t ect ur e behav of r eg_dpr am i st ype MEM i s ar r ay ( 0 t o 15) of st d_l ogi c_vect or ( 31 downt o 0) ;si gnal r amTmp : MEM;

begi n

- - Wr i t e Funct i onal Sect i onpr ocess ( cl ock, waddr ess, we)begi ni f ( cl ock=' 0' ) t heni f ( we = ' 1' ) t hen

i f ( i o_mode = ' 0' ) t henr amTmp ( conv_i nt eger ( waddress) )


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print.vhd- - USED TO PRI NT THE RESULTS I N A NEAT FORMAT. NOT SYNTHESI SABLE.- - USED ONLY FOR SI MULATI ON PURPOSE.l i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use std. t ext i o. al l ;

use wor k. but t er _ l i b. al l ;use i eee. st d_l ogi c_t ext i o. al l ;use i eee. st d_l ogi c_unsi gned. al l ;use I EEE. mat h_r eal . al l ;use I EEE. std_ l ogi c_ar i t h. al l ;use work. t xt _ut i l . al l ;

ent i ty pr i nt _ resul t i sport ( cl ock, op : i n std_l ogi c ;

f i n_r es : OUT st d_l ogi c_vect or ( 31 downt o 0) ;r esul t : i n st d_l ogi c_vect or ( 31 downt o 0) ) ;

end pr i nt _r esul t ;

ar chi t ecture r t l of pr i nt_ r esul t i sf i l e vect or w_f i l e : t ext open wr i t e_mode i s"G: \ Xi l i nx92i \ proj ect s \ proj _ f f t _ I I \ resul t . t xt " ;begi npr ocess( op, cl ock)var i abl e l , l 2 : l i ne ;var i abl e q , p : i nt eger : = 0 ;var i abl e count : i nt eger : = 1 ;begi ni f ( op = ' 1' ) t hen

i f ( count < 17) t heni f ( cl ock=' 0' and cl ock' event ) t henq : = 31 ;count : = count + 1 ;f or p i n 1 t o 32 l oop - - dat a f r om RAM- - wr i te( l 2 , resul t ( p) ) ;q : = q - 1 ;end l oop ;q : = 31 ;- - wr i t el i ne( vect orw_ f i l e , l 2) ;end i f ;end i f ;end i f ;

end process ;end r t l ;


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out_result.vhd- - OUTPUT RESULTS. SYNTHESI SABLEl i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use i eee. std_ l ogi c_ar i t h. al l ;use wor k. but t er _ l i b. al l ;


ent i ty pr i nt _ resul t i sPORT(

cl ock : I N std_l ogi c;op : I N st d_l ogi c;f i n_r es : OUT st d_l ogi c_vect or ( 31 downt o 0) ;r esul t : I N st d_l ogi c_vect or ( 31 downt o 0) ) ;

end pr i nt _r esul t ;

ar chi t ecture r t l of pr i nt_ r esul t i sbegi n

pr ocess( op, cl ock)var i abl e count : i nt eger : = 1 ;begi ni f ( op = ' 1' ) t heni f ( count < 17) t heni f ( cl ock=' 0' and cl ock' event ) t henf i n_r es


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normalize.vhdl i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use wor k. but t er _ l i b. al l ;use i eee. std_ l ogi c_ar i t h. al l ;use std. t ext i o. al l ;

use i eee. st d_l ogi c_t ext i o. al l ;use i eee. st d_l ogi c_unsi gned. al l ;

ent i t y nor mal i ze i spor t (

a , b : i n st d_l ogi c_vect or ( 31 downt o 0) ;numb : i n st d_l ogi c_vect or ( 32 downto 0) ;exp : i n st d_l ogi c_vect or ( 7 downt o 0) ;si gnbi t , addsub , c l ock , en_nor m , r st_norm : i n

st d_l ogi c ;zer o_det ect : i n st d_l ogi c_vect or ( 1 downt o 0) ;exi t _n : out std_l ogi c ;

normal _sum : out st d_l ogi c_vect or ( 31 downt o 0) ) ;end nor mal i ze ;

ar chi t ecture r t l of nor mal i ze i sbegi npr ocess ( cl ock)var i abl e numb_t emp : st d_l ogi c_vector ( 31 downt o 0) ;var i abl e t emp_exp : st d_l ogi c_vect or ( 7 downt o 0) ;var i abl e t , t 2 : std_ l ogi c : = ' 1' ;

begi ni f ( rs t_norm = ' 0' ) then

i f ( en_nor m = ' 1' ) t heni f ( t = ' 1' ) thennumb_t emp : = numb( 31 downt o 0) ;t emp_exp : = exp (7 downt o 0) ;t : = ' 0' ;end i f ;i f ( t2 = ' 1' ) theni f ( zer o_det ect = 0) t heni f ( addsub = ' 0' ) t heni f ( numb_t emp = 0) t hennormal _sum


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end i f ;el si f ( addsub = ' 1' and numb( 32) = ' 1' and cl ock = ' 1' ) t hent emp_exp : = t emp_exp + "00000001" ;normal _sum


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negate.vhd- - NEGATI ON UNI Tl i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use i eee. std_ l ogi c_ar i t h. al l ;use wor k. but t er _ l i b. al l ;


ent i t y negat e i sport (

neg_i n : i n st d_l ogi c_vect or ( 31 downt o 0) ;neg_en , cl ock_mai n : i n st d_l ogi c ;neg_out : out st d_l ogi c_vect or ( 31 downt o 0) ) ;

end negat e ;

ar chi t ecture r t l of negat e i sbegi npr ocess( neg_i n , neg_en , cl ock_mai n)

var i abl e neg_t emp : st d_l ogi c_vect or ( 31 downt o 0) ;begi nneg_t emp : = neg_i n( 31 downt o 0) ;i f ( cl ock_mai n = ' 1' ) t heni f ( neg_en = ' 1' ) t heni f ( neg_i n( 31) = ' 0' ) t henneg_t emp : = ' 1' & neg_t emp ( 30 downt o 0) ;el seneg_t emp : = ' 0' & neg_t emp ( 30 downt o 0) ;end i f ;neg_out


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mux_but.vhd- - MULTI PLEXER I N THE BUTTERFLY PROCESSI NG UNI Tl i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use i eee. std_ l ogi c_ar i t h. al l ;use wor k. but t er _ l i b. al l ;


ent i t y mux i sport (

d0 , d1 : i n st d_l ogi c_vect or ( 31 downt o 0) ;mux_out : out st d_l ogi c_vector( 31 downt o 0) ;choose : i n st d_l ogi c ) ;

end mux ;

ar chi t ecture rt l of mux i sbegi npr ocess( d0 , d1 , choose)

begi ni f ( choose = ' 0' ) t henmux_out


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mux_add.vhd- - mul t i pl exer i n t he addr ess gener at i on uni tl i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use i eee. std_ l ogi c_ar i t h. al l ;use wor k. but t er _ l i b. al l ;


ent i t y mux_add i spor t (

a , b : i n st d_l ogi c_vect or ( 3 downt o 0) ;sel : i n std_ l ogi c ;q : out st d_l ogi c_vect or ( 3 downt o 0) ) ;

end mux_add ;

ar chi t ect ur e r t l of mux_add i sbegi npr ocess ( a , b , sel )

begi ni f ( sel = ' 0' ) thenq


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multiply.vhd- - MULTI PLY UNI Tl i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use i eee. std_ l ogi c_ar i th. al l ;use wor k. but t er _ l i b. al l ;


ent i t y mul t i pl y i sport(

num_mux , num_r om : i n st d_l ogi c_vect or ( 31 downto 0) ;cl ock : i n std_l ogi c ;mul t _out : out st d_l ogi c_vect or( 31 downt o 0) ) ;

end mul t i pl y ;

ar chi t ect ure rt l of mul t i pl y i sbegi nprocess( num_mux , num_r om , cl ock)

vari abl e si gn_mul t , t : std_l ogi c : = ' 0' ;var i abl e t emp1 , t emp2 : st d_l ogi c_vect or ( 22 downto 0) ;var i abl e exp_mux , exp_r om : st d_l ogi c_vect or ( 7 downt o 0) ;var i abl e mant _t emp : st d_l ogi c_vector( 45 downt o 0) ;var i abl e exp_mul t , mux_t emp , r om_t emp : st d_l ogi c_vector( 8downt o 0) ;var i abl e r es_t emp : st d_l ogi c_vect or ( 31 downt o 0) ;begi n

t emp1 : = ' 1' & num_mux(22 downt o 1) ; - - ' 1' f or i mpl i ci t ' 1' .t emp2 : = ' 1' & num_r om( 22 downt o 1) ;i f ( num_mux( 31) = ' 1' and num_r om( 31) = ' 1' and cl ock = ' 1' ) t hen

- - s i gn of r esul tssi gn_mul t : = ' 0' ;el si f ( num_mux( 31) = ' 0' and num_r om( 31) = ' 0' and cl ock = ' 1' )t hensi gn_mul t : = ' 0' ;el s i f ( cl ock = ' 1' ) t hensi gn_mul t : = ' 1' ;end i f ;

i f ( num_mux = 0 and cl ock = ' 1' ) t hen - - i e, t he number i s zer o.t : = ' 1' ;el si f ( num_r om = 0 and cl ock = ' 1' ) t hent : = ' 1' ;

el s i f ( cl ock = ' 1' ) t hent : = ' 0' ;end i f ;

i f ( t = ' 0' and cl ock = ' 1' ) t hen - - separ at i on of mant i ssa andexponentexp_mux : = num_mux ( 30 downt o 23) ;exp_r om : = num_r om ( 30 downto 23) ;


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mux_t emp : = ' 0' & exp_mux( 7 downt o 0) ;r om_t emp : = ' 0' & exp_r om( 7 downt o 0) ;exp_mul t : = mux_ t emp + r om_t emp ;exp_mul t : = exp_mul t - 127 ;

mant _t emp : = t emp1 * t emp2 ;

i f ( mant _t emp( 45) = ' 1' ) t hen - - nor mal i sat i on.exp_mul t : = exp_mul t + 1 ;r es_ t emp : = si gn_mul t & exp_mul t ( 7 downt o 0) & mant _t emp( 44downt o 22) ;mul t _out


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mult.vhd- - MULTI PLEXER TO CHOOSE BETWEEN CLOCK AND C0l i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use i eee. std_ l ogi c_ar i t h. al l ;use wor k. but t er _ l i b. al l ;


ent i t y mul t _cl ock i spor t (

cl ock_mai n , mul t 1_c0 , mul t 1_i omode , mul t _cl ear : i nst d_l ogi c ;

mul t 1_addi ncr : out st d_l ogi c ) ;end mul t _cl ock ;

ar chi t ectur e r t l of mul t _cl ock i sbegi npr ocess( cl ock_mai n , mul t 1_c0 , mul t 1_i omode , mul t _cl ear )

var i abl e t emp1 : st d_l ogi c ;var i abl e t emp2 : st d_l ogi c ;begi ni f ( mul t 1_i omode = ' 0' ) t hen - - i e, f f t comput at i on modet emp2 : = mul t 1_c0 ;el si f ( mul t 1_i omode = ' 1' ) t hen - - i e, i o modet emp1 : = cl ock_mai n ;end i f ;i f ( mul t 1_i omode = ' 1' ) t henmul t 1_addi ncr


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lblock.vhd- - POSI TI VE LEVEL TRI GGERED FLI P FLOPSl i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use i eee. std_ l ogi c_ar i t h. al l ;use wor k. but t er _ l i b. al l ;


ent i t y l _bl ock i sport (

dat a_l : i n st d_l ogi c_vect or ( 31 downt o 0) ;t r i gger_ l : i n s td_ l ogi c ;l _out : out st d_l ogi c_vect or ( 31 downt o 0) ) ;

end l _bl ock ;

ar chi t ect ure r t l of l _bl ock i sbegi npr ocess(dat a_l , t r i gger _l )

begi ni f ( t r i gger_ l =' 1' ) t henl _out


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iod_staged.vhd- - THI S FI LE OUTPUTS THE " I O DONE" AND "STAGE DONE" AND "FFTDONE" SI GNALS AT THE- - CORRECT TI ME. I T ALSO RECEI VES THE OUTPUT OF THE BUTTERFLYGENERATOR- - AND OUTPUTS I T UNCHANGED.

l i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use i eee. std_ l ogi c_ar i t h. al l ;use wor k. but t er _ l i b. al l ;use i eee. st d_l ogi c_unsi gned. al l ;

ent i t y i od_st aged i spor t (

but _f l y : i n st d_l ogi c_vect or ( 3 downt o 0) ;st age_no : i n st d_l ogi c_vect or ( 1 downt o 0) ;add_i ncr , i o_mode : i n st d_l ogi c ;add_i od , add_st aged , add_f f t d : out st d_l ogi c ;

but t er f l y_i od : out st d_l ogi c_vect or ( 3 downt o 0) ) ;end i od_st aged ;

ar chi t ectur e r t l of i od_staged i sbegi npr ocess( but _f l y, add_i ncr , i o_mode)begi ni f ( but _f l y = 15 and i o_mode = ' 1' and add_i ncr =' 0' ) t henadd_i od


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ioadd.vhd- - I O ADDRESS GENERATORl i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use i eee. std_ l ogi c_ar i t h. al l ;use wor k. but t er _ l i b. al l ;


ent i t y i oadd_gen i spor t (

i o_but t er f l y : i n st d_l ogi c_vect or ( 3 downt o 0) ;add_i omode , add_i p , add_op : i n st d_l ogi c ;base_i oadd : out st d_l ogi c_vect or ( 3 downt o 0) ) ;

end i oadd_gen ;

ar chi t ecture r t l of i oadd_gen i sbegi npr ocess( i o_but t erf l y , add_i omode , add_i p , add_op)

var i abl e out _dat a : st d_l ogi c_vect or ( 3 downt o 0) ;begi ni f ( add_i omode = ' 1' ) t heni f ( add_i p = ' 1' ) t henout _dat a : = i o_but t erf l y(3 downt o 0) ;

el si f ( add_op = ' 1' ) t heni f ( i o_but t er f l y( 3) = ' 0' ) t hen - - i e, r eal partout _dat a : = ' 0' & i o_but t er f l y( 0) & i o_but t er f l y( 1) &

i o_but t erf l y( 2) ;el si f ( i o_but t er f l y( 3) =' 1' ) t hen - - i e, compl ex par tout _dat a : = ' 1' & i o_but t er f l y( 0) & i o_but t er f l y( 1) &

i o_but t erf l y( 2) ;

end i f ;end i f ;end i f ;base_i oadd


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divide.vhd- - DI VI DE BY TWO UNI T. THI S FI LE HOWEVER PASSED THE DATAUNCHANGED- - BECAUSE DI VI SI ON I S REQUI RED ONLY I F SCALI NG I S USED TO AVOI DOVERFLOW.- - NO SCALI NG WAS USED I N THI S PROJ ECT, SO THAT RESULTS OF

MATLAB MATCHED WI TH OURSl i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use i eee. std_ l ogi c_ar i t h. al l ;use wor k. but t er _ l i b. al l ;use i eee. st d_l ogi c_unsi gned. al l ;

ent i t y di vi de i sport (

dat a_i n : i n st d_l ogi c_vect or ( 31 downt o 0) ;dat a_out : out st d_l ogi c_vect or ( 31 downt o 0) ) ;

end di vi de ;

ar chi t ect ure r t l of di vi de i sbegi npr ocess( dat a_i n)var i abl e di vi de_exp : st d_l ogi c_vect or ( 7 downt o 0) ;var i abl e di vi de_mant : st d_l ogi c_vect or ( 31 downt o 0) ;begi ni f ( dat a_i n = "00000000000000000000000000000000") t hendat a_out


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dff.vhd- - POSI TI VE EDGE TRI GGERED FLI PFLOPS PLACED BEFORE THE DI VI DE BY

TWO UNI Tl i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use i eee. std_ l ogi c_ar i t h. al l ;


ent i t y l evel _edge i sport (

dat a_edge : i n st d_l ogi c_vect or ( 31 downt o 0) ;t r i gger _edge : i n st d_l ogi c ;edge_out : out st d_l ogi c_vect or ( 31 downt o 0) ) ;

end l evel _edge ;

ar chi t ectur e r t l of l evel _edge i sbegi n

pr ocess( data_edge , t r i gger _edge)begi ni f ( t r i gger _edge=' 1' and t r i gger _edge' event ) t henedge_out


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cycles_but.vhd- - WAVEFORM GENERATOR- - THE 4 BI TS OF " DATA_OUT" ARE "C0 C1 C2 C3"l i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use wor k. but t er _ l i b. al l ;

ent i t y cycl es i spor t (

cl ock_mai n , pr eset , c0_en , cycl es_cl ear : i n st d_l ogi c ;waves : out st d_l ogi c_vect or ( 3 downt o 0) ) ;

end cycl es ;ar chi t ect ure rt l of cycl es i s- - t ype state_val ues i s ( st0 , st1 , st2 , st3) ;- - si gnal pr es_st at e1 , next _st at e1 : st at e_val ues ;shar ed var i abl e dat a_out : st d_l ogi c_vect or ( 3 downt o 0) ;begi npr ocess ( cl ock_mai n , pr eset , c0_en, cycl es_cl ear )

var i abl e t : std_ l ogi c ;begi ni f ( c0_en = ' 1' ) t heni f ( pr eset = ' 1' and t =' 1' ) t henpres_st at e1


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dat a_out : = "0001" ;next _st at e1 next _s t at e1


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controller.vhd- - CONTROL UNI T OF THE PROCESSORl i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use i eee. std_ l ogi c_ar i t h. al l ;use wor k. but t er _ l i b. al l ;


ent i t y cont _gen i spor t (

con_st aged , con_i od , con_f f t d , con_i ni t : i n st d_l ogi c ;con_i p , con_op , con_i omode , con_f f t : out st d_l ogi c ;con_enbw , con_enbor , c0_enabl e , con_preset : out

st d_l ogi c ;con_cl ear , di sabl e : out st d_l ogi c ;c0 , cl ock_mai n : i n st d_l ogi c ;en_r om , en_r omgen , r eset _count er : out st d_l ogi c ;con_cl kcount : i n st d_l ogi c_vect or ( 2 downt o 0) ) ;

end cont _gen ;

ar chi t ecture r t l of cont _gen i st ype s tate i s ( r st 1, rs t2, rs t 3, rs t4, rs t 5, rs t 6, rs t7) ;si gnal cur r ent _st at e , next _st at e : st at e ;shar ed var i abl e count er , t emp2 : st d_l ogi c_vect or( 1 downt o 0) : ="00" ;begi npr ocess ( cur r ent _st at e , con_st aged , con_i od , con_f f t d ,con_cl kcount , c0)

begi n

case cur r ent _st at e i swhen rst 1 =>con_i omode


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con_f f t


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con_cl ear


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butter_lib.vhd- - THI S FI LE DECLARES THE SI GNALS USED I N THE PROCESSORl i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use i eee. std_ l ogi c_ar i t h. al l ;use i eee. st d_l ogi c_unsi gned. al l ;

package but t er _l i b i s

si gnalr am_dat a, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15, d16, d17,d18, d19, out _dat a : st d_l ogi c_vect or ( 31 downt o 0) : = ( ot hers =>' 0' ) ;si gnal dat a_r om , r om_f f : st d_l ogi c_vect or ( 31 downt o 0) ;si gnal cl ock_mai n , r eset , enbl , cl ock : st d_l ogi c : = ' 0' ;si gnal c0 , c1 , c2 , c3 , c0_c1 , c2_c3 , c0_c2 , c1_c3 :st d_l ogi c ;si gnal

c0_and, c1_and, c2_and, c3_and, c0_c1and, c2_c3and, c0_c2and, c1_c3and :st d_l ogi c ;si gnal r eset _count : st d_l ogi c ;t ype st at e i s ( r eset 1 , r eset 2 , r eset 3 , r eset 4 , r eset 5 ,r eset 6 , r eset 7) ;

si gnal f i nal _sum : st d_l ogi c_vect or ( 31 downt o 0) : = ( ot her s =>' 0' ) ;s i gnal shi f t , f i ni sh_sum , s i gnbi t , nor mal i se , end_al l ,a_smal l , addsub , sum_out 2 , shi f t _done , done , num_r ec , setbi t, addpul se : st d_l ogi c : = ' 0' ;si gnal shi f t _out a , swap_num2 : st d_l ogi c_vect or ( 31 downt o 0 )

: = ( ot her s => ' 0' ) ;si gnal swap_num1 , sum_out : st d_l ogi c_vect or ( 32 downt o 0) : =( ot her s => ' 0' ) ;si gnal sub2 : st d_l ogi c_vect or ( 8 downt o 0) : = ( ot her s => ' 0' ) ;si gnal suba : st d_l ogi c_vect or ( 8 downt o 0) : = ( ot her s => ' 0' ) ;si gnal exp : st d_l ogi c_vect or ( 7 downt o 0) : = ( ot her s => ' 0' ) ;si gnal r st , enswap , ensub , enshi f t , f i nsub , f i nswap ,f i nshi f t , numzero : std_l ogi c : = ' 0' ;si gnal zer odet ect : st d_l ogi c_vect or ( 1 downt o 0) ;si gnal changea : st d_l ogi c ;

si gnal f i nal _sumb : st d_l ogi c_vect or ( 31 downt o 0) : = ( ot hers =>' 0' ) ;

si gnal shi f t b , f i ni sh_sumb , si gnbi t b , nor mal i seb , end_al l b ,a_smal l b , addsubb, sum_out2b , shi f t _doneb , doneb , num_r ecb ,set bi t b , addpul seb , cl ockb : st d_l ogi c : = ' 0' ;si gnal shi f t _out b , swap_num2b : st d_l ogi c_vect or ( 31 downt o 0 ): = ( ot her s => ' 0' ) ;si gnal swap_num1b , sum_out b : st d_l ogi c_vect or ( 32 downt o 0) : =( ot her s => ' 0' ) ;si gnal sub2b : st d_l ogi c_vect or ( 8 downt o 0) : = ( ot her s => ' 0' ) ;


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si gnal subb : st d_l ogi c_vect or ( 8 downt o 0) : = ( ot her s => ' 0' ) ;si gnal expb: st d_l ogi c_vect or ( 7 downt o 0) : = ( ot her s => ' 0' ) ;si gnal r st b , enswapb , ensubb , enshi f t b , f i nsubb , f i nswapb ,f i nshi f t b , numzer ob , cl ock_mai nb , r eset b , enbl b : st d_l ogi c: = ' 0' ;si gnal zer odet ect b : st d_l ogi c_vect or ( 1 downt o 0) ;

si gnal changeb : st d_l ogi c ;

si gnal i ncr , cl ear , i o_mode , st aged , i od : st d_l ogi c ;si gnalbutt er f l y, f f t add_rd, shi f t 1, shi f t 3, shi f t 4, shi f t 5, shi f t 6, ram_wr , r am

_r d, i o_add : st d_l ogi c_vect or ( 3 downt o 0) : = ( ot her s => ' 0' ) ;s i gnal f f t d , f f t _en , i p , op , i ni t : s td_ l ogi c ;si gnal st age : st d_l ogi c_vect or ( 1 downt o 0) ;- - si gnal cl ock_mai n, c0, c1, c2, c3, c0_c1, c2_c3, c0_c2, c1_c3 :st d_l ogi c ;si gnal pr eset , di sabl e, c0_en, r om_en, r omgen_en : st d_l ogi c ;si gnal cl k_count : st d_l ogi c_vect or ( 2 downt o 0) ;

si gnal enbw , enbor : st d_l ogi c ;si gnal dat a_i o : st d_l ogi c_vect or ( 31 downt o 0) : = ( ot her s => ' 0' );si gnal r om_add : st d_l ogi c_vect or( 2 downt o 0) ;t ype state_val ues i s ( st 0 , st 1 , st2 , st 3) ;si gnal pr es_st at e1 , next_st at e1 : st at e_val ues ;

si gnal but t er f l y_i od : st d_l ogi c_vect or ( 3 downt o 0) ;si gnal cyc_cl ear : std_l ogi c ;si gnal add_r d , add_wr : st d_l ogi c_vect or ( 3 downt o 0) ;

end but t er _l i b ;


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but.vhd- - BUTTERFLY GENERATORl i br ar y i eee ;use i eee. st d_l ogi c_1164. al l ;use i eee. std_ l ogi c_ar i t h. al l ;use wor k. but t er _ l i b. al l ;


ent i t y but _gen i spor t (

add_i ncr , add_cl ear , st agedone : i n st d_l ogi c ;but _but t er f l y : out st d_l ogi c_vect or ( 3 downt o 0) ) ;

end but _gen ;

ar chi t ecture r t l of but _gen i sbegi npr ocess( add_cl ear , add_i ncr , st agedone)var i abl e cnt : i nt eger ;

var i abl e count : st d_l ogi c_vect or ( 3 downt o 0) ;begi ni f ( add_cl ear = ' 1' or st agedone = ' 1' ) t hencount : = "0000" ;but_but t er f l y


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baseindex.vhd- - BASE I NDEX GENERATORl i br ar y i eee;use i eee. st d_l ogi c_1164. al l ;use wor k. but t er _ l i b. al l ;

ent i t y basei ndex i sport(

i nd_but t er f l y: i n st d_l ogi c_vect or ( 3 downt o 0) ;i nd_st age: i n st d_l ogi c_vect or ( 1 downt o 0) ;add_f f t : i n std_ l ogi c ;f f t add_r d: out st d_l ogi c_vect or ( 3 downt o 0) ;c0, c1, c2, c3: i n std_l ogi c);

end basei ndex;

ar chi t ecture r t l of basei ndex i sbegi npr ocess( i nd_but t er f l y, i nd_st age, add_f f t , c0, c1, c2, c3)

var i abl e out _si g : st d_l ogi c_vect or ( 3 downt o 0) ;begi ni f ( add_f f t =' 1' ) t heni f ( c2=' 1' ) t hen - - addr ess f or ' x' . Si nce t hi s i s t he r eal par t ,case i nd_st age i s - - M. S. B i s ' 0' .

when "00" => out _s i g : = "00" & i nd_but t er f l y( 1 downt o 0) ;when "01" => out _si g : = ' 0' & i nd_but t er f l y(1) & ' 0' &

i nd_but t er f l y( 0) ;- - when "10" => out _si g : = ' 0' & ' 1' & ' 1' & i nd_but t er f l y( 3) ;

when "10" => out_s i g : = ' 0' & i nd_but t er f l y( 1 downt o 0) & ' 0' ;when ot her s => out _si g : = "0000";

end case;

el si f ( c0=' 1' ) t hen - - addr ess f or ' y' .case i nd_st age i s

when "00" => out _s i g : = "01" & i nd_but t er f l y( 1 downto 0) ;when "01" => out _si g : = ' 0' & i nd_but t erf l y(1) & ' 1' &

i nd_but t er f l y( 0) ;when "10" => out _s i g : = ' 0' & i nd_but t erf l y( 1 downt o 0) & ' 1' ;when ot hers => out _si g : = "0000" ;

end case;

el si f ( c1=' 1' ) t hen - - addr esss f or ' Y'case i nd_st age i s

when "00" => out _s i g : = "11" & i nd_but t er f l y( 1 downto 0) ;

when "01" => out _si g : = ' 1' & i nd_but t erf l y(1) & ' 1' &i nd_but t er f l y( 0) ;

when "10" => out _s i g : = ' 1' & i nd_but t erf l y( 1 downt o 0) & ' 1' ;when ot hers => out _si g : = "0000" ;

end case;

el si f ( c3=' 1' ) t hen - - addr ess for ' X'case i nd_st age i s


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when "00" => out _si g : = "10" & i nd_but t er f l y( 1 downt o 0) ;when "01" => out _si g : = ' 1' & i nd_but t erf l y(1) & ' 0' &

i nd_but t er f l y( 0) ;when "10" => out _s i g : = ' 1' & i nd_but t erf l y( 1 downt o 0) & ' 0' ;when ot hers => out _si g : = "0000" ;

- - el se

- - out _si g : = "ZZZZ";end case;end i f ;end i f ;f f t add_r d


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c2

fft using vhdl

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