programs of vhdl

1

Program No. 1

Aim: Write a VHDL program to implement a 3:8 decoder.

Truth Table:

A B C EN D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 1 0 0 0 0 0 0 0

1 0 0 1 0 0 0 0 1 0 0 1

0 1 0 1 0 0 1 0 0 0 0 0

1 1 0 1 0 0 0 0 0 0 1 0

0 0 1 1 1 0 0 0 0 0 0 0

1 0 1 0 0 0 0 0 0 0 0 0

0 1 1 0 0 0 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0 0 0 1

0 0 0 1 1 0 0 0 0 0 0 0

Program:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity decoder is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

C : in STD_LOGIC;

EN : in STD_LOGIC;

D : out STD_LOGIC_VECTOR (0 to 7));

end decoder;

2

architecture Behavioral of decoder is

begin

process(A,B,C,EN)

variable ABAR,BBAR,CBAR:STD_LOGIC;

begin

ABAR :=NOT A;

BBAR :=NOT B;

CBAR :=NOT C;

if EN='1' then

D(0)<= ABAR AND BBAR AND CBAR;

D(1)<= ABAR AND BBAR AND C;

D(2)<= ABAR AND B AND CBAR;

D(3)<= ABAR AND B AND C;

D(4)<= A AND BBAR AND CBAR;

D(5)<= A AND BBAR AND C;

D(6)<= A AND B AND CBAR;

D(7)<= A AND B AND C;

else

D <= "00000000";

end if;

end process;

end Behavioral;

3

RTL Logic:

Output Waveform:

Result: VHDL Program of a 3 :8 decoder has been implemented

4

Program No. 2

Aim: Write a VHDL program to implement an 8:1 multiplexer.

Truth Table:

S0 S1 S2 A0 A1 A2 A3 A4 A5 A6 A7 Z

0 0 0 0 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 0 1 0

0 1 0 1 0 0 0 1 0 1 0 0

1 1 0 1 1 1 1 1 1 1 0 1

0 0 1 1 0 1 1 0 1 1 1 0

1 0 1 0 0 1 0 1 1 1 0 1

0 1 1 1 1 1 0 1 0 1 0 0

1 1 1 1 0 1 1 1 0 0 1 1

0 0 0 1 0 1 1 0 1 0 1 1

Program:-

library IEEE;





5


--library UNISIM;


entity Ramkrishna_MUX is

Port ( A : in STD_LOGIC_VECTOR (0 to 7);

S : in STD_LOGIC_VECTOR (0 to 2);

Z : out STD_LOGIC);

end Ramkrishna_MUX;

architecture Behavioral of Ramkrishna_MUX is

begin

process (S,A) is

begin

case S is

when "000" => Z<=A(0);

when "001" => Z<=A(1);

when "010" => Z<=A(2);

when "011" => Z<=A(3);

when "100" => Z<=A(4);

when "101" => Z<=A(5);

when "110" => Z<=A(6);

when "111" => Z<=A(7);

when others => Z<='X';

end case;

end process;

end Behavioral;

6

RTL Logic:

Output Waveform:

Result: VHDL Program of 8:1 multiplexer has been implemented using behavioral

modeling.

7

Program No: 3

Aim:- To write a VHDL program to implement a 1:8 demultiplexer.

Truth Table:-

A S2 S1 S0 Z0 Z4 Z2 Z6 Z1 Z5 Z3 Z7

0 0 0 0 0 0 0 0 0 0 0 0

1 1 0 0 - 1 1 1 1 1 1 1

0 0 1 0 - - 0 0 0 0 0 0

1 1 1 0 - - - 1 1 1 1 1

0 0 0 1 - - - - 0 0 0 0

1 1 0 1 - - - - - 1 1 1

0 0 1 1 - - - - - - 0 0

1 1 1 1 - - - - - - - 1

Program:-

library IEEE;






--library UNISIM;


entity DEMUX is

Port ( A : in STD_LOGIC;

S : in STD_LOGIC_VECTOR(0 TO 2);

Z : out STD_LOGIC_VECTOR(0 TO 7));

end DEMUX;

architecture Behavioral of DEMUX is

BEGIN

8

PROCESS(A,S)

BEGIN

CASE S IS

WHEN "000"=>Z(0)<=A;

WHEN "001"=>Z(1)<=A;

WHEN "010"=>Z(2)<=A;

WHEN "011"=>Z(3)<=A;

WHEN "100"=>Z(4)<=A;

WHEN "101"=>Z(5)<=A;

WHEN "110"=>Z(6)<=A;

WHEN "111"=>Z(7)<=A;

WHEN OTHERS=>Z<="XXXXXXXX";

END CASE;

END PROCESS;

end Behavioral;

9

RTL Diagram:-

Output Waveform:-

Result: A VHDL Program of 1 :8 demultiplexer has been implemented by behavioral

modeling.

10

Program No. 4

Aim: Write a VHDL program to implement 4-bit addition/subtraction.

Truth Table:

Program:

library IEEE;






--library UNISIM;


entity BIT_ADDER_SUB is

Port ( A : in STD_LOGIC_VECTOR (3 downto 0);

B : in STD_LOGIC_VECTOR (3 downto 0);

M : in STD_LOGIC;

C_IN : inout STD_LOGIC;

C_OUT : out STD_LOGIC;

S : out STD_LOGIC_VECTOR (3 downto 0));

end BIT_ADDER_SUB;

A0 A1 A2 A3 B0 B1 B2 B3 M CIN COUT S0 S1 S2 S3

0 1 0 0 0 0 0 0 1 1 1 0 1 0 0

0 0 1 0 1 0 0 0 0 0 0 1 1 0 0

0 1 1 0 1 1 0 0 1 1 1 1 0 0 0

0 0 0 1 1 0 1 0 0 0 0 1 1 1 0

0 1 0 1 1 1 1 0 1 1 1 1 0 0 0

0 0 1 1 1 0 0 1 0 0 0 1 1 1 1

11

architecture Behavioral of BIT_ADDER_SUB is

begin

PROCESS(A,B,M,C_IN)

VARIABLE C:STD_LOGIC_vector(0 to 3);

VARIABLE B0BAR,B1BAR,B2BAR,B3BAR:STD_LOGIC;

BEGIN

C_IN<=M;

B0BAR:=NOT B(0);

B1BAR:=NOT B(1);

B2BAR:=NOT B(2);

B3BAR:=NOT B(3);

IF M='0' THEN

C(0):=((A(0)AND B(0))OR (A(0)AND C_IN)OR (B(0) AND C_IN));

C(1):=((A(1) AND B(1)) OR (A(1) AND C(0)) OR (B(1) AND C(0)));

C(2):=((A(2) AND B(2)) OR (A(2) AND C(1)) OR (B(2) AND C(1)));

S(0)<=(A(0)XOR B(0) XOR C_IN);

S(1)<=(A(1) XOR B(1) XOR C(0));

S(2)<=(A(2) XOR B(2) XOR C(1));

S(3)<=(A(3) XOR B(3) XOR C(2));

C_OUT<=((A(3) AND B(3))OR (A(3) AND C(2)) OR (B(3) AND C(2)));

ELSE

C(0):=((A(0) AND B0BAR)OR (B0BAR AND C_IN)OR (A(0) AND C_IN));

C(1):=((A(1) AND B1BAR)OR (B1BAR AND C(0))OR (A(1) AND C(0)));

C(2):=((A(2) AND B2BAR) OR (B2BAR AND C(1)) OR (A(2) AND C(1)));

S(0)<=(A(0) XOR B0BAR XOR C_IN);

S(1)<=(A(1) XOR B1BAR XOR C(0));



12

C_OUT<=((A(3)AND B3BAR) OR (B3BAR AND C(2)) OR (A(3) AND C(2)));

END IF;

END PROCESS;

end Behavioral;

13

RTL Logic:

Output Waveform:

Result: VHDL Program to implement 4 bit addition/subtraction have been studied.

14

Program No: 5

Aim: Write a VHDL program to implement a 4-bit comparator.

Truth Table:

A0 A1 A2 A3 B0 B1 B2 B3 AGB AEB ALB

0 0 0 0 0 0 0 0 0 1 0

1 1 1 0 1 0 0 1 1 0 0

0 1 0 0 0 0 0 1 1 0 0

1 0 0 1 1 0 0 1 0 1 0

0 1 0 1 1 0 1 0 0 0 1

0 0 1 1 1 1 1 0 0 0 1

1 0 1 0 1 0 1 0 0 1 0

1 1 1 0 1 0 0 1 1 0 0

0 1 1 0 1 0 0 0 0 0 1

Program:

library IEEE;






--library UNISIM;


entity COMPARATOR is

Port ( A : in STD_LOGIC_VECTOR (0 to 3);

B : in STD_LOGIC_VECTOR (0 to 3);

AGB : out STD_LOGIC;

AEB : out STD_LOGIC;

ALB : out STD_LOGIC);

end COMPARATOR;

15

architecture Behavioral of COMPARATOR is

begin

PROCESS(A,B)

BEGIN

IF A>B THEN

AGB <='1';

AEB <='0';

ALB <='0';

ELSIF A=B THEN

AGB<='0';

AEB<='1';

ALB<='0';

ELSIF A<B THEN

AGB<='0';

AEB<='0';

ALB<='1';

END IF;

END PROCESS;

END BEHAVIORAL;

16

RTL Logic:

Output Waveform:

Result: A VHDL Program of 4 bit comparator has been implemented.

17

Program No: 6

Aim: Write a VHDL program to implement MOD-10 counter.

Truth Table:

SLOAD CLR Q0 Q1 Q2 Q3

1 1 0 0 0 0

1 0 0 0 0 1

1 0 0 0 1 0

1 0 0 0 1 1

1 0 0 1 0 0

1 0 0 1 0 1

1 0 0 1 1 0

1 0 0 1 1 1

1 0 1 0 0 0

1 0 1 0 0 1

1 0 0 0 0 0

1 0 0 0 0 1

Program:

library IEEE;




18



--library UNISIM;


entity MOD_10 is

Port ( CLK : in STD_LOGIC;

SLOAD : in STD_LOGIC;

CLR : in STD_LOGIC;

Q : out STD_LOGIC_VECTOR (0 to 3));

end MOD_10;

architecture Behavioral of MOD_10 is

SIGNAL TEMP:STD_LOGIC_VECTOR(0 TO 3);

begin

PROCESS (CLK) IS

BEGIN

IF (CLK'EVENT AND CLK='1') THEN

IF CLR='1' THEN

TEMP <= "0000";

ELSIF SLOAD ='1' THEN

IF TEMP="1001" THEN

TEMP<= "0000";

ELSE TEMP<=TEMP+"0001";

END IF;

END IF;

END IF;

END PROCESS;

Q<=TEMP;

END BEHAVIORAL;

19

RTL Logic:

Output Waveform:

Result: A VHDL Program to generate Mod- 10 up counter has been implemented.

20

Program No. 7

Aim: To write a VHDL program to generate the 1010 sequence detector.

Truth Table:

X Z

0 0

0 0

0 0

0 0

1 0

0 0

1 0

0 1

0 0

0 0

0 0

Program:

library IEEE;






--library UNISIM;


entity SEQ_DETECTOR is

Port ( X : in STD_LOGIC;

21

CLK : in STD_LOGIC;

Z : out STD_LOGIC);

end SEQ_DETECTOR;

architecture Behavioral of SEQ_DETECTOR is

TYPE STATE_TYPE IS (S0,S1,S2,S3);

SIGNAL CURRENT_STATE,NEXT_STATE:STATE_TYPE;

BEGIN

PROCESS(CURRENT_STATE,X)

begin

CASE CURRENT_STATE IS

WHEN S0=>

IF X='0' THEN

Z<='0';

NEXT_STATE<= S0;

ELSIF X='1' THEN

Z<='0';

NEXT_STATE <=S1;

ELSE

Z<='0';

NEXT_STATE <=S0;

END IF;

WHEN S1=>

IF X='0' THEN

Z<='0';

NEXT_STATE <= S2;

ELSIF X='1' THEN

Z<='0';

NEXT_STATE <=S1;

ELSE Z<= '0';

22

NEXT_STATE <=S0;

END IF;

WHEN S2=>

IF X='0' THEN

Z<='0';

NEXT_STATE<= S0;

ELSIF X='1' THEN

Z<='0';

NEXT_STATE<=S3;

ELSE

Z<='0';

NEXT_STATE <=S0;

END IF;

WHEN S3=>

IF X='0' THEN

Z<='1';

NEXT_STATE<= S1;

ELSIF X='1' THEN

Z<='1';

NEXT_STATE<=S0;

ELSE Z<='0';

NEXT_STATE<=S0;

END IF;

END CASE;

WAIT UNTIL CLK='1'AND CLK'EVENT;

CURRENT_STATE<=NEXT_STATE;

END PROCESS;

end Behavioral;

23

RTL Logic:

Output Waveform:

Result: A VHDL Program to generate the 1010 sequence detector has been studied.

24

Program No. 8

Aim: To write a VHDL program to perform serial to parallel transfer of 4-

bit binary number.

Truth Table:

CLR PR DIN Y(0) Y(1) Y(2) Y(3)

1 1 1 - - - -

1 1 0 1 - - -

1 1 1 0 1 - -

1 1 0 1 0 1 -

1 1 1 0 1 0 1

1 1 0 1 0 1 0

1 1 1 0 1 0 1

1 1 0 1 0 1 0

1 1 1 0 1 0 1

Program:

library IEEE;






--library UNISIM;


entity SIPO is

Port ( D : in STD_LOGIC;

CLR : in STD_LOGIC;

CLK : in STD_LOGIC;

25

PR : in STD_LOGIC;

Y : out STD_LOGIC_VECTOR(0 TO 3));

end SIPO;

architecture Behavioral of SIPO is

SIGNAL A:STD_LOGIC_VECTOR(0 TO 3);

begin

PROCESS(CLR,CLK,PR,D)

BEGIN

IF(CLR='1' AND PR='1' AND CLK='1' AND CLK'EVENT)THEN

A(0)<=D;

A(1)<=A(0);

A(2)<=A(1);

A(3)<=A(2);

Y<=A;

ELSIF(CLR='1' AND PR='0')THEN

Y<="1111";

ELSIF (CLR='0' AND PR='1')THEN

Y<="0000";

END IF;

END PROCESS;

end Behavioral;

26

RTL LOGIC:

Output Waveform:

Result: A VHDL program of serial to parallel transfer of 4 bit binary number has been

verified.

27

Program No. 9

Aim: To write a program to perform parallel to serial transfer of 4-bit binary

number.

Truth Table:

Din Clk

Load Dout

0 1 1 -

0 0 0 0

1 1 1 0

1 0 0 1

2 1 1 0

2 0 0 2

3 1 1 0

3 0 0 3

Program:

library IEEE;






--library UNISIM;


entity PISO is

Port ( din : in STD_LOGIC_VECTOR (3 downto 0);

load_shtbar : in STD_LOGIC;

clk : in STD_LOGIC;

dout : out STD_LOGIC);

28

end PISO;

architecture Behavioral of PISO is

signal sr_bit:std_logic_vector(3 downto 0):="0000";

begin

process(clk)

begin

if (clk='1' and clk'event)then

if(load_shtbar ='1')then

sr_bit <=din;

else

sr_bit<='0'& sr_bit(3 downto 1);

end if;

dout<=sr_bit(0);

end if;

end process;

end Behavioral;

29

RTL Logic:

Output Waveform

Result: A VHDL program of parallel to serial transfer of 4 bit binary number has been

verified.

30

Program No: 10

Aim: Write a VHDL program to implement BCD to Seven segments

Decoder.

Truth Table:

BCD

0

BCD

1

BCD

2

BCD

3

LED

0

LED

1

LED

2

LED

3

LED

4

LED

5

LED

6

0 0 0 0 0 1 1 1 1 1 1

1 0 0 0 1 1 1 1 1 1 1

0 1 0 0 1 1 0 0 1 1 0

1 1 0 0 0 0 0 0 0 0 0

0 0 1 0 1 0 1 1 0 1 1

1 0 1 0 0 0 0 0 0 0 0

0 1 1 0 1 1 1 1 1 0 1

1 1 1 0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0 1 1 0

Program:

library IEEE;






--library UNISIM;


entity BCD_7SEGMENT is

Port ( BCD : in STD_LOGIC_VECTOR (3 downto 0);

LED : out STD_LOGIC_VECTOR (6 downto 0));

31

end BCD_7SEGMENT;

architecture Behavioral of BCD_7SEGMENT is

BEGIN

PROCESS(BCD)IS

begin

CASE BCD IS

WHEN "0000"=>LED<="1111110";

WHEN "0001"=>LED<="0110000";

WHEN "0010"=>LED<="1101101";

WHEN "0011"=>LED<="1111001";

WHEN "0100"=>LED<="0110011";

WHEN "0101"=>LED<="1011011";

WHEN "0110"=>LED<="1011111";

WHEN "0111"=>LED<="1110000";

WHEN "1000"=>LED<="1111111";

WHEN "1001"=>LED<="1111011";

WHEN OTHERS=>LED<="0000000";

END CASE;

END PROCESS;

end Behavioral;

32

RTL Logic:

Output Waveform:

Result: A VHDL Program of BCD to SEVEN SEGMENT display has been

implemented.

33

Program No. 11

Aim: Write a program to convert 8 bit vector into an integer.

Truth Table:

Program:

library IEEE;






--library UNISIM;


entity CONVERTOR is

Port ( A : in BIT_VECTOR (0 to 7);

OP : out INTEGER RANGE 0 to 255);

end CONVERTOR;

A3 A2 A1 A0 S0 S1 S2 S3 S4 S5 S6

0 0 0 0 0 1 1 1 1 1 1

0 0 0 1 0 1 1 0 0 0 0

0 0 1 0 1 1 0 1 1 0 1

0 0 1 1 1 1 1 1 0 0 1

0 1 0 0 0 1 1 0 0 1 1

0 1 0 1 1 0 1 1 0 1 1

0 1 1 0 0 0 1 1 1 1 1

0 1 1 1 1 1 1 0 0 0 0

1 0 0 0 1 1 1 1 1 1 1

1 0 0 1 1 1 1 0 0 1 1

* * * * 0 1 1 1 1 1 1

34

architecture Behavioral of CONVERTOR is

IMPURE FUNCTION CONV(X:BIT_VECTOR(0 TO 7))

RETURN INTEGER IS

VARIABLE T:INTEGER;

begin

T:=0;

FOR I IN 0 TO 7 LOOP

IF A(I)='1' THEN

T:=T+2**I;

END IF;

END LOOP;

RETURN T;

END FUNCTION CONV;

BEGIN

OP<=CONV(A);

end Behavioral;

35

RTL Logic:

WAVEFORM:

RESULT: A program to convert 8 bit vector into an integer have been studied.

programs of vhdl

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