frequency synthesizer final report

7/30/2019 Frequency Synthesizer Final Report

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Frequency Synthesizer for GSM-900

Group Project for ECE802-607

Instructor : Salem, Fathi M

Group member: Green, ElwoodVelez, Dalimar

Yang, ChaoZiel, Stephen Allen

Design summary.(Directory: /egr/course/personal/ece802/finalproject/PLL)

Sub design Library name Status designer

system design PLL Simulation & schematic Done Chao

PFD&CP&LPF PLL Schematic & Simulation Done

Layout Done

Chao

VCO VCO Schematic & simulation done.

on chip inductor done.

Stephen

Divider Divider Schematic & simulation done.

Layout is partially finished.

Dalimar

Elwood


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INTRODUCTION

1. Target of the projectThe target of this project is to design a Frequency synthesizer used in a GSM-900

system, including the schematic design as well as layout design. AMI 0.5um CMOS

process is the targeted technology to realize this design.2. Frequency SynthesizerFrequency Synthesizer is used to generate variety of frequency or realize

modulation for many applications. It is built with Phase Locked Loop (PLL). Thus, for

most of the case, PLL and Frequency Synthesizer have the same meaning. Typical PLL

structure is shown below:

PFDCharge

pump

LPF2nd order VCO

Counter

Figure.1 Block diagram of PLL system

A feedback loop forces the output to track the input reference phase so

that the output frequency loop is locked. Based on different configurations in the loop.

The PLL can be categorized into following table.

Table.1 PLL categorization

For many wireless communication applications, Digital PLL are adopted, becauseit can provide high frequency output and easy to be designed.

3. GSM-900MHz system

GSM is the most popular cellphone protocols. GMS-900 is a subset of GSMnetwork. GSM-900 uses 890 - 915 MHz to send information from the and 935 - 960 MHzfor the other direction, providing 124 RF channels spaced at 200 kHz. Duplex spacing of

45 MHz is used.

4. design approach.


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For simplicity, the integer-N PLL is adopted. other targeted

parameters are list in table-1

Reference

Frequency

200KHz

Loop bandwidth 20KHzVCO gain 40MHz/Volts

Prescalor Two modulus 8/9

Charge PumpCurrent

100uA

order of LPF 2nd

order

Frequency

range

890MHz-915MHz (124

Channel)


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Design Report

s y s t em s i m u l a t i o n The PLL was modeled and simulated to test its stability and locking time.

Figure.2 shows the behavioral model of the PLL.The parameters in the model is described in the following table

Icp 100uA

C1 14p

C2 211p

R2 155K

K0 40MHz/Volts

Divider radio 4500

The simulation result was shown below:

(a) (b)Figure.2 models of PLL, (a) close loop, (b) open loop

Figure. xxxx (a) freqnency response of open loop structure(b) frequency response of close loop structure

(c) step response of close loop structure.


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Simulation result shows that

Bandwidth: 20KHz

Looking time:100usPhase Margin: 60

PFDThe PFD was realized in a digital way. additional delay was inserted in the

feedback .The circuit is shown in figure.3

figure.3 PFD schematic

figure.4 simulation result of the pfd.

figure. 5 layout of the pfd.


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C h a rg e P um p & LP F.

The chcare pump use current mirror to generate sourcing current & sink current of

100uA. For the LPF, the samll capacitor of 15pF was put onchip. The larger one (211pF)was palced offchip. A external pin was claimed for it. Figure.5 shows the schematic of

Charge Pump and LPF.

Figure.5 schematic of charge pump and LPF.

Figure. 6 layout of schematic.


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Vo l t a g e C on t r o l l e d O s c i l l a t o r

Theory

A typical CMOS voltage controlled oscillator can be seen in figure one below. It consistsof two NMOS and two PMOS transistors hooked up in a negative resistance formation,

which can be modeled as shown in figure two. If both the PMOS and NMOS have thesame gm, then figure three shows the final equivalent circuit, which can be modeled as a

simple RLC tank. All three of these models are using the small signal equivalent model

for the MOSFET analysis.

C1 and C2 really represent MOSFET varactors, where the drain, source (and sometimes,

but not always) the bulk nodes are tied together. In this configuration, the bulk node of

an NMOS would act as the VCTRL pin (to prevent reverse biasing of the internal diodes),and the gate node would act as the output connection. An analysis of this circuit can

show that when the drain and source are tied together, ID is shorted out, and the transistor

is in cutoff. This can be shown visually by using the high frequency model [1].

Figure 1: Typical

VCO Schematic

Figure 2:

Equivalent

circuit of fig. 1

Figure 2: Final

RLC Equivalent

circuit

Figure 4: High Frequency model

for the MOSFET transistor


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Using this high frequency model, one can derive the expected equivalent capacitance as

follows:

1.) Drain and source tied together; bulk connected to VCONTROL.

++

+= GSGDBSBD

GBTOTAL

CCCCCC 11//

( )( )

+++++

GSGDBSBD

BSBDGSGDGB

CCCC

CCCCC //

EquivalentGB CC //

Therefore, in this configuration it can be seen that CGB is the biggest contributer to theoverall capacitance because CEquivalent comprises of capacitive dividers due to the rest of

the parasitic capacitances of the MOSFET.

2.) Drain, source and bulk all tied together, which are then connected to VCONTROL.

GDGSGB

GDGSGBTOTAL

CCCCCCC

++=

1////

The other capacitances do not show up in this equation because they are all shorted out.

For this project, the first configuration was used, however the above derivations show

that both configurations will work as a variable capacitor.

Resul ts

For this project, we were required to meet the specifications of a GSM receiver. A VCOoperating under these conditions must be able to acquire a tuning frequency from the

range of 890 MHz to 915 MHz. The results of our VCO are shown on the next page.

The extra circuitry to the right of the VCO (N19 and V2) were merely to cause oscillation

in the circuit by offsetting the circuit during initial conditions, thanks to the advice ofProfessor Salem.

Table 1: VCO Transistor Sizes


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Figure 6: FFT Analysis on VCO Circuit

Figure 5: Final VCO Circuit


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The inductor was realized using the ASITIC software. A screenshot, along with its

various characteristics, can be seen below.

Figure 7: Plotted results comparing Vctrl to the frequency of the VCO

Figure 8: Layout of on-chip Inductor

Table 2: ASITIC Inductor Parameters


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F re q u e n c y D iv i d e r

Theory:

The frequency divider divides the output frequency of the VCO until it is

comparable to the reference frequency. The frequency divider closes the feedback path

between the output of the VCO and the phase and frequency detector. The feedback loop

makes possible that the VCO will eventually lock on a multiple of the reference signal.

Figure 1 represents a block diagram of a synthesizer with a frequency divider of ratio .

Using this figure it is determined that the relation of the output and reference frequency

is:

refout fMf *= where M is the division ratio.

) RXW3) ' / 3) 9&2

) UHTXHQF\

' LYLGHU

) UHI

Figure 3: Block diagram of Frequency synthesizer

The frequency divider is implemented using an integer-N architecture as shown in

figure 2. This consists of a dual-modulus prescaler with two parts counter. The two

counters are the program counter and swallow counter. The prescaler divides by

1+N until the swallow counter has counted S cycles. At this point the swallow counter

changes the state of the Modulus control to set the prescaler in divide by mode. After

this change the program counter continues counting until it reaches P cycles. In other

words, the program counter already count S cycles and needs SP cycles at the input,

to reach to P pulses. Expressing the above discussion mathematically, the total number

of VCO cycles for one dual modulus division is:


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PNSNSPNSM +=++= *)())1(*(

(eq.1)

Frequency toPFD

ProgramCounter

%P

Swallow

Counter

%S

Dual ModulusPrescalar

%N/(N+1)

Frequencyfrom VCO

Modulus

ControlReset

Bit Control

Figure 4: Integer N frequency divider

Design:

The frequency divider will operate at the GSM protocols to send information. The

transmit frequency range for this protocol is between 890 MHz to 915 MHz. We have124 RF channels spaced at 200 kHz.

In the design process we choose the dual modulus prescaler to be 8/9. Then S will

count until the number of channels in this case is 124 cycles. P is calculated using

equation 1 when S is 1 and 125 respectively. The following steps calculate P:

a) refout fMf *= , where M have lowM and highM .

4450200

890==

kHz

MHzMlow 4575

200

915==

kHz

MHzMhigh

b) Use equation 1:

55645758*)125()9*125(then125

55644508*)1()9*1(then1

==+=

==+=

PPS

PPS


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Table 1 shows a summary of the design specification for the frequency divider.

Prescaler N/(N+1) = 8/9

Program Counter 556

Swallow counter 1 to 125

Table 2: Summary of frequency divider specifications

Dual Modulus Prescaler:

The dual modulus prescaler (DMP) is a simple way of implementing a high

frequency division. In our case N=8 and the circuit was designed to divide by 9 when the

modulus control is low, and by 8 when modulus control is high. The implementation of

the DMP was achieved using four flip-flops with some gate logic. The prescaler consists

of a 2/3 synchronous divider with asynchronous divider circuit. In order to achieve high

speed, the current mode logic (CML) is preferred to static CMOS logic. In this case

differential signals are used at both input and output signals. Figure 3 and Figure 4 are

some of the CML circuits, Dlatch and And/Or gate. The And/Or gate is the same circuit,

but with a different configuration, you can get the 4 operations (AND, NAND, OR,

NOR). For example if you want the operation of OR, the inputs are A and B, and the

output is OUT. This can be shown in Figure 5.

Figure 5: Dlacth schematic


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Figure 6: And/Or gate schematic

Figure 7: Simulation of the And/Or gate


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The DMP schematic is shown in Figure 6. From the Figure 7 you can count the cycles of

the clock to verify the function but if you use the markers A and B, take the delta anddivide by the period, you get the number of cycles. For the simulation the circuit is

running with a frequency of 900 MHz or a period of 1.1 ns. In Figure 7a, the cycles are

8.8ns/1.1ns = 8 cycles and in part b 9.9ns/1.1ns = 9 cycles.

Figure 8: DMP 8/9 Schematic

Figure 9: Results of DMP, a) MC = 1, b)MC = 0


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Program counter:

Program counter is responsible for counting P pulses of output of the prescaler

before outputting a pulse to the phase and frequency detector and resetting itself and the

swallow counter. This program counter will receive frequencies up to 114 MHz. The

program counter will count until 556 so we need 10 bit to implement the circuit. The

circuit uses 10 D Flip-flops and some logic gates to compare the counting with the

desired number, in this case 556. When the circuit reaches 556, it will have a pulse in the

output to the phase and frequency detector, but the same output is the reset for the

swallow counter and the DMP. The schematic circuit is in Figure 8.

Figure 8: Program counter schematic


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Swallow counter:

The swallow counter, or channel-spacing counter, will count until 125. This input

of 7 bits is controlled from the outside; it can be a microprocessor. The circuit uses 7 D

Flip-flops and some logic gates (XOR, NAND, OR) to compare the counting with the

desired number. When the circuit reaches the desires bits, it will change the state of the

modulus control in order to change the prescaler. After that the swallow counter waits to

be reset from the Program counter. The schematic circuit is in Figure 9 and the resulting

simulations are in Figure 10.

Figure 9: Swallow counter schematic


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Figure 10: Swallow counter schematic


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Conclusion and further work

A PLL working at 890-915MHz was developed in this project. Only one external

capacitor was used. All other components are realized on-chip. In the future,

following improvement might be made:

1. Try to integrated the off-chip capacitor on to the chip. (using MOS cap or

capacitor multiplier)

2. Use fractional-N instead of integer-N structure to get better noise performance.


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Reference

[1] Gray, Hurst, Lewis, and Meyer, Analysis and Design of Analog Integrated

Circuits, 4th

edition, pp. 55.[2] M. Rachedine, D. Kaczman, A. Das, M. Shah, J. Mondal, and C. Shurboff,

Performance Review of Integrated CMOS VCO Circuits for WirelessCommunications,IEEE Radio Frequency Integrated Circuits Symposium, pp.77

80, 2003.[3] P. Andreani and S. Mattisson, On the Use of MOS Varactors in RF VCOs,

IEEE Journal of Solid-State Circuits, pp.905 910, June, 2000.

[4] K. Waheed, K. Desai, F. Salem, A Low Power Frequency Synthesizer with anIntegrated Negative Transconductance LC-Tuned VCO,Proc. IEEE

International Conference on Robotics, Intelligent Systems and Signal Processing,

Changsha, China, October, 2003.[5] B. Razavi, RF Microelectronics, Upper Saddle River: Prentice Hall, Inc., 1998.

[6] A.S. Sedra and K.C. Smith, Microelectronic Circuits, Oxford: Oxford University

Press, 1998.[7] T. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd edition

Cambridge University Press, 2004.

[8] M. Houlgate, A Frequency Synthesizer for a Radio-Over-Fiber Receiver,

Carleton University, April 2003.[9] R, Desikachari, High-Speed CMOS Dual Modulus Prescalers for Frequency

Synthesis, PhD. Thesis, Oregon State University, 2003

frequency synthesizer final report

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