frequency synthesizer for zigbee transceiver
TRANSCRIPT
CHAPTER 1INTRODUCTION
1.1 Background and Motivation
The need for ubiquitous mobile computing and networking has lead to the
development of various wireless standards by the Institute of Electrical and Electronics
Engineers (IEEE) in consortium with the industry over the last decade. The development of
such standards has lead to a complete revolution in the wireless segment by spurring on an
exponential growth in the semiconductor and communications industry. Examples of such
standards include Bluetooth, IEEE 802.11 a/b/g, Ultra wide-band (UWB), etc. It merits
mention that each standard caters to a different application and has an altogether different
design focus.
The IEEE 802.15.4/ Zigbee standard [1] has been recently developed to cater to the
needs of low cost, low power, low data rate, and short range wireless networks. This new
standard is specifically intended for applications pertaining to data monitoring, industrial
control and sensor networks. The thesis focuses on the design of a frequency synthesizer for a
2.4 GHz IEEE 802.15.4/Zigbee transceiver.
A frequency synthesizer (FS) is a device that generates one or many frequencies from
one or a few frequency sources. The output of an FS is characterized by its frequency tuning
range, frequency resolution, and frequency purity. Ideally, the synthesized signal is a pure
sinusoidal waveform. But in reality, its power spectrum features a peak at the desired
frequency and tails on both sides. The uncertainty of a synthesizer’s output is characterized
by its phase noise (or spur level) at a certain frequency offset from the desired carrier
frequency in unit of dBc/Hz.
The design of a monolithic solution of a low power, high-performance frequency
synthesizer in CMOS is the main challenge. Implementation of the synthesizer in a
transceiver environment leads to additional design considerations and evaluation of non-ideal
ties. It is shown that careful planning at the system level of the synthesizer can lead to high-
performance realizations. The frequency planning of the transceiver also plays a key role in 1
the development of the synthesizer. Further, it can be seen that a similar design approach be
followed for the implementation of synthesizers for other wireless transceivers.
1.2 Thesis Organization
The whole thesis is organized in seven chapters.
Chapter 1 gives Background and Motivation.
Chapter 2 forms the theoretical base for the synthesizer design. This chapter explains
fundamental principles of phase-locked loop and describes various synthesizer types. It also
explains some of the architectures of PFD, Charge Pump, VCO and divider. Phase noise
analysis of VCO is also presented.
Chapter 3 begins with the need for the IEEE 802.15.4/Zigbee standard and a comparative
study with the existing standards of Bluetooth, IEEE 802.11a/b/g and UWB. The architecture
of the entire transceiver is given and the important specifications for the synthesizer have
been derived from the standard. The architecture chosen for the particular implementation of
this synthesizer in a transceiver environment is provided. Moreover, a detailed system level
design procedure with stability and settling time considerations aids in understanding the
system level issues of the synthesizer better. A literature survey of synthesizer
implementation for transceiver is provided at 2.4 GHz. The survey helps us in understanding
the bottlenecks and performance oriented goals for a successful design better.
Chapter 4 explains system level specifications and derives specifications of the PLL sub-
blocks.
Chapter 5 forms the crux of this thesis and deals with the practical design and implementation
of a frequency synthesizer in a UMC 180nm Technology.
Chapter 6 includes the simulation results for the synthesizer and its components.
Chapter 7 gives Conclusions.
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CHAPTER 2LITERATURE SURVEY
2. Phase Locked Loop Fundamentals
Phase locked loops (PLLs) generate well-timed on-chip clocks for various
applications such as clock-and-data recovery, microprocessor clock generation and frequency
synthesizer. The basic concept of phase locking has remained the same since its invention in
the 1930s. However, design and implementation of PLLs continue to be challenging as
design requirements of a PLL such as settling and low phase noise become more stringent. A
large part of this thesis focuses on the design of a PLL for high performance digital systems.
In order to understand the challenges and trade-off behind the design of such a PLL, this
chapter provides a brief study of Phase locked loops.
2.1 Introduction to PLL
The basic block diagram of a PLL is shown in Figure 1. A PLL is a closed-loop
feedback system that sets fixed phase relationship between its output clock phase and the
phase of a reference clock. A PLL tracks the phase changes that are within the bandwidth of
the PLL. A PLL also multiplies a low-frequency reference clock, f ref, to produce a high
frequency signal, fout.
Figure 1: Basic block diagram of PLL
The basic operation of a PLL is as follows. The phase frequency detector produces an
error output signal based on the phase difference or frequency difference between the
feedback signal from divider output and the reference signal. Over time, small frequency
differences accumulate as an increasing phase error. The difference or error signal is low pass
filtered and drives the oscillator. The filtered error signal acts as a control signal (voltage or
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current) of the oscillator and adjusts the frequency of oscillation to align φdiv with φref . The
frequency of oscillation is divided down to the feedback signal by a frequency divider. The
phase is locked when the feedback signal has a constant phase error and the same frequency
as the reference clock. Because the feedback signal is a divided version of the oscillator’s
signal frequency, the frequency of oscillation is N times the reference signal.
2.2 PLL Components
The block diagram of a charge-pump PLL [2] is shown in Figure 2. A PLL comprises
of several components: (1) phase frequency detector, (2) charge-pump, (3) loop filter, (4)
voltage-controlled oscillator, and (5) frequency divider. The functioning of each block is
briefly described below.
Figure 2: Individual Blocks of PLL.
2.2.1 Phase Frequency Detector
A phase detector is a circuit whose average output, Vout, is linearly proportional to the
phase difference, ∆Φ, between its two inputs (Fig 3). In the ideal case, the relationship
between Vout and ∆Φ is linear, crossing the origin for ∆Φ = 0. Called the “gain” of the PD, the
slope of the line, KPD, is expressed in V/rad.
Figure 3: Definition of phase detector
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A familiar example of phase detector is the exclusive OR (XOR) gate. As shown in Fig4, as
the phase difference between the inputs varies, so does the width of the output pulses, thereby
providing a dc level proportional to ∆Φ. While the detector XOR circuit produces error
pulses on both rising and falling edges, other types of phase detectors may respond only to
positive or negative transitions.
Figure 4: Exclusive OR gate as phase detector
2.2.1.a. Problem of Lock Acquisition
Suppose when a PLL circuit is turned on, its oscillator operates at a frequency far
from the input frequency, i.e., the loop is not locked. The transition of the loop from unlocked
to locked condition is a very nonlinear phenomenon because the phase detector senses
unequal frequencies. The “acquisition range” is on the order of WLPF, that is, the loop locks
only if the difference between win and Wout is less than roughly WLPF. In type-I PLL, if WLPF
is reduced to suppress the ripple on the control voltage, the acquisition range decreases.
In order to remedy the acquisition problem [2], modern PLLs incorporate frequency
detection in addition to phase detection. Called ‘aided acquisition” and illustrated in Fig.5,
the idea is to compare Win and Wout by means of a frequency detector, generate a dc
component VLPF2 proportional to Win-Wout, and apply the result to the VCO in a negative
feedback loop. At the beginning, the FD drives Wout towards Win while PD output remains
“quiet”. When is sufficiently small, the phase-locked loop takes over, acquiring
lock. Such a scheme increases the acquisition range to the tuning range of the VCO.
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Figure 5: Addition of frequency detection to increase the acquisition range.
For periodic signals, it is possible to merge the two loops of Fig5. by devising a circuit that
can detect both phase and frequency differences called a phase/frequency detector (PFD) and
illustrated conceptually in Fig.6, the circuit employs sequential logic to create three states and respond
to the rising (or falling) edges of the two inputs. If initially QA = QB = 0, then a rising transition on A
leads to QA = 1, QB = 0. The circuit remains in this state until B goes high, at which point QA returns
to zero. The behaviour is similar for the B input. The outputs QA and QB are called the “UP” and
“DOWN” pulses, respectively.
Figure 6: conceptual operation of a PFD.
The circuit of Fig.6 can be realized in various forms. Fig.7 Shows a simple
implementation consisting of two edge-triggered, resettable D flip-flops with their D inputs
tied to a logic ONE. The inputs of interest, A and B, serve as the clocks of the flip-flops. If
QA = QB = 0 and A goes high, QA rises. If this event is followed by a rising transition on B,
QB goes high and the AND gate resets both flip-flops. In other words, QA and QB are
simultaneously high for a short time but the difference between their average values still
represents the input phase or frequency difference correctly.
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Figure 7: Implementation of PFD
State diagram of PFD.
The input-output characteristics of the above PFD [2] can be plotted as shown in Fig8.
Defining the output as the difference between the average values of QA and QB when WA =
WB and neglecting the effect of the narrow reset pulses, it can be noted that the output varies
symmetrically as begins from zero. For ∆Φ = ± 360o, Vout reaches its maximum or
minimum and subsequently change sign.
Figure 8: Input-output characteristic of the three-state PFD.
The primary advantages of the phase detector architectures shown in Figure 7 are its
size and simplicity. Unlike the classic architecture and the four RS latch architecture which
require 9 and 10 standard cells, respectively, to construct, this architecture requires only 5
cells, two for each flip-flop and one for the AND gate. In addition, the behavior of this phase
detector is conceptually simpler. Consider the case where the reference signal is leading the
feedback signal. When the reference signal transitions high, the associated flip-flop is
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clocked, causing the high signal on its data input to be passed through to its output. This
corresponds with the Up output signal being asserted. The delay before the output transitions is equal
to the flip-flop clock-to-Q delay. This signal will now stay high regardless of what the reference
signal does until the phase detector's state is reset. Next, the feedback signal clocks the second flip-
flop, causing the Dn output to be asserted. When the Dn output asserts, the AND gate will cause both
flipflops to be reset, thus resetting the state of the whole phase detector. The length of time for which
both outputs will be asserted is equal to one gate delay plus the flip-flop reset-to-Q delay. Assuming
the same limiting case as for the previous architectures, the maximum operating frequency for this
phase detector will be
……………………………..(2.1)
The flip-flops used with this design must accept an asynchronous reset signal. Also, the type
of flip-flop used will generally have an all-overriding reset, meaning that its output cannot be asserted
as long as the reset signal is high.
2.2.1. b Dead Zone
One of the disadvantages that PFD suffers is dead-zone. Dead-zone is a small
difference in the phase of the inputs that a PFD will not be able to detect. Dead zone is due to
the delay time of the logic components and reset of the feedback path of the flip flops.
Figure9 illustrates the dead zone problem. When the two clocks are very close to each
other (small phase error),due to the delay time the reset delay, the output signals UP and
DOWN will not be able to charge and no output will signal leading to losing this small
difference.
s
Figure 9: Dead Zone
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Fig 10 illustrates the output voltage of the charge pump vs. the phase error measured by the
PFD. Figure 10(a) illustrates the relation in no dead zone PDFs, while figure 10(b) illustrates
the relation in the presence of a dead zone. We can see that in a dead zone PFDs the relation
become nonlinear around zero. This is due to inability to detect the phase error in this region.
Plenty of solution has been done for this problem some of them reduce the delay time in the
internal components of the PFDs, other solution eliminate the reset path by implementing
new reset techniques that will not create a delay and produce a high speed PFDs.
Figure 10: Phase Error vs. Output Voltage
2.2.2 Charge pump
The output of a PFD can be converted to DC (voltage/current) in many different
ways. Since the difference between the average values of QA and QB is of interest, the two
outputs can be low-pass filtered and sensed differentially, as shown in figure 11.
Figure 11: PFD followed by low-pass filters.
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A more common approach [2] is to interpose a “charge pump” (CP) between the PFD
and the loop filter. A charge pump consists of two switched current sources that pump charge
into or out of the loop according to two logical inputs. Figure 12 illustrates a charge pump
driven by a PFD and driving a capacitor. The circuit has three states. If QA = QB = 0, then S1
and S2 are off and Vout remains constant. If QA is high and QB is low, then I1 charges CP.
Conversely, if QA is low and QB is high, then I2 discharges CP. Thus if, for example, A leads
B, then QA continues to produce pulses and Vout rises steadily, called UP and DOWN
currents, respectively, I1 and I2 are nominally equal.
Figure 12: PFD with charge pump.
2.2.2.a Charge pump architectures
Three generic topologies of charge-pumps are shown in Fig13. The switch is put at
the drain, gate and source of the current source (or sink) transistor in Fig. 13 (a), (b) and (c),
respectively. The one with switch at drain has the shortest switch time, but its peak current
matching is a problem. The one with switch at gate has the longest switch time and it is less
used in practice.
Figure 13: Simplified schematic of generic charge-pumps.
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Figure 14: Current steering charge-pumps.
Charge-pumps using the current steering technique shown in Fig.14 feature faster
transient response and no supply current glitches. A buffer is used in Fig.14 (b) to better
match the charge and discharge currents, and to minimize charge sharing at the output. The
charge pump in Fig. 14 (c) uses symmetric switches, but the two switch-to-output paths are
asymmetric.
Many efforts have been made to improve current matching and/or reduce charge-
injection and charge-sharing due to switching operation in the literature. However, we also
need to pay attention to the transient characteristic of charge pump because the PFD pulse
width is very small (typically around 1ns) in the locked state. Fast and symmetrical transient
response is critical for good matching in the charge pump. Fortunately, the reference
frequency is very high in the fractional-N synthesis and the reference spur is much less
concerned. The simplified schematic of the charge pump in the prototype PLL is the same as
the one illustrated in Fig. 14 (a). It has the properties of fast transient response and good
timing delay matching from switching controls, and DN, to output current Iout.
2.2.2.b Non Ideal Effects in Charge Pump
1. As shown in above figures switches are constructed using PMOS and NMOS. The inherent
mismatches between these two switches results in mismatch in charging and discharging
current in addition to timing mismatch. Hence there is variation in control voltage at the
output. In fact the W/L ratios are adjusted so as to have equal UP and DOWN currents. Even
though, mismatching is observed between these currents in simulation. That means, since two
current sources are themselves mismatched, the control voltage experiences the random
changes in it.
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2. There is also problem of charge sharing between output node of CP (in fact between filter
capacitor) and the parasitic capacitances between drain and source of switch transistors. This
results in sudden change in control voltage which may disturb the VCO.
3. Another effect is clock feed through. The high frequency signal provided at the gate of
switch transistor passes to the output node via gate to drain parasitic capacitor Cgd. This also
results in jumps in control voltage. Since the VCO sensitivity is high, even a small jump in
control voltage results a large jump in output frequency.
4. Another effect is limited output voltage. If we want higher output voltage the current
source value must be increased. This is not possible in every condition, since that increases
power consumption also.
Apart from this reference spur in PLL is also one of the critical problem which arises due to
current mismatches in charge pump.
To remove the non ideal effects in CP, so many different architectures are proposed. In
practice charge pumps are roughly classified into two categories. “Single ended charge
pump” and “Differential charge pump”.
2.2.2.c Single Ended and Differential Charge Pumps
In single ended charge pump only two inputs UP and DOWN are given to the
respective switches, while in differential charge pump two outputs of PFD are given to the
two differential switches with each input inverted and given to the second input of the
respective switch. Figure 15 shows one of the examples of differential charge pump.
Figure 15: Current steering charge-pumps
Without going into the details of differential charge pump, the advantages and limitations of
differential charge pump are listed below.
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2.2.2.d Advantages of Differential Charge Pumps
1. The switching mismatch between NMOS and PMOS does not affect the overall
performance substantially. The matching requirement between NMOS and PMOS transistors
are relaxed to the matching between NMOS or between PMOS transistors respectively.
2. The differential CP uses switches using NMOS and the inverter delays for UPb and DNb
signals do not generate any offset due to its fully symmetric operation.
3. This configuration doubles the range of output voltage compliance compared to single
ended charge pump.
4. Differential stage is less sensitive to the leakage current since leakage current behaves as
common mode offset with the dual output stages.
2.2.2.e Limitations of Differential Charge Pumps
Though differential CP has many advantages listed above, they suffer from critical
drawbacks. They require two loop filters and common mode feedback circuitry. Since more
number of transistors are required, with two or more current sources, they occupy large
silicon area. This also leads to higher power consumption.
2.2.2.f Limitations of Single Ended Charge Pumps
1. Switch mismatch, clock feed through, charge sharing problems are still not eliminated
fully.
2. Limited output voltage compliance range. For source CP shown above if we want higher
output voltage we have to increase the charging and discharging current values.
3. Switch mismatch also results in timing mismatch as well as dead zone.
4. Parasitic capacitances are dominant in single ended CP. Using of OPAmp may solve above
mentioned problems; but designing of OPAmp it itself tedious process and also increases
unnecessary hardware.
Even though single ended charge pump has these disadvantages, they are more
popular than differential design, because they do don’t require two loop filter and offer tri
state operation with lower power consumption. Also the problems listed above are not those
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much difficult to handle. With proper modification into the architecture, these problems can
be eliminated or minimized easily. Also, single ended charge pumps require fewer
components than differential charge pumps; hence they occupy less area in a chip. In the next
session we will discuss the different architectures of single ended charge pumps with their
simulation and comparison.
2.2.3 LOOP FILTER
The output signal of PFD consists of a number of terms; in the locked state of PLL the
first of these is a “dc” component and is roughly proportional to the phase error ∆Ф; the
remaining terms are “ac” components having frequencies of 2w1, 4w1.....etc. Because these
higher frequencies are unwanted signals, they are filtered out by the loop filter. Because the
loop filter must pass the lower frequencies and suppress the higher, it must be a low-pass
filter. In most PLL designs a first-order low-pass filter is used.
A simple PLL with first-order low-pass filter is shown in figure 16.
Figure 16: simple charge-pump PLL.
The closed loop transfer function of the above type-I PLL is given by
H(s) = …………………….... (2.2)
The closed-loop system contains two imaginary poles at S1,2 = ±j
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and is therefore unstable. The instability arises because the loop gain has only two poles at
origin, (i.e., two ideal integrators). As shown in Fig.17 (a), each integrator contributes a
constant phase shift of 900, allowing the system to oscillate at the gain crossover frequency.
Figure 17: (a) Loop gain characteristic of simple charge-pump PLL (b) addition of zero.
In order to stabilize the system, we must modify the phase characteristic such that the
phase shift is less than 1800 at gain crossover frequency. As shown in Fig17 (b), this is
accomplished by introducing a zero in the loop gain, i.e., by adding a resistor in series with
the loop filter capacitor.
The compensated type II PLL [2] of Fig.18 suffers from a critical drawback. Since the
charge pump drives the series combination of Rp and Cp, each time a current is injected into
the loop filter, the control voltage experiences a large jump. Even in the locked condition, the
mismatches between I1 and I2 and the charge injection and clock feedthrough of S1 and S2
introduce voltage jump in Vcont. The resulting ripple severely disturbs the VCO, corrupting
the output phase. To relax this issue, a second capacitor is usually added in parallel with R p
and Cp suppressing the initial step as shown in fig 19.
Figure 18: Addition of zero to charge-pump PLL
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The loop filter now is of second order, yielding a third-order PLL and creating stability
difficulties. Nonetheless, if C2 is about one-fifth of Cp, the closed-loop time and frequency
responses remain relatively unchanged. Also, the components R3 and C3 can be added in
order to further reduce the reference spur levels.
Figure 19: Addition of C2 to reduce ripple on the control voltage.
2.2.4 Voltage Controlled Oscillator
2.2.4. a Introduction to VCO
The VCO is a key block of a PLL frequency synthesizer. It determines the out of band
phase noise performance. Most applications require that oscillators be “tunable”, i.e., their
output frequency be a function of a control input, usually a voltage. An ideal voltage-
controlled oscillator [2] is a circuit whose output frequency is a linear function of its control
voltage (Fig. 20)
Wout = Wo + KvcoVcont. …………………………… (2.4)
Here, Wo represents the intercept corresponding to Vcont = 0 and Kvco denotes the “gain” or
“sensitivity” of the circuit (expressed in rad/s/V). The achievable range, ω2-ω1 is called the
“tuning range”.
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Figure 20: Definition of VCO
Commonly, both ring oscillators and LC oscillators are used in GHz range applications. But
the phase noise of ring oscillators is generally not good enough in the application of narrow
band wireless communication systems.
2.2.4.b Oscillation Conditions
An oscillator is based on a self-sustaining oscillation mechanism that is able to initiate
oscillation and perform continuous generation of a periodic output. Oscillators can be treated
as both two-port and one port networks, as illustrated by Figure 21.
Figure 21: Oscillator representation by: (a) the feedback system, (b) the one port view
Depending on the desired configuration and the characteristics of the oscillator that is
being designed, one model may be preferred over the other to represent the actual oscillator.
The principles behind the operation of the two oscillators sketched in Figure 21 are
considered in the following. In reference to Figure 21(a), the closed loop transfer function of
the feedback system is defined as:
………………………… (2.5)
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Assuming a unity value of feedback i.e. β( jw) = 1 . The gain of the active circuit
denoted H(jw), is the open-loop gain, since it is the gain between X(jw) and Y (jw) when the
feedback loop is open. To achieve steady oscillation, two conditions must be simultaneously
met at the resonance frequency. These conditions are known as the Barkhausen criteria that
states
The magnitude of the loop gain H(jw)β(jw) must have a value of unity and the total phase
shift around the closed loop must be 0o or a multiple of 360o in the positive feedback system.
For oscillation to occur, an output signal must be present even if no input signal is
applied. Specifying X (jw) = 0 in Equation 2.5 results in the fact that a finite value of Y(jw)
is possible to achieve only when the denominator is zero. Applying this statement: 1 − H (jw)
= 0, results in the requirement to the loop gain i.e. H (jw) β (jw) = 1, which complies with the
Barkhausen’s criteria.
Besides from being necessary, in some cases the Barkhausen criteria is not sufficient
for oscillation, such as in the oscillator start-up. To ensure the start-up of oscillation, the
small-signal loop gain must be greater than unity while the achievement of steady oscillation
requires that the loop gain falls back to unity. If this is not the case, at some point a limitation
of the oscillation growth will occur due to the finite value of supply voltage. In this situation,
the sinusoidal shape of the oscillation will be lost due to clipping of the oscillation amplitude.
Using a FET as the active circuit involves an analysis of the small-signal equivalent of
the FET with the purpose to determine the transconductance parameter gm that constitutes
the gain of the active circuit and the open-loop gain of the feedback system. In the oscillator
start-up period, gm should be set to its small-signal value since the circuit is in the small-
signal regime before start of oscillation.
Assuming that the impedance of the LC tank is purely real at the resonance frequency
entails that β(jw)Rp, which results in the fact that GmRp = 1 must be fulfilled for steady
oscillation, according to the Barkhausen criteria. By observing the movements of the closed
loop poles in the s-plane, it is possible to evaluate the closed-loop step response and the three
possible situations are mentioned below.
GmRp < 1: Closed-loop poles located in the left half s-plane, oscillation dies out.
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GmRp > 1: Closed-loop poles in the right half s-plane, amplitude grows with time.
GmRp = 1: Poles located on the jw axis, oscillation maintained.
As mentioned previously, the control of the amplitude must be in focus in the attempt to both
initiate the oscillation start-up and to maintain the steady oscillation.
In addition to the positive feedback approach, an oscillator can likewise be modeled using
two one port networks, as shown by Figure 21(b). The purpose of the active circuit in this
case is to generate a small-signal negative resistance at the operating point of the oscillator.
The value of the generated negative resistance must be equal to -Rp and thereby the parallel
resistance will appear as infinite to the resonator allowing steady oscillation. The resonator
consists of an LC tank including the parasitic resistances and this circuit can be converted to a
parallel version that is equivalent for a limited frequency range. This method is useful for
VCO purposes, since the VCO operates over a narrow band of frequencies.
2.2.4.c Performance parameters of VCOs
Center frequency: The center frequency is determined by the environment in which the
VCO is used.
Tuning range: The required tuning range dictated by the two parameters
1. The variation of the VCO center frequency with process and temperature and
2. The frequency range necessary for the application.
The center frequency of some CMOS oscillators may vary by a factor of two at the extremes
of process and temperature, thus mandating sufficiently wide (≥2x) tuning range to guarantee
that the VCO output frequency can be driven to the desired value. Also some applications
incorporate clock frequencies that must vary by one desired value. Also, some applications
incorporate clock frequencies that must vary by one to two orders of magnitude depending on
the mode of operation, demanding a proportionally wide tuning range.
An important concern in the design of VCOs is the variation of the output phase and
frequency as a result of noise on the control line. For a given noise amplitude, the noise on
the output frequency is proportional to KVCO because Wout=Wo+ KVCO Vcont. Thus, to
minimize the effect of noise in Vcont, the VCO gain must be minimized a constraint in direct
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conflict with the required tuning range. The allowable range of Vcont is from V1 to V2 (0 to
Vdd) and the tuning range must span atleast w1 to w2, then KVCO must satisfy the following
requirement:
KVCO
Note that for a given tuning range Kvco increases as supply voltage decreases,
making the oscillator more sensitive to noise on the control line.
Tuning Linearity: The tuning characteristic of VCOs exhibit nonlinearity, i.e., their gain
Kvco is not constant. This nonlinearity degrades the settling behaviour of phase-locked loops.
For this reason, it is desirable to minimize the variation of Kvco across the tuning range.
Actual oscillator characteristics typically exhibit a high gain region in the middle of
the range and a low gain at the two extremes. Compared to a linear characteristic, the actual
behaviour displays a maximum gain greater than that predicted by, implying that for a given
tuning range, nonlinearity inevitably leads to higher sensitivity for some region of the
characteristic.
Output Amplitude: It is desirable to achieve a large output oscillation amplitude, thus
making the waveform less sensitive to noise. The amplitude trades with power dissipation,
supply voltage, and the tuning range. Also, the amplitude may vary across the tuning range,
an undesirable effect.
Power dissipation: As with other analog circuits, oscillators suffer from trade-offs between
speed, power dissipation, and noise. Typical oscillators drain 1 to 10mw of power.
Supply and common-mode rejection: Oscillators are quite sensitive to noise, especially if
they are realized in single-ended form. But the differential oscillators exhibit supply
sensitivity. The design of oscillators for high noise immunity is a difficult challenge. Note
that noise may be coupled to control line of VCO aswell. For these reasons, it is preferable to
employ differential paths for both the oscillation signal and the control line.
Output signal purity: Even with constant control voltage, the output waveform of a VCO is
not perfectly periodic. The electronic noise the devices in the oscillator and supply noise lead
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to noise in output phase and frequency. These effects are quantified by “jitter” and “phase
noise” determined by the requirements of application.
Types of Integrated Oscillators
Integrated VCOs for high-frequency communication applications can be implemented
using ring architecture, relaxation circuits, or LC based networks. Among these, LC
oscillators have the phase noise and frequency performance because of their use of passive
resonant elements with high Q factors. LC oscillators have been constructed using bonding
wires, integrated inductors. Using external parts, however rises the cost of the system and
introduces other problems such as increased parasitic levels and increased power dissipation;
therefore fully monolithic designs are highly desirable. There are other problems related with
the utilization of bonding wires as the high Q inductor of the LC oscillator such as the lack of
accurate control of the inductance value. In state of the art CMOS processing it is possible to
fabricate integrated inductors with high quality factors (Q~85). They can be implemented
monolithically at the expense of adding processing steps that significantly increase the cost
and the expense of adding processing steps that significantly increase the cost and complexity
of the system. Micro-Electro-Mechanical Systems (MEMS) designers, for example use
various etching techniques to obtain high performance monolithic inductors. Addition of
inductors to a CMOS process also introduces problems such as the control of eddy currents in
the substrate and magnetic coupling.
Ring oscillators, on other hand, are suitable for monolithic system design using any
digital CMOS fabrication process. Ring designs may require less die area when compared to
the LC counterparts because of the lack of area –consuming passive elements (inductors and
varactors). In addition, the design of ring oscillators is straightforward using integrated circuit
design techniques. Other properties of ring oscillators such as the availability of multiple
phases at the output and wide tuning range can be useful for some specific applications
including frequency synthesizers and over sampling circuits. These characteristics of ring
oscillators lead to conclusion that they are still important in modern integrated
communication systems. As implied above the noise performance of ring oscillators is
generally worse than LC oscillators because of the low quality factor Q of the ring
structure .However by using different ring architectures and circuit techniques , it is possible
to achieve frequencies and noise levels comparable to LC designs.
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The final candidate for the high frequency integrated VCO design is relaxation
oscillator. A relaxation oscillator employs the same elements as a ring oscillator without the
need for high-quality inductors. The only difference is the use of an additional capacitive
element. This is in contrast to high-speed ring oscillator designs ,which utilize the capacitive
parasitic s of the Metal oxide semiconductor transistors(MOS).Only a few CMOS relaxation
oscillators have been published ,with the fastest running at 900MHz .They also do not match
the noise performance of LC and ring oscillators because of their relatively low effective
quality Q factor.
2.2.4.1 LC –Oscillators
The core of an LC oscillator is a resonator tank that is constructed from on chip inductors and
varactors. This tank performs as the frequency selective network that was shown in the oscillator
model of fig24.As shown in fig23, the resonator tank can be simply modelled as a parallel connected
LC network along with the series parasitic resistance of the Rs of the inductor.
Figure 22: Resonator Tank circuit
Figure 23: LC oscillator model
The tank might have a very good quality factor; however the tank alone is not sufficient for
steady oscillations because of the energy loss on the parasitics. After excitation, the resonator will
only oscillate for approximately Q many cycles until all the stored energy is dissipated on the Rs
unless the energy loss is accompanied before. Therefore every LC oscillator employs an active
circuitry that cancels the parasitic resistance with its negative effective resistance by providing the
required energy at every cycle. This active circuitry is shown as the LC oscillator is strictly
determined only by the characteristics of the resonator, that is Wr =1/√(LC) and ideally is not effected
by the active circuitry if the capacitive loading of the -R element is ignored.
22
Ring oscillator usually takes less area and has a large tuning range. The LC oscillator
often takes more chip area due to spiral inductors and has a smaller tuning range.
2.2.4.2 Ring Oscillators
As discussed in the previous sections, the Barkhausen criterion for oscillation can be
satisfied with a positive feedback loop that does not contain any frequency selective
elements. A ring oscillator can be constructed by closing the feedback loop around an
amplifier block while an LC oscillator needs both the amplifier block and the frequency
selective network to operate properly. A ring oscillator is realized by connecting a number of
amplification stages in series as shown in below fig24.Then the loop is closed by connecting
the output of the last element to the input of the first element forming the positive feedback.
The most basic ring oscillator employs single-ended inverters in place of the amplification
stages. In this case, an odd number N of inverter stages is needed for steady oscillations.
Otherwise the oscillator latches up at a DC level which corresponds to the satisfaction of the
Barkhausen criterion at zero frequency. From another perspective, an odd number of stages
will oscillate because if one mode is excited, the pulse will propagate through all the stages
Figure 24: Ring oscillator structure
and will reverse the polarity of the initial node. It was already implied that the frequency of
oscillation will be 1/(2*N*Td) where Td is the propagation delay of a single stage for this
case.
2.2.4.2.a Frequency Domain Analysis
This discussion, however does not tell anything about oscillation criteria of ring
oscillators when different types of stages are used or when a differential architecture is
utilized. Therefore, let us generalize this discussion to ring oscillators with gain stages that
can be characterized by a transfer function.
In this case, we can define the loop gain L(s) as
23
.......................................(2.7)
Where are the s-domain transfer functions of
individual delay stages. For most practical applications, the gain stages are identical so that
the loop gain reduces to
L(s) = A (s) .....................................................(2.8 )
Where N is the number of stages, and
According to Barkhausen criterion, the total phase difference should be equal to a multiple of
2п and the magnitude of the loop function should be equal to one. This implies that a single
stage should be able to provide a phase shift of 2kп/N at the unity gain frequency, where k is
an integer .Therefore the oscillation criterion can be alternatively written as
.....................................................................(2.9)
And
...........................................................(2.10)
Figure 25: Ring oscillator structure
for the ring oscillators at the oscillation frequency. If the ring oscillator stages are replaced
with their linear equivalents i.e., small signal equivalents that consists of a negative
24
transconductance and RC load, the simple ring loop can be redrawn as shown in above fig25.
In this model, every stage has a phase shift of (п+θ) as shown in fig25. Coming from the
DC inversion and θ from the RC load delay. To satisfy the oscillation criteria, the total phase
shift around the loop must be equal to a multiple of 2п, with Nп of this supplied by the odd
number of inversions in the loop. The general practice is to minimize the required phase shift
to reduce the number of the required stages and, therefore, the total phase shift of the RC
delays should be equal to ±п, now, θ can be written as
θ = ±п/N
Next, using this phase relationship among the stages, oscillation frequency can be found after
simple derivations. From the given linear model, the transfer function of a single stage can be
written as
.......................................................(2.11)
At the oscillation frequency phase of this transfer function is
....................................................(2.12)
Note that, because of the phase shift criteria that was founded above, we can get
......................................................(2.13)
And finally the oscillation frequency can be found as
...............................................................(2.14)
This reduces to √3/RC for a three stage ring and 1/RC for a four stage one.
Phase requirement is automatically satisfied for different ring loops because of the
connections in the loop, assuming that the structure oscillates. However, the gain requirement
as given in equation is also satisfied by replacing A(jw) with gmR/ √
25
The gain requirement can be written as
.........................................(2.15)
By substituting RC with using the frequency relationship founded above , this can
be reduced to
...........................................................(2.16)
Since gm, R and cosθ are positive identities as defined before; we can cancel the Nth
exponents and simplify this argument as
.........................................................(2.17)
Remembering that the gain should be at least is equal to one at the oscillation
frequency. Therefore, the gain requirement of three stages loops ≥ 2, where as the
requirement is ≥ √2 for a four stage one. This equation shows that, it is easier to satisfy
the criteria for longer chains because each stage is required to have a smaller gain at the
oscillation frequency.
When single- pole amplifier stages are used in regular oscillator loop, the minimum
required number of stages is three. According to the analysis provided in this section, this is
because a single pole amplifier stage provide only θ = п/2 phase shift at the infinite
frequency. A simple implementation of ring oscillators is depicted in figure 26.
Let us assume the circuit of figure 26 begins with VX=VDD. Under this condition,
VY=0 and VZ=VDD. Thus, when the circuit is released, VX begins to fall to zero (because the
first inverter senses a high input), forcing VY to rise to VDD after one inverter delay, TD, and
VZ to fall to zero after another inverter delay. The circuit is therefore oscillates with a delay
of TD between consecutive node voltages, yielding a period of 6T.
26
Figure 26: Waveforms of ring oscillator when one node is initialized to VDD.
Ring oscillators employing more than three stages are also feasible. The total number
of inversions in the loop must be odd so that the circuit does not latch up. On the other hand,
the differential implementation can utilize an even number of stages by simply configuring
one stage such that it does not invert, as illustrated in figure 27. This flexibility demonstrates
another advantage of differential circuits over their single-ended counterparts.
Figure 27: Four-stage differential ring oscillator
Tuning in ring oscillators
27
The oscillation frequency of N stage ring equals 1/ (2N ), where denotes the large
signal delay of each stage. Thus to vary the frequency can be adjusted.
Consider the differential stage as shown in below fig 28 as one stage of ring oscillator.
Figure 28: Differential pair with variable output time constant
Here M3 and M4 operate in the triode region ,each acting as a variable resistor controlled by
Vcont.As Vcont becomes more positive ,the on resistance of M3,M4 increases, thus raising
the time constant at the output,T, and lowering the fosc. If M3 and M4 remain in deep triode
region
.......................................................................(2.18)
In the above equation denotes the total capacitance seen at each output to ground
(including the input capacitance of the following stage). The delay of the circuit is roughly
proportional to , yielding
28
Interestingly, is linearly proportional to .
But the above structure suffers from a critical drawback: The output swing of the circuit
varies considerably across the tuning range. With complete switching each stage provides a
differential swing of 2IssRsRon3, 4. Thus a tuning range of, say two to one translates to a
twofold variation in the swing.
In order to minimize the swing variation, the tail current can be adjusted by V cont as well such
that, as Vcont becomes more positive, Iss decreases. The circuit nonetheless requires a means
of maintaining IssRsRon3, 4 relatively constant.
Phase noise
The ideal synthesizer produces a pure sinusoidal wave for V(t )= Vo sin(2п t )
where Vo and are amplitude and frequency of the signal. When the amplitude and phase
fluctuations are accounted, the waveform becomes
V(t)=( Vo + v (t) ) sin( 2п t+ φ (t) ).................................(2.19)
Where v (t) and φ (t) represent amplitude and phase fluctuations respectively. Here we
considered that the phase fluctuations effect in a frequency synthesizer out. φ (t) represents
the random phase variation and it produces phase noise. The definition for the phase noise is
shown in
29
Figure 29: The definition of phase noise
The SSB phase noise is defined as the ratio of noise power in 1Hz bandwidth at frequency
offset Δf from the carrier to the carrier power. The unit is dBc/Hz.
....................................(2.20)
Where (fo+ Δf ,1 Hz) the noise power in 1Hz bandwidth at is offset frequency Δf from the
Carrier frequency fo and Pcarrier is the carrier power.
PHASE NOISE IN WIRELESS COMMUNICATIONS
Phase noise is usually characterized in the frequency domain. For an ideal oscillator
operating at the spectrum assumes the shape of an impulse, whereas for an actual oscillator,
the spectrum exhibits “skirts” around the center or “carrier” frequency (Fig. 30).
Figure 30: Phase noise in oscillator.
30
Figure 31: Generic Wireless Transceiver.
To quantify phase noise, we consider a unit bandwidth at an offset with respect to
carrier. Calculate the noise power in this bandwidth, and divide the result by the carrier
power. To understand the importance of phase noise in wireless communications, consider a
generic transceiver as depicted in Fig. 31, where the receiver consists of a low noise
amplifier, a band-pass filter, and a down conversion mixer, and the transmitter comprises an
up conversion mixer, a band-pass filter, and a power amplifier. The local oscillator (LO)
providing the carrier signal for both mixers is embedded in a frequency synthesizer. If the LO
output contains phase noise, both the down converted and up converted signals are corrupted.
This is illustrated in Fig. 32 and 33 for the receive and transmit paths, respectively.
Figure 32: Effect of phase noise on receive and Figure 33: Transmit paths
Referring to Fig.32 and Fig 33 we note that in the ideal case, the signal band of
interest is convolved with an impulse and thus translated to a lower (and a higher) frequency
with no change in its shape. In reality, however, the wanted signal may be accompanied by a
large interferer in an adjacent channel, and the local oscillator exhibits finite phase noise.
When the two signals are mixed with the LO output, the down converted band consists of two
overlapping spectra, with the wanted signal suffering from significant noise due to tail of the
interferer. This effect is called “reciprocal detect a weak signal at while a powerful, nearby
transmitter generates a signal at with substantial phase noise. Then, the wanted signal is
31
corrupted by the phase noise tail of the transmitter. The important point here is that the
difference between and can be as small as a few tens of kilohertz while each of these
frequencies is around 900 MHz or 1.9 GHz. Therefore, the output spectrum of the LO must
be extremely sharp.
2.3 PLL-based Frequency Synthesizer
A PLL frequency synthesizer is one of the key building blocks of a CMOS RF
frontend transceiver. In this section, we will introduce two main PLL frequency synthesizers.
2.3.1 Integer-N PLL Frequency Synthesizers
A basic PLL-based integer-N frequency synthesizer consists of four basic
components: a phase detector (PD), a loop filter, a voltage controlled oscillator (VCO), and a
programmable frequency divider. The phase detector compares the phase of the input signal
against the divided phase of the VCO. The output of the phase detector is a measure of the
phase difference between the two inputs. The difference voltage is then filtered by the loop
filter and applied to the VCO. The control voltage on the VCO changes the frequency in the
direction that reduces the phase difference between the input signal and the frequency divider
output.
Figure 34: Integer N synthesizer architecture
For an integer-N synthesizer, the output frequency is a multiple of the reference
frequency
fout = N.fref ……………………………………..(2.21)
Where N is the loop frequency division ratio, is an integer. From Eq. (2.21), the frequency
resolution is equal to the reference frequency fref. Due to this limitation of the reference
frequency, for narrow-band applications, the reference frequency of the synthesizer is very
32
small. So the small reference frequency results in a very small loop bandwidth, moreover, a
very large frequency division ratio.
The conventional integer-N PLL with low reference frequency has several
disadvantages. First, the lock time is long due to its narrow loop-bandwidth. Second, the
reference spur and its harmonics are located at low offset frequencies. Third, the large
division ratio (N) increases the in-band phase noise associated with the reference signal,
phase detector, and frequency divider. Finally, with a small loop bandwidth, the phase noise
of the VCO will not be sufficiently suppressed at low offset frequencies. So, fractional-N
frequency synthesizers are introduced to improve the phase noise and settling time
performance of integer-N PLL synthesizers.
2.3.2 Fractional-N PLL Frequency Synthesizers
Fractional-N frequency synthesizers are used to overcome the disadvantages of
integer-N synthesizers. In fractional-N synthesizers, fractional multiples of the reference
frequency can be synthesized, allowing a higher reference frequency for a given frequency
resolution.
Figure 35: Fractional-N frequency synthesizer architecture
In Fig. 35 the division modulus of the frequency divider is steered by the carry bit of a
simple digital accumulator of x-bit width. The symbol N/N + 1 of the divider means that the
division ratio is N +1 when the carry bit is 1, otherwise the division ratio is N. To realize a
fractional division ratio i.e. N + F, with F€ [0, 1], a digital input K = F/ 2n is applied to the
accumulator. A carry output is produced every K cycles of the reference frequency f ref, which
is also the sampling frequency of the accumulator. This means that in 2x clocks of reference
33
frequency fref, the division ration is N for (2n-K) clocks, and the division ratio is N + 1 for K
clocks. This results in an average division ratio Navg, given by
…………………………. (2.22)
This means that a non-integer division ratio can be realized. The most important disadvantage
of fractional synthesizer architecture is the generation of spurs in the output spectrum due to
the noise on the modulus control called pattern noise in the overflow signal. The pattern noise
can be better understood if the accumulator is regarded as a ΣΔ modulator.
2.4 Divider Architecture and Hierarchy
A crucial aspect of the present-day consumer electronics industry is the short time
available for the introduction of new products in the market. Short time-to-market demands
architectures providing fast design time, simple layout work, and easy optimization.
Furthermore, from a high re-usability point of view, architecture with easy adoption of the
input frequency range, maximum and minimum division ratios is more desirable. For these
reasons, we prefer a generic and fully programmable architecture.
Generic Chain Architecture:
The multi-modulus divider system architecture [4] is depicted in fig 36. It consists of
a chain of divide-by-2/3 dual-modulus prescalers in cascade, connected like a ripple counter.
Figure 36: Multi-modulus Divider architecture
The multi-modulus divider operates as follows. In every division period, the last cell
of dual-modulus prescaler in the chain generates signal mod (n-1). This signal then 34
propagates up the chain. An active mod signal would enable the cell to divide by three once
in a division cycle, as long as the programmable input bit p is set to 1. In other word, the
dual-modulus divide-by-2/3 cell would divide by three only ONCE in a whole division cycle,
if it ever gets enabled to do so by having both the programmability p and the signal mod
enabled. For the rest of the division cycle, the cell divides the input by two. Thus, division-
by-three action only adds one extra period of each cell’s input signal to the period of output
signal. For example, each divide-by-three action in a cell with a 2.5 GHz (0.4ns period) input
would introduce an extra 0.4 ns to the output period. The output period then becomes 1.2ns
instead of 0.8 ns. Applying the principle to the whole chain, the output period can be
………….
(2.23)
CHAPTER 3ZIGBEE FREQUENCY SYNTHESIZER
In this section, the need for the Zigbee standard is addressed and the specifications for
the frequency synthesizer for application in a 2.4 GHz transceiver are derived. The
architecture development of the synthesizer and the system level design issues are discussed
here. The frequency synthesizer, which performs the main role of career generation for the 35
down-conversion/ up-conversion, is a key building block in radio front-ends. Despite not
being directly involved in the signal path, the performance of the synthesizer affects the
overall performance of the transceiver.
3.1 Wireless Standards
The 21st century has lead to the dawn and revolution of new information technology
era marked by the emergence of various wireless standards. Internetworking technologies
have lead to a high connectivity to information, be it data, voice, audio, or video. The need
for ubiquitous mobile computing and networking is more so felt now than ever before.
Various standards have been developed over the last decade to cater to different needs and
applications.
Examples of such standards include Bluetooth, 802.11a/b/g, ultra wideband, 802.15.4/
Zigbee, GSM, GPS, DECT-1800, DECT-1900, etc. It merits mention that certain standards
like the GPS were mainly developed for military applications, only to be released in the
commercial market too. Moreover, the technological advances, especially, in the field of
integrated circuits has accelerated this revolution. Complete low-area, low-cost, monolithic
integrated transceiver solutions are now in vogue.
The IEEE 802.15.4/ Zigbee standard has been recently developed (officially released
for commercial applications in December 2004) to cater to the needs of low cost, low power,
low data rate, and short range wireless networks [1]. The Zigbee Alliance is responsible for
the Zigbee wireless technology, which defines network, security and application layers upon
the IEEE 802.15.4 PHY and MAC layers [1]. Henceforth, for reasons of brevity, the IEEE
802.15.4/ Zigbee standard will be termed Zigbee. It has been realized that already existing
short-range wireless standards like Bluetooth and 802.11a/b/g have relatively high data rates
when compared to the actual data rate required for certain applications. For e.g. the use of a
bluetooth transceiver, with a data rate of 1 Mbps, in applications involving the
communication of data in the form of simple text, leads to sheer wastage of resources.
Networks involving machine-to-machine (M2M) communication for monitoring and quality
control purposes do not need a high data rate. The standard addresses the need of network
applications requiring high density of transceivers with low data-rate. Such transceivers need
to have a long battery life and should be highly economical in cost. They are an attractive
option for applications pertaining to low-data industrial monitoring and control, sensor based
36
network systems, home automation, gaming, medical and automotive solutions. Further, it
can theoretically support upto 65,000 nodes in the network [1].
The important design considerations from the paradigm of a transceiver design are
frequency band, the data rate, the required range of wireless transmission, sensitivity at the
receiver end, modulation scheme, transmitted output power, settling time for frequency
hopping, adjacent and alternate channel interferers etc. These specifications influence the
choice of technology, the choice of architecture and the choice of the standard.
Table I gives a comparison between the popular wireless standards – IEEE 802.11.
a / b /g [11-13], Bluetooth[14], and ultra wideband[15] with the Zigbee standard[8]. It can be
seen that Zigbee is the only standard that is tailored for low data-rate systems. Further, it can
be inferred that prior to the Zigbee standard, more importance had been given to the
development of high data-rate, multimedia friendly standards.
Table I
3.2 Synthesizer Specifications from Standard
The IEEE 802.15.4 standard gives the communication protocol for the prototype
transceiver implementation and the specifications for the transceiver and the synthesizer need
to be derived from this standard. The mapping of the specifications from the standard is an
important pre-design process. This section highlights the one-to-one correspondence between
the standard and the key performance metrics of the synthesizer. The key specifications from
37
the standard that are used for the estimation of the synthesizer performance metrics is
explained figuratively using Fig. 37.
Figure 37: Mapping Standard to Key Synthesizer Specifications
3.2.1 Frequency Synthesis
The 2.4 GHz Zigbee standard has 16 channels, spaced 5 MHz apart, from 2405MHz
to 2480 MHz. The synthesizer needs to synthesize these 16 channel selection clock
frequencies with 40-ppm frequency accuracy. This performance metric is essential for the
selection of the architecture and the design of the divide ratio for the divider. Since 16
channels need to be synthesized with a spacing of 5 MHz, it is natural to assume a clock
reference of 5 MHz for an integer-N PLL based synthesizer scheme.
3.2.2 Phase Noise
Typical wireless systems employ the concept of time division multiple access or
frequency division multiple access to increase the throughput and capacity of the system.
Hence, it becomes necessary to switch from one channel to another in time. With this
38
multiple access approach, the signal actually seeps into the other channels and contributes to
channel interference. In the Zigbee PHY layer, the maximum contribution to co-channel
interference is from the adjacent and alternate channels, spaced 5 MHz and 10 MHz apart
from the channel of interest.
Fundamentally, the LO spectrum is not a pure single frequency tone in real-life
implementations. The mechanisms of phase noise lead to the “skirt” behavior in the LO
spectrum of the VCO or the synthesizer. The time domain manifestation of phase noise is
jitter. Jitter can be defined as the variations in the zero crossings of the signal. These
variations can be both random and deterministic. The various sources of jitter are reference,
charge pump mismatch, spurs in the control line of the VCO, thermal noise of the loop filter,
supply noise, phase noise of the VCO, phase mismatch in the dividers, etc.
Figure 38: Down conversion in a Transceiver
Thus, the phase noise of the LO for a particular channel, contributes to co-channel
interference due to the mechanism of down-conversion. In typical wireless systems, signal
processing is performed in two steps (as shown in Fig. 38) down-conversion of the RF signal
following “low-noise” amplification by the LNA to the baseband domain; and subsequent
baseband processing. Thus, down-conversion is inevitable and most phase noise
specifications are derived from adjacent channel rejection requirements of the standard.
The phase noise of the adjacent channel LO frequency tone creates interference for the
channel of interest. From Fig. 38, it can be seen that the Signal to Noise Ratio required at the
input of the IF section (say, following down-conversion) is given as
SNR = (Psig + PLO) – (PN + Pint + PBW) > SNRmin ......................................(3.1)
39
Where Psig is the power content of the carrier
PLO is the power content of the LO
PN is the phase noise contribution of the LO
Pint is the power content of the interferer
PBW is the power content of the signal across the channel bandwidth
SNRmin is the required SNR at the input of the IF section following down-conversion for the
given demodulation scheme and tolerable bit error rate.
Figure 39: Phase Noise Contribution SNR at Input of IF to Section
Careful gain planning gives us a minimum SNR requirement at the input of the IF
section. To support a minimum SNR requirement of 2 dB at the input of the demodulator in
the receiver path, the SNR requirement at the input of the IF section can be calculated as 8
dB. The signal (Psig) is down-converted to IF or DC by LO (PLO) provided by the synthesizer.
The channel spacing is 5 MHz, there would be a guard band on either side of the channel to
prevent aliasing and minimize co-channel interference. The actual bandwidth of the channel
would therefore be less than 5 MHz. However, for purposes of hand calculations, we can
assume that the bandwidth is 5 MHz.
Equation 3.1 can be rearranged to give
PN-PLO < (Psig -Pint) -PBW - SNRmin ...........................................(3.2)
From the above equation, the phase noise specifications for the synthesizer can be calculated
as
(PN-PLO) 5MHZ = (0-0) – 10*log(5.106) – 8=-75dBc/Hz
(PN-PLO) 10MHZ = (0-30) – 10*log(5.106) – 8=-105dBc/Hz.
40
Figure 40: Leeson Phase Noise Model
Assuming a margin of 5 dB in SNR to model the non-idealities of the system, the
phase noise specification can be taken as –110 dBc/Hz at an offset of 10 MHz from the
carrier. The Leeson model of phase noise provides a good approximation. Typically at
frequency offsets in the range of 1 MHz (beyond the knee frequency f1, given by flicker
noise up-conversion limitations), the “skirt” assumes a -20 dBc/decade roll-off behaviour
(Refer Fig. 40). Thus it can be seen that the 10 MHz specification is tighter to meet.
Therefore meeting the phase noise specifications at 10 MHz implies that the specification at 5
MHz is met, but not vice-versa.
3.2.3 Spur Rejection
The reference spurs appear at the output of the VCO spectrum in any PLL based
system. If the integer-N PLL based synthesizer scheme is implemented, reference spurs
appear at an offset of 5 MHz, equal to the channel spacing. The downconverted spur
contributes to the interference and worsens the SNR at the input of the IF section. The Zigbee
standard specifies the adjacent channel interference of 0 dB at an offset of 5 MHz. Here, the
spur is considered as a single tone and not as an integrated noise
.
Figure 41: Sources of Reference Spur in an Integer-N PLL based Synthesizer
41
Further, the importance of PCB level issues on the spur performance of a synthesizer
is highlighted. The modulation of the control voltage of the VCO leads to spurs in the output
spectrum of the VCO and the synthesizer. Various sources exist for the modulation of this
control line of the VCO. The important sources are the PCB coupling, substrate coupling,
charge pump mismatch, and the power supply noise and are given in Fig.41.
From Fig.42, the Signal to Noise Ratio required at the input of the IF section (say, following
down conversion) can be obtained as
SNR = (Psig + PLO) – (Pspurs + Pint) > SNRmin..............................(3.3)
Pspurs-PLO < (Psig -Pint) - SNRmin..................................................(3.4)
Figure 42: Effect of Spurs on SNR at Input of IF Section
Thus the spur suppression requirement for the synthesizer can be calculated as
Moreover, the fundamental reference spur is at 5 MHz. Harmonics of the reference spur
occur at 10 MHz, 15 MHz, etc. The differential mode of operation should ideally give only
odd-harmonics. However, realistic environments give finite even-order components. Thus,
the spur suppression specification at an offset frequency of 10 MHz, where the alternate
channel interferer is present can be calculated as
PSpurs PLO (0 0) -8 8dbc
Assuming a margin of 5 dB in SNR to model the non-idealities of the system, the Spur
Suppression Specifications can be taken as –13 dBc and –43 dBc at offset frequencies of 5
MHz and 10MHz respectively.
PSpurs PLO (0 0) -8 8dBc
42
3.2.4 Settling Time
The standard supports a data rate of 250 Kbps. Each symbol is a word, consisting of 4
bits. Thus, the supported symbol rate is 62.5 K symbols/ sec. The maximum RX-TX or TX-
RX turnaround time is given as 12 symbol periods, which is equivalent to 192 μs. This gives
an estimate of the worst case settling time for the synthesizer for extreme switching from
Channel 1 to channel 16.
The settling time for the synthesizer is equivalent to the locking time for the PLL. The loop
settles to a new frequency output based on the channel selection configuration. For e.g. the
transceiver is operating in the receive mode at 2.405 GHz. In the next scheme of operation, it
needs to operate in the transmit mode at 2.48 GHz. The synthesizer now synthesizes
2.48GHz. The time taken by the synthesizer to settle to the new frequency can be seen as the
frequency response time of the loop.
3.3 Synthesizer Architecture
The synthesizer needs to synthesize channels in steps of 5 MHz from 2405-2480MHz.
The frequencies to be synthesized are integer multiples of the channel spacing. Hence,
integer-N PLL based synthesizer architecture will be best suited for this application. Since the
phase noise and spur rejection specifications are relaxed, the integer-N PLL based solution
gives the best performance in terms of power consumption and ease of integrability. Other
synthesizer architectures exist, namely the Fractional-N synthesizer and Direct Digital
Synthesizer [16, 17].
The fractional synthesizer uses a fractional divider scheme with sigma-delta
Modulator for dithering mechanism and noise shaping in the divider section. This
architecture is particularly useful in applications requiring very high frequency resolution.
For e.g., in typical read channel applications, the synthesizer works from 1 GHz to 2 GHz
with a frequency resolution of 1.5%. The fractional-N synthesizer is not the best scheme for
2.4 GHz Zigbee applications.
The direct digital synthesizer doesn’t make use of a feedback mechanism and is
known to provide frequency synthesis with fast settling times. However, the frequency of
application is limited due to the inherent digital nature of the synthesizer. It makes use of an
accumulator, read only memory (ROM), digital-analog converter (DAC) and low pass filter
43
(LPF). It is difficult to obtain ROM’s working at 4.8 GHz for 2.4 GHz synthesizers. Thus,
this approach is not suitable for 2.4 GHz Zigbee applications.
Figure 43: Integer-N PLL Based Synthesizer
The integer-N PLL based synthesizer architecture is given in Fig.43. It consists of a
phase frequency detector that compares the reference with the feedback signal obtained from
the dividers to translate into time-level information. The charge pump along with the loop
filter converts the critical time-level information into voltage. This voltage is effectively the
control voltage of the VCO. Based on the behaviour of the control voltage, the VCO changes
its frequency. The PLL finally settles to a new frequency based on the channel select
configuration. The divider provides programmability to the synthesizer. The synthesizer
implementation, given above, is a complex discrete-time system and involves a non-linear
control theory approach. However, for purposes of gaining insight into the operation of the
PLL control structure, the continuous time approximation can be made, provided the
Gardener’s Stability limit is taken into consideration. This approximation helps us in
understanding the loop stability and dynamics better.
3.4 System Level Design
3.4.1 Theory
The charge-pump based PLL architecture [9] is given with the respective transfer
functions of each block in Fig.44. The oscillator and the charge pump-loop filter contribute to
two poles at the origin. For purposes of stability, a zero is placed appropriately to ensure
sufficient phase margin. The loop filter introduces a pole and a zero in the system. If C 2 were
44
absent, the control voltage experiences sharp transitions every time charge is injected into the
R1-C1.
Eqn.3.5 gives the overall open loop transfer function as
Hopen (s) = = ............................................(3.5)
Where ωz1 =1/R1C1 ωp1=1/R1C2
Figure 444: Charge Pump PLL The closed loop transfer function can be obtained as
Hclosed(s) = = ................................(3.6)
Normally, the pole ωp1 is placed beyond the natural frequency ωn of the system.
Therefore, Eqn.3.6 reduces to a second order system given by Eqn. 3.7
Hclosed(s) = = ......................................(3.7)
Where wz1=1/R1C1
45
This can be compared with the classical second order equation given by Eqn.3.8
Hll(s) = ..........................................................................(3.8)
to obtain the critical design parameters given by Eqns. (3.9-3.11).
......................................................................................(3.9)
= = .............................................................................(3.10)
...................................................................................(3.11)
From Fig 45, it can be seen that the exact location of the pole ωp1 and the zero ωz1 affects the
transient dynamics of the entire closed loop. From control theory if
= ......................................................................................................(3.12)
= .................................................................................................(3.13)
then, α = 2 yields ξ =1; the case for critical damping in a II order system. Critical damping
leads to a fair compromise between settling time and overshoot.
46
Figure 45: Pole-Zero Placement
CHAPTERPROBLEM CHARACTERIZATION AND SPECIFICATIONS
This chapter deals with clear understanding and characterization of the problem
before aiming specifications.
4.1 Zigbee Transceiver
The main design focus of this transceiver implementation is design for low power
consumption and high integrability in a low cost technology. The transceiver in a
communication system is composed of many blocks (as shown in fig 46): Low Noise
Amplifier (LNA), mixer, power amplifier and phase locked loop. Frequency Synthesizer has
the major power consumption among these blocks. It generates the carrier frequency for
transmission and selects channel frequency for reception. Decreasing its power would
decrease total power of the transceiver.
Figure 46: Transceiver Architecture47
The Zigbee alliance has been developing a standard based wireless sensor networks
with low data rates and low power consumption. IEEE 802.15.4 defines Physical (PHY) layer
and Medium Access control (MAC) layer, while ZigBee alliance has added Network,
Security and Application layers above it. It is the first global wireless standard aimed at low-
power remote monitoring and control applications.
IEEE 802.15.4 defines three frequency bands of operation. The 868, 915 MHz and
2.4GHz unlicensed bands. Among the three the 2.4GHz band is highly attractive, since this
unlicensed band is commonly available throughout the world. The typical applications of this
low data rate standard include those for industrial and commercial uses, home automation,
PC peripherals, customer electronics and personal care applications, as well, toys and games
that should be able to run for six months to two years on just button cells.
Table 3.1 Transceiver Specifications
4.2 System level specifications
The 2.4 GHz Zigbee standard has 16 channels, spaced 5 MHz apart, from 2405 MHz to
2480 MHz. The synthesizer needs to synthesize these 16 channel selection clock frequencies
with 40-ppm frequency accuracy. This performance metric is essential for the selection of the
architecture and the design of the divide ratio for the divider. Since 16 channels need to be
48
synthesized with a spacing of 5 MHz, it is natural to assume a clock reference of 5 MHz for
an integer-N PLL based synthesizer scheme.
The frequency synthesizer is designed to cover a frequency range from 2.4 GHz to
2.4835 GHz, and hence VCO tuning range is from 2.4GHz to 2.4835GHz.
Divider ratio is from 480-495 since reference frequency is 5MHz.
Signal to Noise Ratio required at the input of the IF section is given as
SNR = (Psig + PLO) – (PN + Pint + PBW) > SNRmin
PN-PLO < (Psig -Pint) -PBW – SNRmin
(PN-PLO) 10MHZ = (0-30) - 10log (5.106) – 8 = -105dBc/Hz
Assuming a margin of 5 dB in SNR to model the non-idealities of the system, the
phase noise specification can be taken as –110 dBc/Hz at an offset of 10 MHz from
the carrier
The frequency synthesizer is designed to cover S band (2.4 GHz to 2.4835 GHz), and it is a
integer-N 3rd Order Type II. The system level specifications of the synthesizer are
Parameter value
Reference frequency 5MHz
VCO tuning range 2.4GHz-2.4835GHz
Phase-noise offset@10MHz -110dBc/Hz
Lock time 192μs
Table 4.1: System level Specifications of Synthesizer.
4.3 Block level specifications
From the given system a level specification, the VCO tuning range is 2.4GHz-
2.4835GHz and the phase noise is -110dBc/Hz. The VCO conversion gain is taken as
200MHz/V.
49
The constraint on the loop filter gain is it should be less than 1/10 th of the reference
frequency for stability concerns. And from the settling time constraint, it should be greater
than 1/4th of (1/settling time). So the bandwidth of the loop filter is taken as 30 kHz.
The divider used in this synthesizer is multi-modulus divider. The division ratio can
be found by dividing the tuning range with the reference frequency. So the division ratio in
this case is 480 – 495.
Parameter Value
Tuning range 2.4 GHz –2.4835 GHz
Conversion gain 200 MHz/V
Phase noise @ 10MHz offset -110dBc/Hz
Reference frequency 5 MHz
Charge pump current 10μA
Loop bandwidth 30kHz
Divide ratio 480 – 495
The difference between charging and
discharging current sources
<2%
Supply voltage 1.8V
Table 3.2: Block level specifications of synthesizer.
50
CHAPTER 5DESIGN AND IMPLEMENTATION
This chapter discusses the design and implementation of PLL’s sub blocks. The
problem characterization and specifications of these blocks have already been given in
chapter 3. It discusses circuit topologies and sub blocks identification for implementation of
PLL. All the sub blocks have been tried independently before final implementation. This
chapter starts with the design of VCO, followed by the design of charge pump and loop filter,
PFD, and divider.
Figure 47: PLL Based frequency synthesizer.
The PLL based frequency synthesizer is shown in Fig 47. A standard tri-state PFD as
shown in Fig.7 was implemented using two resettable flip-flops. To eliminate dead-zone a
delay element was added to the reset path. Because most gates used in the design of the PFD
are operating at a relatively slow speed of 40MHz, it was possible to minimize power
51
consumption without affecting signal performance. The charge pump as shown in Fig.11, is
responsible for adding or removing charge from the loop filter, which in turn will increase
or decrease the control voltage on the VCO. Careful design of charge pump is necessary
such that flicker and thermal noise contributors to in-band phase noise are mitigated. The
divider was formed by cascading 8 divide-by-2/3 stages to produce a maximum divide ratio
of 495 and a minimum divide ratio of 480.
5.1 Design of LC-VCO
For minimum power consumption and maximum output swing, a complementary
differential CMOS LC tuned voltage controlled oscillator [8] is implemented. Both the cross
coupled NMOS-transistor and PMOS-transistor generate a negative resistance that
compensates the loss of LC tank. The differential admittance for each pair is –gm/2 as shown
below.
Figure 48: Schematic of LC-VCO.
Illustration of Negative resistance transformation
52
I = -I =
V0 = V1 –V2 =
= - ( )
5.1.1 Design Constraints
VCOs are generally designed for minimum phase noise under constraints of d.c.
power dissipation, tuning range, output voltage swing and die area.Usually on-chip spiral
inductors are utilized for this type of VCO. These inductors usually dominate the chip area
required ranging in diameter from 100 to 500μm. The d.c. power dissipation is given by
VsupplyIbias ≤ Pdissipation_max ……………………….................................. (4.1)
The magnitude of the output voltage at the drains of the NMOS transistors is
governed, to first order, by the a.c. impedance of the lossy tank: Vtank = IbiasRp where Rp =
QLWoL and Vtank is the single-ended peak-to-peak voltage swing at either the + or - output
node of the VCO before any output buffering. The tuning range of a VCO is required to be in
excess of a certain minimum percentage of the centre frequency fo. The LC tank is made
tunable by implementing the ‘C’ of the LC tank using a varactor (variable capacitor). The
varactor is designed to be adjustable over some range Ctank min to Ctank max.
53
Assuming that
……………………………………... (4.2)
(i.e. that of an ideal tank) then,
LtankCtank_min = ; LtankCtank_max = …………(4.3)
Where (Wmax − Wmin)/WO = fractional tuning range and (Wmax + Wmin)/2 = WO
Total inductance Ltank=2L
Total capacitance 2Ctank= Cnmos +Cpmos + CL+ Cv+ Ccoarse + Cload
Cnmos=4Cgdn + Cgsn + Cdbn
Cpmos=4Cgdp + Cgsp + Cdbp
Total conductance 2gtank=gdsn + gdsp + gv + gL + gcoarse
gv = Effective parallel varactor conductance=> gv =(CmaxW)/Qv
gL =Effective parallel inductor conductance=>gL =1/Rp + Rs/(LW)2
Total negative Conductance gneg, tank= - (gm, n + gm, p)/2 = -gm, n
gm, n ≥ αg gtank
Qloaded = Rp/ω0L
Qloaded=QLQC
Since QL << QC ==> QL≈ Qloaded
The minimum criterion for oscillation is that the closed loop gain, α, is at least unity.
In practice designers set the gm of the NMOS transistors so that α exceeds the absolute
minimum value of 1 such that the minimum designed α becomes αmin > 1. A αmin of 2 or 3 is
often used. Finally, assuming that the on-chip spiral inductors are limiting chip-area one
usually determines the inductor diameter d such that it is ≤ some maximum possible value (d
≤dmax).
5.1.2 VCO Design Procedure
Certain design specifications must be given:
54
a) Maximum d.c. power dissipation = VsupplyIbias
b) Minimum output voltage swing (single-ended) = Vtank
c) Tuning range in percentage
% . …………………………..(4.7)
d) Frequency of operation (Wo)
The goal of the design is then to develop a VCO that meets the above constraints with
minimum phase noise. An alternative strategy may be to design a VCO with a pre-specified
phase noise but where the d.c. power dissipation is minimized.
Design Procedure Steps
The LC-VCO in dissertation is designed for the following specifications :
Supply 1.8V
Frequency tuning 2.4GHz – 2.4835GHz
Power consumption 4.4mW
1) Set Ibias = Pd.c. max / Vsupply
2) Determine maximum value for QL of inductors for a given process at required frequency
Wo. This can be determined in many ways including
i) Already known from previous design experience in that particular process
ii) Read from model elements in design kit
iii) Determined through exhaustive design and optimization of inductor using
electromagnetic simulation packages
iv) Measured data taken from test inductors already fabricated in the same process.
3) Using Vtank = IbiasRp = IbiasWoLQL, set value of L so that Vtank is at minimum required
voltage swing for the design. Ibias, Wo and QL are already known.
55
4) The series resistance of inductor can be calculated from .
Caution: Values of L must be chosen such that it is in a practical value range to be fabricated
as well as being at a value that results in a practical value of capacitance C, for the varactor.
5) The equivalent parallel resistance is given by RP=Q2RS.
6) The condition to produce the oscillations is given by , assuming
gmn1=gmn2=gmp3=gmp4=gm. From this, the value of gm can be calculated.
7) Using , (W/L)N1, (W/L)N2, (W/L)p1, (W/L)p2 can be calculated.
8) Using W0 = …………………………….. (4.8)
Where R = = effective series resistance of Inductor calculate the required value of C for
the LC tank with WO being the center frequency of the VCO.
9) Take transistor non-idealities into account to arrive at a new gm and also a transistor
width, W.
5.1.3 Designing a NMOS Varactor
1) Determine Cmax/Cmin ratio required for design:
Fractional tuning range =
Where fo = center oscillator frequency =
; ………... (4.9)
…………….......……………………….… (4.10)
56
2) MOS varactor layout considerations
a) Use channel length Lmin = minimum available L for maximum varactor quality factor Q
b) Determine MOS gate total width, W, using
……………………………….. (4.11)
c) Layout varactor using multi-finger gate to reduce gate series resistance such that Q of
varactor is reasonably high.
Figure 49: Fingered MOSFET gate.
……………………………….. (4.12)
Where Rg = total gate a.c. series resistance = . Assuming that the gate contact is
composed of polysilicon with sheet resistance and n = number of fingers and assuming
gate is connected from one end. If the gate is contacted from both ends then divide above
formula by 2. For balanced differential structures, layout two varactors for best matching. For
LC tank oscillators, a high Q for the varactor would be where Qvar _ Qinductor, e.g. Qvar = 40 to
50 when Qinductor = 10.
Results: Tuning Gain 200MHz/V
Phase Noise@1MHz -120 dbc
Noise Analysis:
57
Total output Noise =1.00157 e-09
Total input referred Noise =1.07789e08
RMS noise calculated is 31.64 v
5.2 Proposed Programmable divider (Vaucher divider)
In this, a fast programmable frequency divider with a wide dividing ratio range and
50% duty cycle is presented.
Specifications:
Supply 1.8V
Input frequency <3GHz
Frequency division ratio 480-495
Power consumption 6.8mW
A programmable frequency divider [4] can have a wide range of dividing ratios(
-1).We can specify the minimum power value ‘min’ and maximum power
value ‘max’.The binary control digits ( ) are used to set the dividing
ratios.The block diagram of Vaucher divider is shown in below fig. The proposed design has
modified internal building blocks of ‘Div_n_vaucher for higher frequency of operation and
reduced layout area. Each proposed block consists divide by 2 or 3. The first 2/3 divider
block needs to be operated at the input frequency, while the subsequent blocks will be
operated at reduced frequencies.
58
Figure 50: General architecture of a multi-modulus programmable divider
(1a) If all of or division ratio <
Division ratio = ...................(4.15)
(1b) otherwise (if any or
Division ratio ≥
Division ratio = +........
..................................................................(4.16)
If the dividing ratio< , set to loic 1 since ,.... =0
For the Div_n_vaucher min=n-2, max=n
So we need the division ratio from 480 to 495. So 8 stages are used.
Dividing ratio=
The D_latch and D_latch combined with AND gates are shown in figures.
59
Figure 51: Eight Multi-modulus Divider Chain.
Divide-by-2/3 cell
A 2/3 divider cell comprises two functional blocks, as depicted in figure 52. The
prescaler logic block divides, upon control by the end-of cycle logic, the frequency of the
CLK input signal either by 2 or by 3, and outputs the divided clock signal to the next cell in
chain. The end of- cycle logic controls the momentaneous division ratio of the cell,
depending on the state of its MODin and P inputs, and outputs the MOD-out signal to the
preceding 2/3 cell in the chain.
A divide-by-2/3 [4] cell comprises four latches and three AND gates as depicted in fig
53. The upper part (latch1 and latch2) commonly operates at divide-by-2 mode. Unless the
Mod-in (Mi) signal becomes active, and if P=1, latch3 forces the upper part to swallow one
extra period of the input signal. Here, we know if P = 0, latch3 has no contribution to the
operation of the whole divider. Its current can therefore be cut off. As to latch4, it incepts the
Mi signal from the subsequent cell, and provides the Modout (Mo) signal for the preceding
cell. The D-latch and And-latch implementations for the 2/3 divider cell are shown in
figure54.
60
Figure 52: 2/3 functional block
Figure 53: Prescaler Logic for divider
d-latch and and- latch implementations of 2/3 divider cell
Figure 54: D-latch and AND-latch circuits
5.2.1 Frequency divider with 50% duty cycle
61
Figure 55: Schematic of the proposed design with 50% duty cycle
The output pulse width of Vaucher’s design [4] is very narrow. Thus vouchers divider
has poor capability to drive other circuits. The circuit in fig (55) can generate an output with
very close to 50% duty cycle , while retaining the same dividing ratio as
To get 50% duty cycle, a divide by two divider ‘Div-2’ is added at the output of
Div_n Vaucher [4]. An AND gate and ‘n’bit haif adder are also included in the feedback
loop. The original output signal is (top middle part) , whose duty cycle is faroff
50%. The duty cycle of the proposed output ‘ ’is the output of Div-2 and the period of
changes very little, S0, S1, S2 .........,Sn are the dividing ratio controls of the
proposed divider .’S0’ is the LSB (Least Significant Bit), ’ and are the inputs of AND
gate is fed to the Cin input of the half adder .The outputs of the adder are used as the dividing
ratio controls for the ‘Div_n_Vaucher’.
Use ‘m’ to represent the binary combination of (S1, S2, S3........., Sn),
62
So m= .............................................(4.17)
For the Div_n Vaucher if the dividing ratio less than (or the proposed divider less
than ) set Pn-2 or Sn-1 to logic 1. Equation (4.17) can be used to represent the dividing
ratio of ‘Div_n Vaucher’. If S0 is ‘0’ the binary combination of the outputs will be equal to
‘m’.After Div_2 the ratio of will be equal to:
2*m=0+ ..........................................................(4.18)
If S0 is ‘1’ the signal at the Cin of the adder will oscillate between ‘0’ and ‘1’. The
binary outputs of the adder (or the dividing ratios of Div_n Vaucher) will have an average
value of (0.5+m). Thus average ratio of will be equal to
2*(0.5+m) =1+ .................................................(4.19)
Combining (4.18) and (4.19) the dividing ratio can be written as the following
+ ................... ...........................................(4.20)
So the circuit not only generates an output signal with close to 50% duty cycle, but also keeps
the step size of the dividing ratio to be 1.
5.3 Design of Charge pump and Loop filter
5.3.1 Loop Filter Design Criteria
Loop filter design is an important aspect of the frequency synthesizer design since
most performance parameters (phase noise‚ stability‚ lock time‚ reference spurs) of the
synthesizer depend on the loop filter parameters. A major design consideration in the design
of loop filter the PLL is to minimize the integrated phase noise to meet the specification by
changing charge pump current and loop bandwidth while meeting the lock time specification
and reference spur levels. For optimum design of the loop filter‚ one question may arise;
63
“should loop filter be placed off-chip or on chip‚ and why?”. The loop filter parameters Rz ,
Cz and Cp are designed for given PLL parameters; ICP, KVCO and N and for specified loop
bandwidth(Wc) and phase margin(Фm). The PLL parameters; VCO gain and feedback divide
ratio can be considered as design constants; however we have freedom to chose charge pump
current value. Each charge pump current value will result in a set of loop filter parameters for
given phase margin and loop bandwidth values. Smaller charge pump current results in
smaller loop filter capacitance values and hence ease the loop filter integration. Larger charge
pump current reduces the close in phase noise; and hence it reduces integrated phase noise.
Selection of a charge pump current value depends on the PLL requirements. If the integrated
phase noise requirement is relaxed or not constrained‚ this translates into relaxed close-in
PLL noise. When the close-in noise is relaxed or not constrained‚ the loop filter can be
integrated (on-chip) by making CP current as small as possible in order to make loop filter
capacitor values small enough so that their physical sizes are practically implementable. If the
integrated phase noise is tightly specified‚ then the CP current value and loop bandwidth are
concurrently changed to meet the integrated noise specification. Therefore‚ the loop filter
must be placed off-chip for noise optimization purposes; and this is the case for this design.
Figure 56: schematic of loop filter.
5.3.2 Loop filter design
The loop filter in this dissertation is designed with the following specifications:
VCO gain KVCO 200MHz/V
64
Charge pump current 10μA
Loop division ratio 480
Reference frequency 5MHz
Settling time 192µs
1). From the settling time, calculate the minimum loop bandwidth. To achieve a settling time
of 192µs, the minimum loop bandwidth calculated from
……………………………………. 4.17
is 20kHz. Here a loop bandwidth of fc = Wc / (2π) = 30kHz which is 50% more than the
minimum value, is chosen. Note that there are also other limitations on the loop bandwidth.
For example, the loop bandwidth should be less than 1/10 of the reference frequency for
stability concerns. Moreover, the loop bandwidth affects the noise transfer characteristic of
the PLL. To minimize the phase noise, the optimal loop bandwidth is where the high-pass
VCO noise contribution is equal to the total low-pass noise contribution from the reference,
PFD and charge-pump, etc.
2). since the reference spur level requirement is not very stringent, a second order passive
loop filter is adopted. Choose Wz = Wc/22 and Wp2 = 22Wc that is, fz = Wz/2π = 7.5kHz and fp2
= Wp2/(2π) = 120kHz Therefore, the phase margin calculated from
……………….. 4.18
is Фm = 620. A large phase margin helps cover variations of the VCO conversion gain and
loop filter values to guarantee the loop stability. Now, with a charge-pump current of Icp =
10µA, the loop filter values R1, C1 and C2 can be calculated from
………………………………………4.19
65
…………………………..4.20
From the above equation, calculated R1 = 43.02kΩ Therefore, the two capacitors are C1 =
1/(WzR1) = 499pF and C2 = 1/(Wp2R1) = 31pF.
5.3.3 Charge pump circuit Design
Specifications of this block are as follows:
Supply 1.8V
Current consumption 10μA
The difference between charging <2%
and discharging current sources.
The Charge pump designed in this is as shown in Fig.57. The circuit consists of a PMOS
current mirror (M5 and M6) to mirror IUP into the charge pump. This IUP current either goes
into the loop filter or into the ground node depending on the position of the two PMOS
switches (M1 and M2). AN NMOS current mirror (M7 and M8) is used to mirror IDOWN into
the charge pump. This IDOWN current either discharges the loop filter or pulls current from the
ground node depending on the position of the two NMOS switches (M3 and M4). IUP and
IDOWN are both set equal to insure a constant phase detector gain.
66
Figure 57: schematic of charge pump
These currents are set to the following value.
IUP=IDOWN=10uA
The charge pump must satisfy a certain voltage compliance to generate a relatively
constant output current over the output range of the VCO control voltage. The VCO has a
tuning range of 0.8V with a 1.8V supply. This implies the following compliance voltage.
Charge pump voltage Compliance = 500mV from each rail.
Charge pump design Procedure
The design Procedure for the charge pump is presented. The charge pump sources or
sinks 10uA of current over an output voltage range of 0.8V
1. Set the proper VDSAT values for transistors M5 and M7 to satisfy the voltage compliance
range. The VDSAT for M5 and M7 is set to 0.3V to insure that they don’t go out of saturation
when the output node swings from 1.3v to 0.5V. This VDSAT value also allows for a possible
0.2V drop across the switch transistors M1-4. A VDSAT value of 0.3V results in the following
minimum sizes for M5, M6, M7, and M8.
=> (W/L) 5, 6 >2ID/(K’pV2dsat)
67
=> (W/L) 7,8 >2ID/(K’nV2dsat)
2. Size of the switch transistor M1-4 to insure that voltage drop across the switches does
not exceed 0.2V. In order to meet this requirement a value of 0.15V is used for calculation.
This results in the following minimum sizes for M1-4.
(W/ L) 1,2,3,4 > ID / Kp (|VGS|-|VT0|) (|VDS|)
M13 and M14 are resistor implementations, while M9-10 is a current sink which has sizes
equal to M7; transistor M11-12 is a current source which has sizes equal to M6.
Mismatch of IDOWN and IUP produces jitter in the loop. So enough care is taken to make
the currents closely. For a simple charge pump using pass transistors has the disadvantages of
charge sharing and clock feed through. This particular topology eliminates charge sharing by
including another switch which will be ON complimentary to the main switch of the charge
pump. This makes the charge on the source of the switch to be same even when they are
switching OFF and ON.
5.4 Design of Phase Frequency Detector
In this, a high speed and low power phase frequency detector (PFD) [7] is designed
using a modified TSPC (true single phase clock) positive edge triggered flip flop. The
proposed PFD has a simple structure with using only 16 transistors. The operation of the PFD
is over 1.4G HZ without using additional prescaler circuits. Furthermore, the PFD has a dead
zone less than 0.01ns in the phase characteristics and has low phase sensitivity errors.
The input phase errors are detected by phase detector (PD) or phase frequency
detector (PFD). These errors, phase or frequency, are converted into current or voltage to
control the output frequency of voltage controlled oscillator (vco) by charge pump in a charge
pump PLL. PD detects a phase error between the reference signal and the output signal of
PLL. Thus the error detection range can be extended with PFD.
5.4.1 Design of Positive edge triggered D-FF for high speed PFD circuit
The operation of proposed D-FF (shown in Fig.58) is as follows [7]. When the input
clock and reset signals are low, node A is connected to VDD through m1, mr1, and charges the
node A to VDD. At the rising edge of the clock signal, node B is connected to ground through 68
m3 & m4. Once the node A is charged to VDD, the node B is not affected by input clock
signal. Because the charges at node A turns off the m3 & this prevents the node B from being
pulled up. Therefore the node B is disconnected from input node. When the reset signal is
applied, node A is disconnected from VDD by mr1 and is connected to ground by mr2. As
soon as the node A is discharged, the node B is pulled up through m2. The mr1 is added to
prevent the short circuit that occurs whenever the reset signal is applied. When the clock
signal is low while the reset signal is high, a current path is made from VDD to ground if mr1
is not provided. This increases the short circuit power consumption. Dynamic power
consumption can be reduced by internal switching and speed is increased by shortening the
input to output path.
Figure 58: Proposed D-Flip Flop
Design of PFD circuit
Full schematic of the proposed PFD [7] is shown in fig.59. Tthe proposed DFF are
used as a positive edge triggered D flip-flops. This structure detects phase errors within –Π to
+Π between the input signals.
The operation of the PFD is shown in fig.59 using input clock signals. If the U1
(resp.U2) signal makes transition from low to high. UP (resp.DN) signal goes to high. As
soon as the U2 (resp.U1) signal goes to high, the U2 reset the F/F1 (resp F/F2). The output of
the other flip flop cannot make transition to high state because U1 signal is asserted to reset
69
input. The high speed operation is accomplished with the proposed PFD because the
proposed PFD structure has no feedback network to reset the flip flop in PFD.
Figure 59: Schematic of the proposed PFD
5.4.2 Addressing the Dead Zone problem
Dead Zone [19] is the cross over distortion of PLL in the region where the charge
pump currents cannot flow proportionally to the phase error. The main cause of the dead zone
is relationship between the propagation delay of the internal gates for the reset of the PFD
and the switching time of the charge pump currents. In PLL application appropriate delay is
added in the PFD reset path to avoid the dead zone problem. Unfortunately, because of this
delay, there will be short pulses on both the up and down signals, even in the locked state.
Thus the charge pump current will switch ON and OFF, a current spikes will appear on the
charge pump output at the reference frequency.
To avoid the dead zone problem the delay of PFD reset path (TR) to be longer than the
charge-pump current switching time (Tth).
70
Figure 60: Schematic of the proposed PFD without delay
Figure 61: Timing diagrams of PFD and charge-pump: (a) TR < Tth and (b) TR > Tth.
71
CHAPTER 6RESULTS
6.1 Transient analysis of VCO
72
6.2 Phase noise analysis of VCO
6.3 Periodic steady state response of VCO
VCO Center Frequency= 2.433GHz
VCO Sensitivity =200MHz/V
73
Phase Noise is 121dbc@1MHz
6.4 Output of the PFD When Fref=Fdiv
74
6.5 Output of the PFD When Fref leads Fdiv
75
6.6 Output of the PFD When Fref not equal to Fdiv
76
6.7 Results of integrated charge pump and loop filter
77
6.8 Frequency divider output for N=480
Dividing ratio S8 S7 S6 S5 S4 S3 S2 S1 S0=111100000
6.9 Frequency divider output with 50% duty cycle
Dividing ratio S8 S7 S6 S5 S4 S3 S2 S1 S0=111100000
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7.0 output of D-Latch used in divider
The output pulse width of Vaucher’s frequency divider (Fig.70) is very narrow. Thus
vaucher’s divider has poor capability to drive other circuits. To get 50% duty cycle, a divide
by two divider ‘Div-2’ is added at the output of Div_n Vaucher. Fig.71 shows the output of
the divider (dividing ratio is 480) with 50% duty cycle.
7.1 Lock in process of Frequency Synthesizer
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CHAPTER 7CONCLUSIONS
2.4-2.4835GHz range fully-integrated CMOS PLL integer-N frequency synthesizer
has been implemented in 0.18μm umc-CMOS technology. It is compliant to ZigBee standard.
Power consumption of the total circuit is reduced to 14.8mW with 1.8V supply. The VCO
section contributed to 30% of the total power. Measured phase-noise is -120 dBc@1MHz
offset.
The sensitivity of the VCO was measured to be around 200 MHz/V with broadband
tuning range from 2405-2480 MHz. Noise analysis is also performed for the VCO section
and the RMS noise calculated is 31.64 v. Lock time of the synthesizer is observed with in
30μs.
It is favorable in low power, low cost transceiver design. Power consumption can be
further reduced by decreasing supply and using high Q inductor. Increasing Q factor would
also reduce phase noise.
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REFERENCES
[1] IEEE Standard for information technology – telecommunications and information exchange between systems – local and metropolitan area networks specific requirements part 15.4 – wireless medium access control (MAC) and physical Layer (PHY) specifications for low-rate wireless personal area networks(LRWPANs), IEEE Standard 802.15.4, 2003.
[2] Behzad Razavi, “Design of Analog CMOS Integrated Circuits Design,” McGraw-Hill publications.
[3] Saurabh Kumar Singh, T K Bhattacharyya “7.95mW 2.4GHz Fully Integrated CMOS integer N Frequency Synthesizer”, VLSI Design, 2007. 20th International Conference on VLSI Design
[4] MO zhang, Syed kamrul Islam “A fast programmable frequency divider with a wide dividing ratio range and 50% duty cycle “IEICE electronic express, vol 4,no.21,672- 678.NOV,2007.
[5] Nesreen Mahmoud Hammam Ismail “Low Power Phase locked loop Frequency Synthesizer for 2.4 GHz Band Zigbee” American J.of Engineering and Applied Sciences: 337-343.2009.
[6] Jie Long, Jo Yi Foo and Robert J. Weber “A 2.4GHz Low-Power Low-Phase-Noise CMOS LC VCO” Proceedings of the IEEE Computer Society Annual Symposium on VLSI Emerging Trends in VLSI Systems Design (ISVLSI’04)
[7] Won-Hoy LEE, Sung-Dae LEE “A High speed, Low power phase frequency detector and charge pump circuits for High frequency Phase locked loop” IEICE trans.fundamentals,vol.E82-A,No.11, Nov2006.
[8] S. K. Singh, T. K. Bhattacharyya, A. Dutta, “Fully integrated CMOS frequency synthesizer for ZigBee applications”, VLSI Design, 2005. 18th International Conference, Page(s):780 – 783, 3-7 Jan. 2005.
[9] F. M. Gardner, “Charge-Pump Phase-Lock Loops”, IEEE Transactions on Communications, vol. COM-28, pp. 1849-1858, Nov. 1980.
[10] K. T. Le, “Designing a Zigbee-ready IEEE 802.15.4-compliant radio transceiver,” RF Design, pp. 42-50, November 2004, [Online]. (http://www.rfdesign.com)
[11] IEEE Wireless LAN Medium Access Control (MAC) and Physical layer (PHY) specifications: High-Speed Physical Layer in the 5 GHz Band, IEEE 802.11a, 1999.
81
[12] IEEE Wireless LAN Medium Access Control (MAC) and Physical layer (PHY) specifications: Higher-Speed Physical Layer Extension in the 2.4 GHz Band, IEEE 802.11b, 1999.
[13] IEEE Wireless LAN Medium Access Control (MAC) and Physical layer (PHY) specifications: Amendment 4: Further Higher Data Rate Extension in the 2.4 GHz Band, IEEE 802.11g, 2003
[14] Specification of the Bluetooth System, v1.0BAvailable: http://www.bluetooth.com.
[15] IEEE Wireless Medium Access Control (MAC) and Physical layer (PHY) specifications for High Data Rate Personal Area Networks (WPANs), IEEE Std. 802.15.3, 2003.
[16] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, New York: Cambridge University Press, 1998.
[17] B. Razavi, RF Microelectronics, Upper Saddle River, New Jersey: Prentice-Hall PTR, 1998
[18] Tiebout Marc, “Low power Low phase noise differential tuned quadrature vco designed in standard CMOS”, solid-state circuits, IEE journal of, vol.36, No.7, pp. 1018-1024, july.2001.
[19] “Scheme for No Dead Zone, Fast PFD Design” Han-il Lee,_ Tae-won Ahn, RFIC Development, Journal of the Korean Physical Society, Vol. 40, No. 4, April 2002, pp. 543_545
82
ContentsINTRODUCTION...............................................................................................................................1
1.1 Background and Motivation............................................................................................................1
1.2 Thesis Organization.........................................................................................................................2
LITERATURE SURVEY...................................................................................................................3
2. Phase Locked Loop Fundamentals ............................................................3
2.1 Introduction to PLL.........................................................................................................................3
2.2 PLL Components.............................................................................................................................4
2.2.1 Phase Frequency Detector........................................................................................................4
2.2.1.a. Problem of Lock Acquisition............................................................................................5
2.2.1. b Dead Zone.........................................................................................................................8
2.2.2 Charge pump............................................................................................................................9
2.2.2.a Charge pump architectures...............................................................................................10
2.2.2.b Non Ideal Effects in Charge Pump...................................................................................11
2.2.2.c Single Ended and Differential Charge Pumps..................................................................12
2.2.2.d Advantages of Differential Charge Pumps.......................................................................13
2.2.2.e Limitations of Differential Charge Pumps....................................................................13
2.2.2.f Limitations of Single Ended Charge Pumps..................................................................13
2.2.3 LOOP FILTER.......................................................................................................................14
2.2.4 Voltage Controlled Oscillator.................................................................................................16
2.2.4. a Introduction to VCO.......................................................................................................16
2.2.4.b Oscillation Conditions.....................................................................................................17
2.2.4.c Performance parameters of VCOs....................................................................................19
2.2.4.1 LC –Oscillators................................................................................................................22
2.2.4.2 Ring Oscillators...............................................................................................................22
2.3 PLL-based Frequency Synthesizer.................................................................................................31
2.3.1 Integer-N PLL Frequency Synthesizers..................................................................................31
2.3.2 Fractional-N PLL Frequency Synthesizers.............................................................................32
2.4 Divider Architecture and Hierarchy...............................................................................................33
ZIGBEE FREQUENCY SYNTHESIZER.......................................................................................35
3.1 Wireless Standards........................................................................................................................35
3.2.1 Frequency Synthesis...............................................................................................................37
3.2.2 Phase Noise............................................................................................................................38
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3.2.3 Spur Rejection........................................................................................................................40
3.2.4 Settling Time..........................................................................................................................42
3.3 Synthesizer Architecture................................................................................................................42
3.4 System Level Design.....................................................................................................................44
3.4.1 Theory....................................................................................................................................44
PROBLEM CHARACTERIZATION AND SPECIFICATIONS.................................................46
4.1 Zigbee Transceiver........................................................................................................................46
4.2 System level specifications............................................................................................................47
4.3 Block level specifications..............................................................................................................48
DESIGN AND IMPLEMENTATION.............................................................................................50
5.1 Design of LC-VCO........................................................................................................................51
5.1.1 Design Constraints..................................................................................................................52
5.1.2 VCO Design Procedure..........................................................................................................53
5.1.3 Designing a NMOS Varactor..................................................................................................55
5.2 Proposed Programmable divider (Vaucher divider).......................................................................57
5.2.1 Frequency divider with 50% duty cycle..................................................................................60
5.3 Design of Charge pump and Loop filter........................................................................................61
5.3.1 Loop Filter Design Criteria.....................................................................................................61
5.3.2 Loop filter design....................................................................................................................62
5.3.3 Charge pump circuit Design...................................................................................................64
5.4 Design of Phase Frequency Detector.............................................................................................66
5.4.1 Design of Positive edge triggered D-FF for high speed PFD circuit.......................................66
5.4.2 Addressing the Dead Zone problem........................................................................................68
RESULTS...........................................................................................................................................70
6.1 Transient analysis of VCO.............................................................................................................70
6.2 Phase noise analysis of VCO.........................................................................................................70
6.3 Periodic steady state response of VCO..........................................................................................71
6.4 Output of the PFD When Fref=Fdiv..............................................................................................72
6.5 Output of the PFD When Fref leads Fdiv......................................................................................72
6.6 Output of the PFD When Fref not equal to Fdiv............................................................................73
6.7 Results of integrated charge pump and loop filter.........................................................................74
6.8 Frequency divider output for N=480.............................................................................................75
6.9 Frequency divider output with 50% duty cycle..............................................................................75
84
7.0 output of D-Latch used in divider..................................................................................................76
7.1 Lock in process of Frequency Synthesizer.....................................................................................76
CONCLUSIONS................................................................................................................................77
REFERENCES..................................................................................................................................78
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LIST OF FIGURES
FIGURE 1: BASIC BLOCK DIAGRAM OF PLL...........................................................................................................3FIGURE 2: INDIVIDUAL BLOCKS OF PLL................................................................................................................4FIGURE 3: DEFINITION OF PHASE DETECTOR..........................................................................................................4FIGURE 4: EXCLUSIVE OR GATE AS PHASE DETECTOR...........................................................................................5FIGURE 5: ADDITION OF FREQUENCY DETECTION TO INCREASE THE ACQUISITION RANGE.....................................6FIGURE 6: CONCEPTUAL OPERATION OF A PFD......................................................................................................6FIGURE 7: IMPLEMENTATION OF PFD....................................................................................................................7FIGURE 8: INPUT-OUTPUT CHARACTERISTIC OF THE THREE-STATE PFD................................................................7FIGURE 9: DEAD ZONE..........................................................................................................................................8FIGURE 10: PHASE ERROR VS. OUTPUT VOLTAGE.................................................................................................9FIGURE 11: PFD FOLLOWED BY LOW-PASS FILTERS...............................................................................................9FIGURE 12: PFD WITH CHARGE PUMP..................................................................................................................10FIGURE 13: SIMPLIFIED SCHEMATIC OF GENERIC CHARGE-PUMPS........................................................................10FIGURE 14: CURRENT STEERING CHARGE-PUMPS.................................................................................................11FIGURE 15: CURRENT STEERING CHARGE-PUMPS.................................................................................................12FIGURE 16: SIMPLE CHARGE-PUMP PLL...............................................................................................................14FIGURE 17: (A) LOOP GAIN CHARACTERISTIC OF SIMPLE CHARGE-PUMP PLL (B) ADDITION OF ZERO.................15FIGURE 18: ADDITION OF ZERO TO CHARGE-PUMP PLL.......................................................................................15FIGURE 19: ADDITION OF C2 TO REDUCE RIPPLE ON THE CONTROL VOLTAGE.....................................................16FIGURE 20: DEFINITION OF VCO.........................................................................................................................16FIGURE 21: OSCILLATOR REPRESENTATION BY: (A) THE FEEDBACK SYSTEM, (B) THE ONE PORT VIEW................17FIGURE 22: RESONATOR TANK CIRCUIT...............................................................................................................22FIGURE 23: LC OSCILLATOR MODEL....................................................................................................................22FIGURE 24: RING OSCILLATOR STRUCTURE..........................................................................................................23FIGURE 25: RING OSCILLATOR STRUCTURE..........................................................................................................24FIGURE 26: WAVEFORMS OF RING OSCILLATOR WHEN ONE NODE IS INITIALIZED TO VDD.................................26FIGURE 27: FOUR-STAGE DIFFERENTIAL RING OSCILLATOR.................................................................................27FIGURE 28: DIFFERENTIAL PAIR WITH VARIABLE OUTPUT TIME CONSTANT.........................................................27FIGURE 29: THE DEFINITION OF PHASE NOISE......................................................................................................29FIGURE 30: PHASE NOISE IN OSCILLATOR............................................................................................................29FIGURE 31: GENERIC WIRELESS TRANSCEIVER...................................................................................................30FIGURE 32: EFFECT OF PHASE NOISE ON RECEIVE AND FIGURE 33: TRANSMIT PATHS......................................30FIGURE 34: INTEGER N SYNTHESIZER ARCHITECTURE.........................................................................................31FIGURE 35: FRACTIONAL-N FREQUENCY SYNTHESIZER ARCHITECTURE..............................................................32FIGURE 36: MULTI-MODULUS DIVIDER ARCHITECTURE.......................................................................................34FIGURE 37: MAPPING STANDARD TO KEY SYNTHESIZER SPECIFICATIONS..........................................................37FIGURE 38: DOWN CONVERSION IN A TRANSCEIVER...........................................................................................38FIGURE 39: PHASE NOISE CONTRIBUTION SNR AT INPUT OF IF TO SECTION......................................................39FIGURE 40: LEESON PHASE NOISE MODEL.........................................................................................................40FIGURE 41: SOURCES OF REFERENCE SPUR IN AN INTEGER-N PLL BASED SYNTHESIZER...................................41FIGURE 42: EFFECT OF SPURS ON SNR AT INPUT OF IF SECTION.......................................................................41FIGURE 43: INTEGER-N PLL BASED SYNTHESIZER..............................................................................................43FIGURE 444: CHARGE PUMP PLL........................................................................................................................44FIGURE 45: POLE-ZERO PLACEMENT...................................................................................................................45FIGURE 46: TRANSCEIVER ARCHITECTURE..........................................................................................................46FIGURE 47: PLL BASED FREQUENCY SYNTHESIZER.............................................................................................50FIGURE 48: SCHEMATIC OF LC-VCO..................................................................................................................51
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FIGURE 49: FINGERED MOSFET GATE................................................................................................................56FIGURE 50: GENERAL ARCHITECTURE OF A MULTI-MODULUS PROGRAMMABLE DIVIDER....................................57FIGURE 51: EIGHT MULTI-MODULUS DIVIDER CHAIN.........................................................................................58FIGURE 52: 2/3 FUNCTIONAL BLOCK....................................................................................................................59FIGURE 53: PRESCALER LOGIC FOR DIVIDER.......................................................................................................59FIGURE 54: D-LATCH AND AND-LATCH CIRCUITS...............................................................................................59FIGURE 55: SCHEMATIC OF THE PROPOSED DESIGN WITH 50% DUTY CYCLE.......................................................60FIGURE 56: SCHEMATIC OF LOOP FILTER..............................................................................................................62FIGURE 57: SCHEMATIC OF CHARGE PUMP...........................................................................................................64FIGURE 58: PROPOSED D-FLIP FLOP....................................................................................................................67FIGURE 59: SCHEMATIC OF THE PROPOSED PFD..................................................................................................67FIGURE 60: SCHEMATIC OF THE PROPOSED PFD WITHOUT DELAY.......................................................................68Figure 61: Timing diagrams of PFD and charge-pump: (a) TR < Tth and (b) TR > Tth......................................69
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