automating thermo-mechanical warpage estimation of pcbs/pcas using a design-analysis integration...
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Automating Thermo-Mechanical Warpage Estimation of PCBs/PCAs Using a Design-Analysis Integration Framework
Authors:Manas Bajaj (Georgia Tech), Russell Peak (Georgia Tech), Dirk Zwemer (AkroMetrix), Thomas Thurman (Rockwell Collins), Lothar Klein (LKSoft), Giedrius Liutkus (LKSoft), Kevin Brady (NIST), John Messina (NIST), Mike Dickerson (InterCAX)
Presenter: Russell Peak
v3 - 2006-07-07
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AbstractAccurate prediction, validation and reduction of thermally-induced PCB warpage are critical for enhancing manufacturing yield and reliability in time-to-market driven electronics product realization.
In this paper, we describe a methodology to simulate thermally-induced warpage of PCBs and PCAs. We will demonstrate this analysis methodology using the following path: read ECAD designs from Mentor Graphics Board Station, identify features relevant to warpage analysis, create idealized analysis models, select solution technique and create solver-specific models (e.g. ANSYS and ABAQUS models for finite-element solution), identify warpage hotspots and calculate metrics to assist PCB/A designers in reducing warpage. We shall also present initial results from experimental verification of this technique using a shadow moiré (TherMoiré®) method.
This methodology provides highly automated simulation capabilities using analysis concepts, idealizations, and solution techniques for modularized and configurable simulation studies. It leverages open standards including ISO 10303 (STEP AP210 – www.ap210.org and Standard Data Access Interface - see www.jsdai.net).
http://eislab.gatech.edu/pubs/conferences/2006-user2user-bajaj/
Resources:(a) http://www.InterCAX.com/warpage
(b) http://eislab.gatech.edu/projects/nist-warpage/
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Contents Warpage Context
— Definition and impact— PCB/A features affecting warpage— Requirements for warpage analysis
Sample simulation results and validation— Bare boards (PCBs)— Assembled boards & chip pkgs. (PCAs, BGAs)
Methodology and tools— Multi-representation architecture— Tool availability
Summary
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Electronics Product Realization
Environmental
Placement
Fabricate Test/Inspect
Part Symbol& Footprint
Assemble
Doc/Proc/RegGuidelines
Corrections
Release
Learn todayUtilize tomorrow
Functional
Layout
Req
uir
emen
ts
Routing Review
Des
ign
Build
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Warpage - Definition
WARPAGE is out of plane deformation of the artifact, caused by differential (non-homogenous) shrinkage or expansion of elements composing the artifact.
Out of plane deformation of a linear element
Basic Model
= (b L2 T) / t where
L: Undeformed Length; t: Undeformed Thickness; T: Temperature Change; b: Specific Coefficient of Thermal Bending
Saddle Deformation
Bowl Deformation
Warpage of 2D artifacts ( basic modes)
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PCA/B Warpage - Illustration
Undeformed Shape
Deformed Shape
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Warpage – Impact and RequirementsRef: Thinking Globally, Measuring LocallyEditorial by Patrick Hassell, AkroMetrix
Impact Low manufacturing yield and high rework of
interconnects— Lack of co-planarity of component footprints— Fine pitch technology— Low solder paste volume
Requirements Managing warpage requirements
— Enforce local warpage requirements— Relax global warpage requirements
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Factors— CTE mismatch: global & local— Temperature / humidity variation— Temperature / humidity gradient— Material rigidity— Thermal conductivity— Geometric size & aspect ratio— Component layout
Consequences— Misregistration— Solder opens — Solder shorts— Delamination— Solder fatigue— Die cracking
Underfill
PWBVias Solder Balls
Molding BGA SubstrateDie/Chip
Estimated Impact: $100M / year
Warpage Effects[after Ding, 2003; Zwemer, 2006; et al.]
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Contents Warpage Context
— Definition and impact— PCB/A features affecting warpage— Requirements for warpage analysis
Sample simulation results and validation— Bare boards (PCBs)— Assembled boards & chip pkgs. (PCAs, BGAs)
Methodology and tools— Multi-representation architecture— Tool availability
Summary
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Complex Features Affecting Thermo-Mechanical Behavior
PCB Level
PCB outline
Mechanical (tooling / drilling) hole
Traces
Land
Plated through hole
Via
Footprint occurrence
Complete trace curve not shown
M150P2P11184
M150P1P21184
Features on PCB - Notional Figure
PCB Layout
Stackup
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Complex Features Affecting Thermo-Mechanical Behavior PCA Level: Complex Components
Solder Resist
Solder Resist
Cu Foil
Cu Foil
Cu Foil
Cu Foil
BT-Resin Core
BT-Resin Core
BT-Resin Core
Mold Resin
Si Chip
Die Attach
Solder Balls (Diagonal Grid Pattern)
Photo: www.shinko.co.jp
Isometric View Side View
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Contents Warpage Context
— Definition and impact— PCB/A features affecting warpage— Requirements for warpage analysis
Sample simulation results and validation— Bare boards (PCBs)— Assembled boards & chip pkgs. (PCAs, BGAs)
Methodology and tools— Multi-representation architecture— Tool availability
Summary
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Requirements for Warpage Analysis
Availability of a rich product model— ECAD design details— PCB layer stackup details— Material behavior and properties
Analysis model creation capabilities— Idealized PCB/A features— Boundary conditions— Thermal loading
FEA model creation and solution capabilities— FE mesher— FE solver
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Eagle Traditional Tools Mentor
Graphics
ElectricalCAD Tools
AP210
Doors
TeamcenterRequirements
Systems EngineeringTools
Pro/E
NX
MechanicalCAD Tools
…
AP203, AP214 AP233, SysML
Collective Product ModelBuilding Blocks: • Information models & meta-models:
• International standards• Industry specs• Corporate standards• Local customizations
• Modeling technologies:• Express, XML, UML, OWL, …
XaiToolsPWA-B LKSoft, …Gap-Filling
ToolsXaiToolsPWA-B
EPM, LKSoft, Theorem, …
STEP-Book AP210,SDAI-Edit,...
Instance Browser/EditorPWB Stackup Tool,…
pgef
EngineeringFramework Tool
AP210 AP2xx
Standards-based Submodels
Rich Product Modelhttp://eislab.gatech.edu/pubs/journals/2004-jcise-peak/
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Product Enclosure
External Interfaces
Printed Circuit Assemblies(PCAs/PWAs)
Die/Chip Package
Packaged Part
InterconnectAssembly
Printed Circuit Substrate (PCBs/PWBs)
Die/Chip
STEP AP210 (ISO 10303-210) Domain: Electronics DesignR
~1200 standardized concepts (many applicable to other domains)Development investment: O(100 man-years) over 10+ years
2003-04 - Adapted from 2002-04 version by Tom Thurman, Rockwell-Collins
Configuration Controlled Design of Electronic Assemblies,their Interconnection and Packaging
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STEP AP210 (ISO 10303-210) Scope
Assembly Models
• User View• Design View• Component Placement• Material Product• Complex Assemblies with Multiple Interconnects
Component / Part Models• Analysis Support • Package• Material Product• Properties• “White Box”/ “Black Box”• Test Bench
Requirements Models
• Design• Constraints• Interface• Allocation
Functional Models
• Functional Unit• Interface Declaration• Network Listing• Simulation Models• Signals• Test Bench
Interconnect Models• Usage View & Design View• Bare Board Design• Layout Templates• Layers and Layer Technologies• Stackup
Configuration Mgmt• Identification• Authority • Effectivity • Control• Net Change
• Geometric Dimensioning and Tolerancing
Design Control
Rules Models• Design• Manufacturing• …
Geometric Models• 2D• 3D• CSG, Brep…• EDIF, IPC, GDSII compatible “trace” model
http://www.ap210.orgUsed for warpage analysis
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Example Design in STEP Book AP210 Pro (PCB Layout View)
Originating ECAD Model from: Mentor Board Station
Current Tool: STEP Book AP210 v2.3
Current Model based on: STEP AP210
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Example Design in XaiTools PWA-B 2.0.b1 Stackup Editor
Originating ECAD from: Mentor Board Station
Current Tool: XaiTools PWA-B v2.0.b1
Current Model based on: STEP AP210
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PCB Warpage Analysis Model Creation
Grid (Sieve) Size
Single Layer View
…
Top view of “effective” grid elements in top layer of the PCB
…
Side view of the PCB with “effective” grid elements across
the stratums
thickness
wid
th
length
Given:
• Thermal loading profile
• Boundary Conditions (mostly displacement)
• Idealize PWB stackup as a layered shell
Building Block-based Analysis ModelAP210-based Manufacturing Product Model
Context
Effective Material Property
Computation
Context Attributes
• Thermal loading profile
• Boundary Conditions (mostly displacement)
• Idealize PWB stackup as a layered shell
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Contents Warpage Context
— Definition and impact— PCB/A features affecting warpage— Requirements for warpage analysis
Sample simulation results and validation— Bare boards (PCBs)— Assembled boards & chip pkgs. (PCAs, BGAs)
Methodology and tools— Multi-representation architecture— Tool availability
Summary
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Chopped PCB Regions for Analysisin XaiTools PWA-B 2.0.b1
First (Top) Design Layer
Second (Bottom) Design Layer
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Example Design - Coeff. of Thermal Bending Results in XaiTools PWA-B 2.0
Regions with greatest
mismatch
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Example Design – Finite Element Model Creation and Solution Input to ANSYS
ANSYS APDL-based description for creating and solving the finite-element model
XaiTools PWA-B 2.0.b1
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Example Design – FEA Warpage Results Out-of-plane deformation
Conditions
T = 125 deg. C - uniform heating from 25 deg. C to 150 deg. C
Y-min and Y-max edges are fully constrained
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Overall Process - Circuit Board Stackup Design &
Warpage Analysis Using AP210 (WIP)GIT and NIST EEEL in collaboration with AkroMetrix, InterCAX/LKSoft, and Rockwell Collins
ECAD and STEP AP210-basedProduct Model
Identification of warpage “hotspots” on a PCB
thickness…
wid
th
length
Analysis Building Block Model (idealized bodies with effective material properties)
PCB Warpage Profile(given: thermal profile +
boundary conditions)
Design Improvement Feedback
http://eislab.gatech.edu/projects/
CTB Map
(smeared property to identify material
distribution)
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-50
0
50
100
150
200
Te
mp
era
ture
(C
)
0
5
10
15
20
25
Model Exp't
Sca
le (
mil
s)
0 C
Simulation Results
Measurement Results
Physical Measurements in TherMoiré oven chamber
www.AkroMetrix.com
SMM - FEA Mesh Model
PCB Warpage: Validation Resultshttp://eislab.gatech.edu/pubs/conferences/2004-eurosime-zwemer/
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BoardStation “Module 10” Example in SB210 Pro v2.3
9 layer board
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Module 10: Idealization Grids for Effective Material Properties
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Module 10: CTB Maps
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out-of-plane deformation (Uz) in inchesdelta T = 150 C
Module 10: FEA Warpage Results
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Recent Production Test Cases
Test Case Name CAD SourceAP210 File
SizeNo. of
Components (MB) Conductive Total (approx.)
Design - 05 Zuken Visula 119.3 9 23 619Design - 07 Zuken Visula 39.4 10 22 559Design - 002J BOT Zuken Visula 18.9 1 1 1012Design - 002J MOD Zuken Visula 100.6 12 25 1757Design - 002J TOP Zuken Visula 29.5 1 1 745Cable DB Mentor Board Station 1.0 2 5 80Surface Mount Flasher Mentor Board Station 0.5 2 5 12
No. of Layers
—- Need more Mentor designs for testing — (collaboration opportunity!)
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Proprietary
Image Deleted
Design-07
Co-efficient of Thermal Bending (per deg C) Warpage Profile (z-axis deflection) – 25C to 150 C
559 components
10 circuit layers
Source ECAD Tool: Zuken Visula
PCA viewed in STEP Book AP210 Pro
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Proprietary
Image Deleted
Design – 02MOD
Warpage Profile (z-axis deflection) – 25C to 150 C
Co-efficient of Thermal Bending (per deg C)
1757 components
12 circuit layers
Source ECAD Tool: Zuken Visula
PCA viewed in STEP Book AP210 Pro
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Contents Warpage Context
— Definition and impact— PCB/A features affecting warpage— Requirements for warpage analysis
Sample simulation results and validation— Bare boards (PCBs)— Assembled boards & chip pkgs. (PCAs, BGAs)
Methodology and tools— Multi-representation architecture— Tool availability
Summary
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PCA Warpage Automated Analysis Model Creation
PCB = printed circuit board (bare board) PCA = printed circuit assembly = PCB + components, etc.
c2. Idealized component designs (APMs) and simulation templates (CBAMs)
c3. Analytical system models (ABBs) (~400 analytical bodies per component)
analytical assembly view
c1. component designs / libraries(e.g., chip packages like
plastic ball grid arrays (PBGAs) )
exploded view
b3. Analytical system model (ABBs) (~50 analytical multi-layer shell bodies)
a1. PCA designplus b1. PCB design
b2. Idealized PCB design (APM) and simulation template (CBAM)
cross-section view
idealization preparation view
d1. Combined analytical system model
(~1000+ analytical bodies) e1. Combined FEA mesh model (SMM)(~50K elements avg. per complex component)
side view
ECAD layout view
Idealized PCA
Idealized components
Idealized PCB
APM ABB
APM ABB
APM ABBABB SMM
i
i
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Case 1: 1 PBGA 265 on top
Automated PCA design warpage analysis
U3
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Case 2: 2 PBGA 265s on top
U3
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Case 3: 3 PBGA 265s on top
[Ding, 2004] results
InterCAX resultsXaiTools Electronics
(SBIR Phase 1 prototype)
Total Warpage for T=150C: 0.0017 in
Qualitative comparison- Different board & components (somewhat similar)- Good warpage shape results comparison- Similar total warpage results (2.2 mils vs. 1.7 mils = ~23% delta)
Total Warpage for T=150C: = 0.0022 in[scaled from 0.07 mm @ T=183C]
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Case 4: PCA with top & bottom PBGAs Analytical model in IDA-STEP as imported from AP203
Produced by idealizing AP210-based PCB design (from ECAD tool)and combining with idealized chip package models in XaiTools Electronics prototype (XE), and exporting as AP203
One PBGA 441(bottom side)
Two PBGA 265(top side)
Bare PCB
Dense off-pitch body
interactions (challenging for FEA meshers)
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Case 4: PCA with top & bottom PBGAs Mesh model in Abaqus as imported from native Abaqus format
[xx - view needs update]
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Case 4: PCA with top & bottom PBGAs FEA mesh model in Abaqus (cont.)
Mesh in dense chip package solder ball regions
(same region in full wireframe view)
Auto-generated mesh between chip package substrate layers, solder balls, and PCB layers
[xx - view needs update]
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Case 4: PCA with top & bottom PBGAs Solved FEA model in Abaqus
Bare board (PCB) warpage
Preliminary Warpage Results(to be further validated in Phase 2)
Results - Case 4:- Demonstrated FEA meshing feasibility (main challenge)- Good results, trends, and compatibility with similar cases [Ding, 2004; Powell, 2006]- Results reveal anticipated asymmetric effects - High fidelity PCB model considers local feature density differences- Future work will try more effective idealizations (ex. shells) & correlate with physical measurements
PCA top
PCA bottom
Warpage(u3 = out-of-plane deformation)
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Case 5: PBGA Chip Package on Sample PCBDeformation magnitude results: PCA 6230 (w/ PBGA 441)
mminches0.00161
0.00000
0.00050
0.00100
[after Zeng, 2004]
0.00150
vc6230 pbga 441 — delta T = 70 C
Phase 1 Results - Case 5- Excellent comparison of deformation pattern - Very good comparison of max. warpage values (1.61 mils vs. 1.50 mils = ~7% delta)
- Possible deviation causes: different meshing approach, different solver version, etc.
Known Results [Zeng, 2004; Shinko] InterCAX SBIR Phase 1 Results
XCP + Patran pre-processing Abaqus solving and Patran post-processing
XE + Simmetrix pre-processing Abaqus solving and post-processing
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PCA Warpage Capabilities
Main Phase 1 results— Successfully demonstrated feasibility of auto-generating
complex FEA models from AP210-based ECAD designs— Included localized board properties key for warpage prediction— Achieved good correlation with published results (within 7%)— Reduced simulation time by 80% for benchmark case— Automatically simulated design configurations ~5 times larger
than previously practical
Excellent outlook for next steps— Phase 2— Services and tools for industry
NIST SBIR FY05 Program InterCAX Phase 1 Project July, 2005 -January, 2006http://www.InterCAX.com/warpage/
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Contents Warpage Context
— Definition and impact— PCB/A features affecting warpage— Requirements for warpage analysis
Sample simulation results and validation— Bare boards (PCBs)— Assembled boards & chip pkgs. (PCAs, BGAs)
Methodology and tools— Multi-representation architecture— Tool availability
Summary
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Multi-Representation Architecture (MRA) forDesign Analysis Integration
Tree View
Bare PWB
Electrical Mechanical Manufacturability
Warpage PTH Fatigue
Layered ShellEffective Materials Properties
Finite Element
Manufacturing Product Model
AnalysisProduct Model
Context-BasedAnalysis Model
AnalysisBuilding Blocks
SolutionMethod Model
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Multi-Representation Architecture (MRA) forDesign Analysis Integration
Stepping-Stone Model View
Solution Method Model
ABB SMM
Analysis Building Block
Context-Based Analysis Model
SMMABB
APM ABB
CBAM
APM
ECAD Tools and Manufacturable Product Model
(STEP AP210-based)
Solution Tools(ANSYS, ABAQUS …)
Printed Wiring Assembly (PWA)
Solder Joint
Component
PWB
body3body2
body1
body4
T0
Printed Wiring Board (PWB)
SolderJoint
Component
AnalyzableProduct Model
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MRA-based Model Browser
Solution Models and Results – Finite Element Model, etc.
Product-specific Analysis Models
Reusable Analysis Models
Design Libraries
Design Artifacts – PCA, PCB, Components, etc.
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Tool Availability STEP Book AP210 Pro v2.3
— Imports & views Mentor Graphics designs: BoardStation (Expedition under development)
— Enables enrichment & AP210 output
XaiTools PWA-B v2.0— Stackup editor— Bare board warpage analysis
XaiTools Electronics v1.0 (prototype)— Assembled board warpage analysis
Product & Service Information:http://www.InterCAX.com/warpage/
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Collaboration Opportunities
Test cases
Georgia Tech research project
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Contents Warpage Context
— Definition and impact— PCB/A features affecting warpage— Requirements for warpage analysis
Sample simulation results and validation— Bare boards (PCBs)— Assembled boards & chip pkgs. (PCAs, BGAs)
Methodology and tools— Multi-representation architecture— Tool availability
Summary
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Summary
Automated board warpage analysis— Bare board stackup design and warpage analysis— Assembled board warpage analysis
Use of rich product models to drive high-fidelity analyses
— AP210 interface to Mentor Graphics ECAD tools
Commercial tools and services
Collaboration opportunities — Georgia Tech research project— Test cases
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References InterCAX warpage resources
— http://www.InterCAX.com/warpage/ Georgia Tech-NIST project for bare board warpage simulation
— http://eislab.gatech.edu/projects/nist-warpage/ Hai Ding (2004) Prediction and Validation of Thermomechanical
Reliability in Electronic Packaging. Doctoral Dissertation, Georgia Institute of Technology, Atlanta.
Reinhard Powell (2006) Development of FE Prediction Tools and Convective Solder Reflow Projection Moiré Warpage Measurement System. Doctoral Dissertation, Georgia Institute of Technology, Atlanta.
Sai Zeng (2004) Knowledge-based FEA Modeling for Highly Coupled Variable Topology Multi-body Problems. Doctoral Dissertation, Georgia Institute of Technology, Atlanta.
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NIST Disclaimer
This document may identify commercial product names and materials by other parties to describe certain procedures or to provide concrete examples (i.e., to help clarify abstract concepts via specific instances). In no case does product or material identification imply recommendation or endorsement by the authors or their organizations, nor does it imply that such items are necessarily the best available for the purpose. Company, product, or service names may be included that are trademarks or service marks of others.
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