� Abstract — This paper presents an X-band direct digital

synthesis (DDS) based chirp radar transmitter implemented in 0.13��m SiGe BiCMOS technology. The transmitter contains a quadrature DDS, two low-pass filters, an IF IQ modulator, a programmable gain amplifier (PGA), a RF mixer and a pre-amplifier. The DDSs, built with two digital-to-analog converters (DACs), generate two-channel IQ baseband chirp signals from 62MHz to 77MHz. The IQ chirp signals are filtered by two programmable 5th-order Butterworth filters before up-converted to the IF frequency with IQ modulators. The filtered IF signal is further up-converted to the desired radio frequency by an RF mixer. The proposed transmitter thus generates a chirp signal at 8.6GHz, consuming a total power of 333 mW from 2.2V and 1.5V power supplies.

Index Terms— Direct digital synthesis (DDS), Chirp, FMCW, Radar, Transmitter.

I. INTRODUCTION

Chirp radar has been widely used for ranging detection. There are many methods used to generate linear FM or chirp signals with an operating frequency that ranges from microwave to millimeter wave [1]-[6]. The voltage controlled oscillator (VCO)-based FM generator for X-band radar applications has been characterized with a simple architecture [1]-[3]. Fig. 1(a) shows the block diagram of the VCO-based FM radar, which generates the chirp RF signal by modulating the VCO output frequency with an input triangle waveform. However, the VCO output frequency has poor linearity due to the non-linearity of the varactors. Flicker noise and power supply noise will contaminate the close-in band of the carrier signal. The VCO gain is typically not accurate because it varies with process, voltage and temperature. Fig. 1(b) illustrates the diagram of the phase-locked loop (PLL)-based FM generator which utilizes negative feedback to achieve linear frequency output [4]-[5]. A direct digital frequency synthesizer (DDFS) generates the linear FM signal that is used as the reference signal for the PLL. In this architecture, the internal loop delay, low resolution, PLL modulation and limited loop bandwidth problems and the VCO’s limited tuning range provide real challenges in achieving a wideband

linear chirp signal [7]. There is always a trade-off between the PLL bandwidth and the chirp bandwidth, which is inversely proportional to the radar resolution.

Direct digital synthesis (DDS) is featured with fast modulation, fine frequency step, and wide output frequency range especially in generating the baseband chirp signal [8], which is up-converted to the frequency of the interest using a super-heterodyne transmitter architecture. This paper proposes a DDS-based chirp transmitter design for X-band radar applications.

The paper is organized as follows. Section II discusses the architecture of the DDS-based chirp transmitter. The detailed design of the critical building blocks, such as the PGA, image-suppressing RF mixer and the RF pre-amplifier are introduced in section III. The measurement results and chip implementation are presented in Section IV.

II. THE DDS-BASED TRANSMITTER ARCHITECTURE As shown in Fig. 2, the proposed transmitter consists of a

quadrature DDS, two 5th order Butterworth low-pass filters with programmable cut-off frequencies, an IF IQ modulator, an IF buffer, an off-chip SAW filter, a programmable gain amplifier (PGA), an RF mixer containing a notch filter and a pre-amplifier embedded with a band-pass filter. The DDS

Jianjun Yu, Joseph Cali, Feng Zhao, Fa Foster Dai, Xin Jin, Michael Pukish, Yuehai Jin, Zachary Hubbard, J. David Irwin, Richard C. Jaeger, and Andre Aklian*

Department of Electrical and Computer Engineering, Auburn University, Auburn, AL 36849, USA * U. S. Army Research, RDECOM CERDEC Intelligence and Information Warfare Directorate

A Direct Digital Synthesis Based Chirp Radar Transmitter in 0.13 μm SiGe Technology

Buffer

DSP

Off chip

VCO

Power divier

Isolator

Amp

AmpIsolator

LNAMixer

Tx

Rx

DDFS PFD CP LPFVCO

1/N

TxFCW

(a)

(b)

Sig. Gen.

Fig.1. Block diagram of prior work: (a) VCO-based FMCW transceiver

and (b) simplified architecture of PLL-based FMCW transmitter.

41978-1-4799-0129-6/13/$31.00 ©2013 IEEE

IEEE BCTM 3.2

generates two baseband chirp signals in I-Q paths with tunable output amplitudes. The 5th order Butterworth low-pass filter attenuates the harmonics and spurs at the DDS output. The IF IQ modulator up-converts the baseband chirp signals to 1.72GHz IF frequency. The LO leakage and harmonics of the IF mixer are attenuated by the off-chip SAW filter. The PGA amplifies the IF signal with a programmable gain from -16dB to 12dB with a step size of 4dB. The RF mixer then further up-converts the chirp signal to an 8.6 GHz RF signal. The image signal is attenuated by a notch filter in the RF mixer. The harmonics and LO leakage tones are attenuated by the band-pass filter embedded in the pre-amplifier stage. The final output of the transmitter achieves a clean spectrum with the chirp signal modulated around 8.6GHz.

III. CIRCUIT DESIGN

A. Quadrature direct digital synthesis A block diagram of the quadrature DDS architecture is

given in Fig. 3. The quadrature DDS consists of a radar controller, a phase accumulator, a frequency accumulator, a phase modulator, a quadrature CORDIC cell, inverse sinc filters and quadrature DACs. The quadrature DDS operates at a clock frequency of 500MHz. The start frequency, stop frequency and frequency step of the chirp signal are all programmable. Each 12-bit DAC has a tunable gain set by a 4- bit control word. The inverse sinc filter is an option to compensate the gain loss when the output frequency approaches the Nyquist frequency.

B. 5th order Butterworth low-pass filter The quadrature DDS generates harmonics and spurs at its

output, and a low-pass filter is needed to remove them. Generally, two types of architectures are employed to build the integrated continuous filters: active-RC filters and OTA-C filters. Active-RC filters are often used in low frequency applications due to the gain-bandwidth limitations of the operational amplifier. For high frequency applications, the

open-loop operation of an OTA-C filter is preferred. In this application, a widely-tunable OTA-C low-pass filter

with a cutoff frequency tunable from 23MHz to 135MHz is employed as shown in Fig. 4. The architecture of the filter is synthesized with the 5th order low-pass Butterworth ladder prototype. Programmability is achieved by switching unit OTA cells on and off. Because of the relaxed linearity requirement in the transmitter path, a simple folded-cascode amplifier is used in the OTA cell to save power while providing moderate linearity.

C. Programmable gain amplifier Fig. 5 shows the simplified schematic of the 3-bit

programmable gain amplifier (PGA). The current mode amplifier is suitable for high frequency applications. The proposed PGA consists of two gain stages. The voltage gain of the first stage is determined by the ratio of the variable degeneration resistance RE to the small signal impedance of the diode-connected transistors Q3 and Q4. RE is programmed by the MSB of the control word. The second stage is the cascoded differential amplifier with a constant degeneration resistor. The cascode structure will reduce the Miller effect of the differential pair Q5 and Q6, thus improving the frequency response. The voltage gain of the second stage is tuned by the programmable bias current I2, which is controlled by the lower 2 bits of the control word. The total gain of this PGA is given by

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RC RC

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VDD

I2I1

Fig. 5 Simplified schematics of the proposed PGA.

Radar Controller

F STA

RT

F STE

P

P STA

RT

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Frequency Accum. F

Phase Accum.

PT

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AI

AQ

BA

BA

BPM

BD

BPTBF

Phase Modulator

Galois PRNG(65'b)

DACI

DACQ

InverseSincFilter

InverseSincFilter

Fig.3 Block diagram of the quadrature DDS.

+

-

+

-

Fig.4 The fully differential 5th order Butterworth filter.

DAC

SAW

DAC

DIG

DDS LPF

RFLO

I

Q

IFLOI

Q

Off chip

PGABuffer Pre-amp

RF mixer

IQ modulator

Fig.2 Block diagram of the proposed DDS-based chirp radar transmitter.

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This PGA can provide a gain that is programmable from -16dB to 12dB with a step size of 4dB. The bandwidth of this PGA is as large as 3GHz.

D. RF mixer with a notch filter The RF mixer up-converts the 1.72GHz IF signal to an

8.6GHz RF signal with a 6.88GHz RF local oscillator clock. Thus the image frequency is at 5.16GHz. The conventional Gilbert cell is often used in RF mixer design. This structure will cause an image signal and LO leakage at the output spectrum. In order to suppress the image signal, a notch filter was proposed and added to the mixer. As shown in Fig.6, the notch filter is implemented with a series LC tank in parallel to the load resistor RC. The resonant frequency of the LC tank is tuned to the image frequency. A symmetric inductor with a moderate quality factor and large number of turns is used in this design to save area and increase the bandwidth of the notch filter. RC provides the gain for the RF signal of interest.

E. RF pre-amplifier with a band-pass filter The spectrum of the RF mixer output contains the LO signal

tone and the harmonics of the RF signal which are caused by parasitic coupling and non-linearity of the mixer circuit, respectively. A band-pass filter is necessary to attenuate these undesired tones in the spectrum. The differential cascoded common-emitter amplifier loaded with the LC tank is a good choice for implementing the RF filter at this frequency with extra gain. A two-stage differential amplifier is used in this design to achieve a higher gain, as shown in Fig. 7(a) and (b). The filter bandwidth is determined by the quality factor of the LC tank and the parallel resistor RC, which is employed to degenerate the total quality factor for a wide bandwidth. In order to cover the change in both the pass and stop frequencies of the filter due to process variations, the filter bandwidth is further widened by the resonant frequency offset in two LC tanks, while the filter maintains a high roll-off.

IV. CHIP IMPLEMENTATION AND MEASURED RESULTS

The proposed DDS-based chirp radar transmitter prototype chip was implemented in a 0.13�m SiGe BiCMOS technology. Fig. 8 shows the die photo of the proposed transmitter. This chip occupies a total active area of 2.05 mm2, while the RF and IF portions occupy an area of 0.74 mm2. The DDS consumes only 89 mW power from the 1.5V digital voltage supply and 2.2V analog voltage supply. The remaining portions of the transmitter consume a current of 111 mA under a 2.2V power supply. This radar-on-chip transmitter was operated and tested with an extensive custom test fixture including a dedicated printed circuit board (PCB), and a digital control system, consisting of FPGA modules supported by a custom PC interface developed in Python.

Fig. 9 depicts the measured output spectrum of the quadrature DDS with a clock frequency of 500MHz. The generated chirp signal has start- and stop-frequencies of 62MHz and 77MHz, respectively. The amplitude of the DDS output signal was maintained at a constant in the transmitting

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Q1

Q3

Q2

Q4

REi

Ri Ri

Voni

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IbufIamp Ibuf

Ci

2Li

ampI ampII

Ci

Q5 Q6

Vopi

(a)

(b)

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Fig. 7 (a) Block diagram and (b) simplified schematic of the RF pre-amplifier.

Clkp

I

Q1

Q3

Q2

Q4

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VDD

Vip Vin

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Fig. 6 Simplified schematic of the RF mixer with a notch filter.

Fig. 8 Die photo of the implemented chirp radar transmitter.

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frequency band. Although the spur changes with output frequency, the spur level is 60dB below the signal power.

Fig. 10 shows the measured transfer curves of the 5th order Butterworth low-pass filter under all combinations of the 3-bit bandwidth control word. A linearly controlled bandwidth has been obtained from 23MHz to 138MHz with an average step frequency of 16.4MHz. The DC gain is -6dB and the gain rolls off at -100dB/decade above the cutoff frequency, which is adequate to attenuate the harmonics at the DDS output if the start frequency is properly selected.

Fig.11 depicts the measured spectrum of the transmitter output. The transmitted chirp ranges from 8.65GHz to 8.665GHz.

V. CONCLUSIONS This paper presents an X-band DDS-based chirp radar

transmitter implemented in 0.13um SiGe BiCMOS technology. For comparison with an analog PLL-based FMCW transmitter, the direct digital synthesis (DDS)-based radar chirp transmitter is featured with fast modulation, fine frequency step and wide output frequency range, especially in generating the baseband chirp signal which is up-converted to the frequency of interest using the super-heterodyne transmitter architecture. The prototype chirp radar transmitter occupies a die area of 2.05 mm2 and consumes a power of 333 mW.

REFERENCES

[1] C.K.C. Tzuang, et al, “An X-band CMOS multifunction-chip FMCW radar,” IEEE MTT-S Int. Microwave Symp. Dig., pp. 2011-2014, June 2006.

[2] S. Wang, Kun-Hung Tsai, Kuo-Ken Huang, Si-Xian Li, Hsien-Shun, Ching-Kuang, and C. Tzuang "Design of X-band RF CMOS transceiver for FMCW monopulse radar," IEEE Transactions on Microwave Theory and Techniques, Vol. 57, no. 1, pp. 61-70, Jan. 2009.

[3] D. Saunders, et al., "A single-chip 24 GHz SiGe BiCMOS transceiver for FMCW automotive radars," IEEE Radio Frequency Integrated Circuits Symposium, pp. 459-462, June 2009.

[4] E. Suijker, L. D. Boer, G. Visser, R.Dijk, M. Poschmann, and F. V. Vliet, "Integrated X-band FMCW front-end in SiGe BiCMOS," IEEE Proceedings of the 40th European Microwave Conference, pp. 1082-1085, Sept. 2010.

[5] Toshiya Mitomo, et al.,"A 77 GHz 90 nm CMOS transceiver for FMCW radar applications," IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 928-937, April 2010

[6] J. Yu, et al., "A single-chip X-band chirp radar MMIC with stretch processing," IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4, September, 2012.

[7] X. Yu, F. F. Dai, J. D. Irwin, and R. C. Jaeger, “A 9-Bit quadrature direct digital synthesizer implemented in 0.18 um SiGe BiCMOS technology,” IEEE Transactions on Microwave Theory and Technology, vol. 56, no. 5, pp. 1257-1266, May 2008.

[8] X. Geng, F. F. Dai, J. D. Irwin, and R. C. Jaeger, “24-Bit 5.0 GHz direct digital synthesizer RFIC with direct digital modulations in 0.13 μm SiGe BiCMOS technology,” IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 944-954, May 2010.

Fig.9 Measured spectrum of the DDS output.

Fig. 11 Measured spectrum of the chirp radar transmitter RF output.

107 108-60

-50

-40

-30

-20

-10

0

Frequency (Hz)

Mag

nitu

de (d

B)

Fig.10 Measured transfer curves of the 5th order Butter worth low-pass filter.

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