8051 architecture(enhanced)octy09

8/3/2019 8051 Architecture(Enhanced)OctY09

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1Week 4 Vocational Training Council, Hong Kong.

The 8051 ArchitectureThe 8051 Architecture

EEE3410 Microcontroller ApplicationsDepartment of Electrical Engineering

Lecture 4


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EEE3410 Microcontroller Applications

Overview

General physical & operational features

Block diagram

Pin assignments

Logic symbol

Hardware description

Pin description

Read-modify-write port instructions

In this Lecture In this Lecture


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Made by Intel in 1981

An 8-bit, single-chip microcontroller optimized

for control applications

128 bytes RAM, 4096 bytes (4KB) ROM, 2 timers,

1 serial port, 4 I/O ports

40 pins in a dual in-line package (DIP) layout

Overview of the 8051Overview of the 8051


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4KB ROM

128 bytes internal RAM

4 register banks of 8 bytes each (R0-R7)

16 bytes of bit-addressable area80 bytes of general purpose memory

Four 8-bit I/O ports (P0-P3)

Two 16-bit timers (Timer0 & Timer1)

One serial receiver-transmitter interface

Five interrupt sources (2 external & 3 internal)

One oscillator (generates clock signal)

General Physical FeaturesGeneral Physical Features 4 x 8 = 321680

------------

128


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Memory of 8051 can be increased externally:

Increase memory space for codes (programs)

by 64KIncrease memory space for data by 64K

Boolean instructions work with 1 bit at a time

Assume clock frequency = 12MHz, it takes

about 4 Qs (i.e. 4 x 10-6s) to carry out a 8-bit

multiplication instruction

General Operational FeaturesGeneral Operational Features


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The 8051 Block DiagramThe 8051 Block Diagram

Interrupt Control

External Interrupts

CPU

OSC

Timer 1

Timer 0

Serial

Port

I/O PortsBus

Control

Counter

Inputs

P0 P3P1

4K byte

ROM128 byte

RAM

P2(Address/Data)

TXD RXD


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The 8051 Pin AssignmentsThe 8051 Pin Assignments1

2

3

4

5

6

7

8

9

10

11

12

13

14

1516

17

18

19

20

40

39

38

37

36

35

34

33

32

31

30

29

28

27

2625

24

23

22

21

VCC

P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

P0.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA/VPP

ALE/PROG

PSEN

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)P2.4 (A12)

P2.3 (A11)

P2.2 (A10)

P2.1 (A9)

P2.0 (A8)

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

RST

(RXD) P3.0

(TXD) P3.1

(INT0) P3.2

(INT1) P3.3

(T0) P3.4

(T1) P3.5(WR) P3.6

(RD) P3.7

XTAL2

XTAL1

GND

8051


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The 8051 Logic SymbolThe 8051 Logic Symbol

VSS VCC RST

P

O

R

T

0

ADDRESS

AND

DATA BUS

XTAL1

XTAL2

ALE

EA

PSEN

P3.7

P3.6

P3.5P3.4

P3.3P3.2

P3.1

P3.0

RxD

TxDINT0

INT1T0T1WR

RD

SECONDARY

FUNCTIONS

P

O

R

T

3

P

O

R

T

2

ADDRESS

BUS

P0.7P0.6

P0.5P0.4

P0.3

P0.2

P0.1P0.0

P2.7

P2.6P2.5

P2.4

P2.3P2.2

P2.1P2.0

P1.7

P1.6P1.5

P1.4

P1.3P1.2

P1.1P1.0

P

O

R

T

1

Without

alternate

function


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1. Oscillator circuit

2. Program counter (PC)

3. Data pointer (DPTR)

4. Accumulator (

A

) register5. B register

6. Flags

7. Program status word (PSW)

8. Internal memory (ROM

, RAM

, additionalmemory)

9. Stack & stack pointer (SP)

10. Special function register (SFR)

Hardware DescriptionHardware Description


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The heart of the 8051Produces clock pulses

Synchronize all 8051s internal operations

Oscillator CircuitOscillator CircuitA single machine cycle

consists of 12 crystal pulses !


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Machine CycleMachine Cycle

Machine cycle is the basic repetitive process that the CPU

performs once it is powered on. A machine cycle consists of a

fixed number of clock cycles (pulses). It is different for

different kinds of CPU.

The 8051 family needs 12 clock cycles for a machine cycle.

The CPU takes one or more machine cycles to complete an

instruction. More complex instructions require more number

of machine cycles to complete the instruction. The number of

machine cycles of the 8051 instructions are ranging from 1 to

4.


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Example 4Example 4--11Find the elapse time of the machine cycle for:

(a) XTAL = 11.0592 MHz

(b) XTAL = 16 MHz

(c) XTAL = 20 MHz

Solution:

(a) 11.0592 MHz / 12 = 921.6 kHz

Machine cycle = 1 / 921.6 kHz = 1.085 Qs

(b) 16 MHz / 12 = 1.333 MHzMachine cycle = 1 / 1.333 MHz = 0.75 Qs

(c) 20 MHz / 12 = 1.667 MHz

Machine cycle = 1 / 1.667 MHz = 0.60 Qs


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PC is a 16-bit registerPC is the only register that does not have aninternal address

Holds the address of the memory location to fetch

the program instructionProgram ROM may be on the chip at addresses0000H to 0FFFH (4Kbytes), external to the chip foraddresses that exceed 0FFFH

Program ROM

may be totally external for alladdresses from 0000H to FFFFH

PC is automatically incremented (+1) after everyinstruction byte is fetched

Program Counter (PC)Program Counter (PC)

Either

One !


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Accumulator (A Register)Accumulator (A Register)

Most versatile CPU register and is used for many

operations, including addition, integer

multiplication and division, and Boolean bit

manipulations

A register is also used for all data transferbetween the 8051 and any external memory


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B register is used with theA register formultiplication and division operations

(eg. MUL AB DIV AB)No other special function other than as alocation where data may be stored

B RegisterB Register


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Flags are 1-bit registers provided to store the resultsof certain program instructions

Other instructions can test the condition of the flags

and make decisions based on the flag states

Flags are grouped inside theprogram status word(PSW) and thepower control (PCON) registers forconvenient addressing

Math flags: respond automatically to the outcomes of

math operations (CY, AC,OV,P)User flags: general-purpose flags that may be used by

the programmer to record some event in the program

(F0, GF0, GF1)

FlagsFlags


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PSWcontains the math flags, user program flag

F0, and the register select bits (RS1, RS0) that

identify which of the four general-purpose

register banks is currently in use by the program

7 6 5 4 3 2 1 0

CY AC F0 RS1 RS0 OV -- P

Program Status Word (PSW)Program Status Word (PSW)


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Program Status Word (PSW)Program Status Word (PSW)

Bit Symbol Function7 CY Carry Flag; used in arithmetic, JUMP, ROTATE,

and BOOLEAN instruction

6 AC Auxiliary carry flag; used for BCD arithmetic

5 F0 User flag 0

4 RS1 Register bank select bit 1

3 RS0 Register bank select bit 0

2 OV Overflow flag; used in arithmetic instructions1 -- Reserved for future use

0 P Parity flag; shows parity of register A: 1 = Odd

Parity


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The 8051 maintains even parity with theaccumulator A, ie; the number of ones in the

accumulator together with the parity bit (in

the program status word, PSW) is always even.


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Instruction that Affect Flag BitsInstruction that Affect Flag BitsInstruction CY OV AC Instruction CY OV AC

ADD X X X SETB C 1

ADDC X X X CLR C 0

SUBB X X X CPL C X

MUL 0 X ANL C, bit X

DIV 0 X ANL C, /bit X

DA X ORL C, bit X

RRC X ORL C, /bit X

RLC X CJNE X

MOV C, bit X Note: X can be 0 or 1


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A functioning computer must have memory forprogram code bytes, commonly in ROM, and RAM

memory for variable data that can be altered as

the program runs

8051 has internal RAM (128 bytes) and ROM

(4Kbytes)

8051 uses the same address but in different

memories for code and data

Internal circuitry access the correct memory based

on the nature of the operation in progress

Can add memory externally if needed

Internal MemoryInternal Memory


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EEE3410 Microcontroller Applications8051 Internal RAM8051 Internal RAMOrganisationOrganisation

R7

R6R5

R4

R3

R2

R1

R0R7

R6

R5

R4

R3R2

R1

R0R7

R6

R5

R4

R3

R2

R1

R0R7

R6

R5

R4

R3

R2

R1

R0

07

06

05

04

03

02

01

00

0F

0E

0D

0C

0B

0A

09

08

17

16

15

14

1312

11

10

1F

1E1D

1C

1B

1A

19

18

Bank

0

Bank1

Bank2

Bank3

27

26

25

24

23

22

21

20

2F

2E

2D

2C

2B

2A

29

28

7F 78

77 70

6F 68

67 60

5F 58

57 50

4F 48

47 403F 38

37 30

2F 28

27 20

1F 18

17 10

0F 08

07 00 30

7F

Working Registers Bit Addressable Gener al Purpose

128 bytes internal RAM

4 register banks of 8 bytes each (R0-

16 bytes of bit-addressable area

80 bytes of general purpose memory


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Example 2Example 2--55State the contents of RAM locations after the following program:

MOV R0, #99H

MOV R1, #85H

MOV R2, #3FH

MOV R7, #63H

MOV R5, #12H

After the execution of the above program we have the following:

RAM location 0 has value 99H RAM location 1 has value 85H

RAM location 2 has value 3FH RAM location 7 has value 63H

RAM location 5 has value 12H

Assume register bank 0

was selected !


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Program Status Word (PSW)Program Status Word (PSW)Ba

nk SelectB

its,R

S1, &R

S0 to select 1 of 4 register ba

nkBa

nk SelectB

its,R

S1, &R

S0 to select 1 of 4 register ba

nk


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Example 2Example 2--66

Repeat Example 2-5 using RAM addresses instead of register

names.

This is called direct addressing mode and uses the RAMaddress location for the destination address.

MOV 00, #99H

MOV 01, #85H

M

OV 02, #3FH

MOV 07, #63H

MOV 05, #12H


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Example 2Example 2--77State the contents of RAM locations after the following program:

SETB PSW.4

MOV R0, #99H

MOV R1, #85H

MOV R2, #3FH

MOV R7, #63HMOV R5, #12H

By default, PSW.3=0 and PSW.4=0; therefore, the instruction SETB

PSW.4 sets RS1=1 and RS0=0, thereby selecting register bank 2.

Register bank 2 uses RAM locations 10H 17H. After the execution of

the above program we have the following

RAM location 10 has value 99H RAM location 11 has value 85H

RAM location 12 has value 3FH RAM location 17 has value 63H

RAM location 15 has value 12H

7 6 5 4 3 2 1 0

CY AC F0 RS1 RS0 OV -- PPSW


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SP is a 8-bit register used to hold an internal RAMaddress that is called the top of the stack

Stack refers to an area of internal RAM that is used inconjunction with certain opcodes to store and retrievedata quickly

SPholds the internal RAM address where the last byteof data was stored by a stack operation

When data is to be placed on the stack, the SPincrements before storing data on the stack so that thestack grows up as data is stored

As data is retrieved from the stack, the byte is readfrom the stack, and then the SPdecrements to point tothe next available byte of stored data

SP= 07H after reset

Stack and Stack Pointer (SP)Stack and Stack Pointer (SP)


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Stack OperationStack Operation

SP = 0A Address 0A SP = 0AStore Data Get Data

SP = 09 Address 09 SP = 09Store Data Get Data

SP = 08 Address 08 SP = 08Store Data Get Data

SP = 07 Address 07 SP = 07

Storing Data on the Stack(Increment then store)

Internal RAM(Get then decrement)

Getting DataFrom the Stack


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Example 2Example 2--88Show the stack and stack pointer for the following. Assume thedefault stack area.

MOV R6, #25H

MOV R1, #12H

MOV R4, #0F3H

PUSH 6

PUSH 1

PUSH 4

0B

0A

09

08

0B

0A

09

08

0B

0A

09

08

0B

0A

09

08

SP = 07

25

After PUSH 6

SP = 08

12

25

SP = 09

After PUSH 1

F3

12

25

SP = 0A

After PUSH 4


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Example 2Example 2--99Examine the stack, show the contents of the registers and SPafter

execution of the following instruction. All values are in hex.

POP 3 ;POP stack into R3



0B

0A

09

08

0B

0A

09

08

0B

0A

09

08

540B

0A

09

08

54

F9

76

6C

54

F9

76

6C

F9

76

6C

SP = 0A SP = 09 SP = 08

After POP 3 After POP 5 After POP 2

Sta

rt SP = 0B

54

F9

76

6C

05

04

03

02

??

??

54

??

05

04

03

02

05

04

03

02

05

04

03

02

F9

??

54

??

F9

??

54

76

??

??

??

??


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Example 2Example 2--1010Show the stack and stack pointer for the following.

MOV SP, #5FH

MOV R2, #25H

MOV R1, #12H

MOV R4, #0F3H

PUSH 2PUSH 1

PUSH 4

63

62

61

60

63

62

61

60

63

62

61

60

63

62

61

602512

25

F3

12

25

Start SP = 5F SP = 60 SP = 61 SP = 62

After PUSH 2 After PUSH 1 After PUSH 4


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8051 has 21 SFRs which occupy the addresses

from 80H to FFH (128bytes)

Not all of the addresses from 80H to FFH areused for SFRs

Attempt to use the empty addresses may

get unpredictable result

Special Function Registers (SFR)Special Function Registers (SFR)


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Special Function Register MapSpecial Function Register MapBit addressable


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Va

lue of SFR

a

tR

esetVa

lue of SFR

a

tR

eset


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Internal ROMInternal ROM

Internal ROM occupies the code address space

from 0000H to 0FFFH (Size = 4K byte)

Program addresses higher than 0FFFH will

automatically fetch code bytes from external

program memory

Code bytes can also be fetched exclusively from

an external memory by connecting the externalaccess pin (EA) to ground


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VCC (pin 40 - provides supply voltage of +5V)

GND (pin 20)

XTAL1 & XTAL2 (pins 19 & 18 - to crystal and

then caps)RST (pin 9- reset)

EA (pin 31 - external access)

PSEN (pin 29 - program store enable)

ALE (pin 30 - address latch enable)

Ports 0-3

Some Important PinsSome Important Pins


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I/O Ports (P0I/O Ports (P0 -- P3)P3)

One of the most useful features of the 8051 is

that it consists of 4 I/O ports (P0 - P3)

All ports are bidirectional (they can take input and

to provide output)All ports have multiple functions (except P1)

All ports are bit addressable

On RESET all the ports are configured as output

When a bit latch is to be used as an input, a 1must be written to the corresponding latch by theprogram to configure it as input (eg. MOV P1, #0FFH)


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Occupies a total of 8 pins (Pins 32-39)

Can be used for :

Input only

Output onlyInput and output at the same time (i.e. some

pins for input and the others for output)

Can be used to handle both address and data

Need pull-up resistors

Port 0Port 0


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Port 0 as an Output PortPort 0 as an Output Port

The following code will continuously send out to

port 0 the alternating values 55H and AAH

MOV A, #55H

BACK: MOV P0, A

ACALL DELAY

CPL A

SJMP BACK

AAH = 10101010255H = 010101012


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Port 0 as an Input PortPort 0 as an Input Port

In the following code, port 0 is configured first

as an input port by writing 1s to it, and then

data is received from that port and sent to P1

MOV A, #0FFH

MOV P0, A

BACK: MOV A, P0

MOV P1, ASJMP BACK

FFH = 111111112


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Dual Role of Port 0Dual Role of Port 0When connecting an 8051 to an externalmemory, port 0 provides both address anddata (AD0 AD7)

When ALE = 0, it provides data D0 D7

When ALE = 1, it provides data A0

A7

ALE is used for demultiplexing address anddata with the help of

a 74LS373 latch


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Can be used as input or output

Does not need any pull-up resistors

Upon reset, port 1 is configured as an

output port

No alternative functions

Port 1Port 1


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MOV A, #55H

BACK: MOV P1, A

ACALL DELAY

CPL A

SJMP BACK


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In the following code, port 1 is configured first as aninput port by writing 1s to it, and then data is

received from that port and saved in R7, R6, and R5

MOV A, #0FFH

MOV P1, AMOV A, P1

MOV R7, A

ACALL DELAY

MOV A, P1

MOV R6, AACALL DELAY

MOV A, P1

MOV R5, A


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Similar function as Port 1


Does not need any pull-up resistors

Upon reset, port 2 is configured as an output

port

Port 2Port 2


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MOV A, #55H

BACK: MOV P2, A

ACALL DELAY

CPL A

SJMP BACK


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In the following code, port 2 is configured first

as an input port by writing 1s to it, and then

data is received from that port and sent to P1

MOV A, #0FFH

MOV P2, A

BACK: MOV A, P2

MOV P1, ASJMP BACK


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Dual Role of Port 2Dual Role of Port 2

When connecting an 8051 to an externalmemory, port 2 provides both address (A8 A15)

It is used along with P0 to provide the 16-bit

addressWhen P2 is used for the upper 8 bits of the 16-

bit address, it cannot be used for I/O


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Similar function as Port 1 and Port 2


Does not need any pull-up resistorsUpon reset, port 3 is configured as an output port

Pins can be individually programmable for other uses

Most commonly be used to provide some important signals

(e.g. interrupts)

Port 3Port 3


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Port 3 Alternate FunctionsPort 3 Alternate Functions

P3 Bit Function PinP3.0 RxD 10

P3.1 TxD 11

P3.2 INT0 12

P3.3 INT1 13

P3.4 T0 14

P3.5 T1 15

P3.6 WR 16

P3.7 RD 17


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ReadRead--ModifyModify--Write FeatureWrite Feature

A method used to access the 8051 portsCombining all 3 actions in a single instructions :

Read the data at the port

Modify (do operation on) the data at the port

Write the results to the port

MOV P1, #55H

AGAIN: XRL P1, #0FFH

ACALL DELAYSJMP AGAIN

Example:

ANL P1, A

ORL P2, A

XRL P3, A

JBC P1.1, LABEL

CPL P3.0INC P2

DEC P2

DJNZ P3, LABEL


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SingleSingle--bit Addressability of Portsbit Addressability of Ports

One of the most powerful features of the

8051

Access only one or several bits of the port

instead of the entire 8 bits

BACK: CPL P1.2

ACALL DELAYSJMP BACK

;bit 2 of port 1


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Example 4Example 4--22

Write a program to perform the following:

(a) Keep monitoring the P1.2 bit until it becomes high;

(b) When P1.2 becomes high, write value 45H to port 0; and

(c) Send a high-to-low (H

-to-L) pulse to P2.3SETB P1.2 ; config pin P1.2 as input

MOV A, #45H

AGAIN:

JNB P1.2, AGAIN ; wait until P1.2=1

; now P1.2 = 1

MOV P0, A

SETB P2.3

CLR P2.3


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General physical & operational features

8051 hardware description

8051 pin description

Read-modify-write port instructions

SummarySummary


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1. In the 8051, the program counter is _________ bits wide.

2. True or false. Every member of the 8051 family, regardless

of the maker, wakes up at memory 0000H when it is

powered up.

3. At what ROM

location do we store the first opcode of an8051 program?

4. The instruction MOV A, #44H is a ______-byte instruction.

5. What is the ROM address space for the 8052 chip?

6. The flag register in the 8051 is called __________.

7. What is the size of the flag register in the 8051?

8. Which bits of the PSW register are user-definable?

Review QuestionsReview Questions


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9. Find the CY and AC flag bits for the following code.MOV A, #0FFH

ADD A, #01

10. Find the CY and AC flag bits for the following code.

MOV A, #0C2HADD A, #3DH

11. What is the size of the SP register?

12. With each PUSH instruction, the stack pointer register (SP) is

_______ (incremented/decremented) by 1.

13. With each POP instruction, the SP _____(incremented/decremented) by 1.

14. ON power up, the 8051 uses RAM location _____ as the first

location of the stack.



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15. On power up, the 8051 uses bank ____ for registers R0R7.

16. On power up, the 8051 uses RAM locations _____ to _____

for register R0R7 (register bank 0).

17. Which register bank is used if we alter RS0 and RS1 of the

PSW by the following two instruction?

SETB PSW.3

SETB PSW.4

18. In Question 17, what RAM locations are used for register

R0R7?



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9i i i i


The 8051 Microcontroller and Embedded Systems -

Using Assembly and C, Mazidi

Chapter 8 P.217 P.227

The 8051 Microcontroller

Hardware, Software andInterfacing, James W. Stewart

Chapter 1 P.1 P.16

Chapter 2 P.19 P.35

Read referenceRead reference

8051 architecture(enhanced)octy09

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