4 8051 architecture

7/24/2019 4 8051 Architecture

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Microcontroller Intel 8051

[Architecture]


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The Microcontroller

Microcontrollers can be considered as self-contained systems with arocessor! memory and I"# orts$

% In most cases! all that is missin& is the software to define the

oeration of the embedded system$

'sually a(ailable in se(eral forms)

% *e(ices for rototyin&

+uilt-in or i&&y-bac, ./#M for storin& the software$

% #ne Time .ro&rammable #T. de(ices$

2o window on the ac,a&e$ Therefore! the internal ./#Mcannot be erased after bein& ro&rammed$

% 3i&h 4olume .roduction de(ices$

'se /#M internally to hold the software$ heaer in lar&e

(olume$


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The Architectural 2eeds of a

Microcontroller

6ets consider what architectural features would beneeded in a microcontroller$

7hat are the eected alications9

% :ensin& the en(ironment Inut% .roducin& a resonse #utut

% The resonse may be delayed Timer"ounter

% .rioriti;ed resonse Interruts

% :oftware to control the rocess 2on-(olatile Memory% Temorary data /AM


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Ma


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amle Microcontroller =amilies

@80 from @ilo&

% 8-bit microrocessor based on the 8080 architecture$

% aable of 1 MI. at M3;$

%Accumulator! B 8-bit re&isters! C inde re&isters$% 'ses eternal /AM for temorary data$

% +uilt-in refresh circuitry for the eternal /AM$

% #nly ort-based I"#$

% :lowly disaearin&$


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amle Microcontroller =amilies Dont$

MB811 from Motorola

% 8-bit stac,-based architecture$

% C accumulators and C inde re&isters$

% +uilt in ./#M and /AM$

% *i&ital I"#$

% Timers$

% A*$

% /:CEC communication$

% Wasthe most owerful and fleible controller a(ailable atintroduction$

Around 1FG0$

% Still(ery oular$


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The M:-51 =amily of Microcontrollers

#ri&inally introduced by Intel in 1F81$% Currently! the most widely used microcontroller$

% 8-bit rocessor$

% C distinct searately addressable memory areas$

Maimum of BH on-chi /#M$

% 'sually 0 to H$ Maimum of BH eternal data memory$

Maimum of BH eternal code memory$

+asic (ersion 8051 contains)

% H +ytes of on-chi /#M instruction memory$

% 1C8 +ytes of on-chi /AM for temorary data stora&e and the

stac,$

% C timers! one serial ort! and four 8-bit arallel I"# orts$

% :eeds startin& from1C M3;$


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=eatures of the 8051 Microcontroller

The 80E1 reuires eternal instruction memory$% It can be as lar&e as BH +ytes$% Jou lose C orts for interfacin& to the eternal memory$

Jou can relace these by interfacin& the chi to an I"# ortcontroller li,e the 8C55$

The 8051 is the ori&inal member of the Intel M:-51 family ofMicrocontrollers$% There are se(eral (arieties that differ sli&htly in the a(ailable

features$


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Manufacturers of M:-51 lones

There is a lar&e number of comanies that

manufacture microcontrollers in the 8051

family$

%ATM6 ororation$

=lash instead of ./#M$

6ow 4olta&e$

Minimal (ersion with less memory and fewer I"#orts in a smaller ac,a&e$

M#: imlementation$

:eeds that ran&e from 1C to C0 M3;$


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Manufacturers of M:-51 lones

% *allas :emiconductor

'ses 24-/AM$ .ro&rammable in-system$

As lar&e as ECH of instruction memory$

:ome (ersions ha(e an on-chi real-time cloc,$

% .hilis ororation$

6ar&e selection of 8051 based microcontrollers$

Include features li,e A"* and *"A on chi$

% Kilin and Altera

8051 =.LA cores$


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The 8051 Microcontroller Internals


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8051 Architecture

.ro&rammers 4iew% Memory #r&ani;ation

% /e&ister :et

% Instruction :et

3ardware *esi&ners 4iew

% .in-out

% Timin& characteristics

% urrent " 4olta&e reuirements


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Memory #r&ani;ation

The 8051 has searate address saces for

ro&ram stora&e and data stora&e$

%*eendin& on the tye of instruction! thesame address can refer to two lo&ically and

hysically different memory locations$


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.ro&ram :tora&e

After reset! the M:-51 starts fetchin& instructions from00003$

% This can be either on-chi or eternal deendin& on

the (alue of the A inut in$

If ANis low! then the ro&ram memory is eternal$ If ANis hi&h! then addresses from 0000 to 0===

will refer to on-chi memory and addresses 1000

u to ==== refer to eternal memory$

% 2ote that the 80E1 must ha(e its A connected low as

all of its memory is eternal$

6in,) A connection


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Access to ternal Memory

.ort 0 acts as a multileed address"data bus$ :endin&

the low byte of the ro&ram counter .6 as an

address$

.ort C sends the ro&ram counter hi&h byte .3

directly to the eternal memory$

The si&nal A6 oerates as in the 8051 to allow an

eternal latch to store the .6 byte while the multileed

bus is made ready to recei(e the code byte from the

eternal memory$

.ort 0 then switches function and becomes the data bus

recei(in& the byte from memory$

6in,) 3"w Interfacin&


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*ata :tora&e

The 8051 has C5B bytes of /AM on-chi$

% The lower 1C8 bytes are intended for internal data

stora&e$

% The uer 1C8 bytes are the :ecial =unction/e&isters :=/$

The lower 1C8 bytes are not to be used as standard

/AM$% Internally 8051s re&isters default to stac, area! and

other features$ [00-G=3]

6in,) Memory #r&ani;ation


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*ata :tora&e [ont$$$]

The lowest EC bytes of the on-chi /AM form ban,s of 8

re&isters each$

#nly one of these ban,s can be acti(e at any time$

+an, is chosen by settin& C bits in .:7% *efault ban, at ower u is ban, 0 locations 00 % 0G$

The 8 re&isters in any acti(e ban, are referred to as /0

throu&h /G

Li(en that each re&ister has a secific address! it can be

accessed directly usin& that address e(en if its ban, is not

the acti(e one$


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*ata :tora&e [ont$$$]

The net 1B bytes % locations C03 to C=3 % form a bloc,

that can be addressed as either bytes or indi(idual bits$

% The bytes ha(e addresses C03 to C=3$

% The bits ha(e addresses 003 to G=3$% :ecific instructions are used for accessin&

the bits$

6ocations E03 to G=3 are &eneral urose /AM$

6in,) Memory #r&ani;ation


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The :=/ :ecial =unction /e&ister

The uer 1C8 bytes of the on-chi /AM are used to house secial

function re&isters$

In reality! only about C5 of these bytes are actually used$ The

others are reser(ed for future (ersions of the 8051$

% These are re&isters associated with imortant functions in the

oeration of the M:-51$

% :ome of these re&isters are bit-addressableas well as byte-addressable$

The address of bit 0 of the re&ister will be the same as the

address of the re&ister$


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The lements of :=/

A and + re&isters % 8 bit each

*.T/ ) [*.3)*.6] % 1B bit combined

. .ro&ram ounter % 1B bits

:. :tac, .ointer % 8 bit

.:7 .ro&ram :tatus 7ord

.ort 6atches

:erial *ata +uffer

Timer /e&isters

ontrol /e&isters

6in,) :=/ lements


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The A % Accumulator

ommonly used for mo(e and arithmetic instructions$

an be referred to in se(eral ways)

% Imlicitly in o-codes$

% /eferred to as A or A for instructions that allow secifyin& a

re&ister$% +y its :=/ address 003$

#erates in a similar manner to the 8085 accumulator$

+it addressable$

% A$C means bit C of the A re&ister$


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The + /e&ister

ommonly used as a temorary re&ister! much li,e a Fth/ re&ister$

'sed by two o-codes

% M'6 A+! di( A+

+ re&ister holds the second oerand and will hold art ofthe result

% 'er 8 bits of the multilication result

% /emainder in case of di(ision$

an also be accessed throu&h its :=/ address of 0=03$

+it addressable$


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The *.6 and *.3 /e&isters

C 8-bit re&isters that can be combined into a 1B-bit *.T/ % *ata

.ointer$

'sed by commands that access eternal memory

Also used for storin& 1Bbit (alues

mo( *.T/! Odata1B

P setu *.T/ with 1Bbit et address

mo( A! Q*.T/

P coy mem[*.T/] to A

an be accessed as C searate 8-bit re&isters if needed$

*.T/ is useful for strin& oerations and 6oo,-'-Table 6'T

oerations$


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The :. /e&ister

:. is the stac, ointer$ :. oints to the last used location of the stac,$

% .ush oeration will first increment :. and then coy data$

% .o oeration will first coy data and then decrement :.$

In 8051! stac, &rows uwards from low memory to hi&h memory

and can be in the internal /AM only$

#n ower-u! :. oints to 0G3$

% /e&ister ban,s C!E! 083 to 1=3 form the default stac, area$

:tac, can be relocated by settin& :. to the uer memory area inE03 to G=3$

% mo( :.! OEC3


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The .:7 /e&ister

.ro&ram :tatus 7ord is a >bit addressable? 8-bit re&isterthat has all the fla&s$

M:+ 6:+

J A =0 /:1 /:C #4 - .

Symbol Position Function

J .:7$G arry =la&

A .:7$B Auiliary arry =la&$ =or +*#erations

=0 .:7$5 =la& 0$ A(ailable to the user for &eneraluroses$

/:1 .:7$ /e&ister ban, select bits$ :et bysoftware to determine which re&isterban, is bein& used$

/:C .:7$E

#4 .:7$C #(erflow =la&

- .:7$1 2ot used

. .:7$0 .arity =la&$ (en .arity$


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The .0! .1! .C! and .E /e&isters

.ort 6atches$

:ecify the (alue to be outut on the secific outut ort

or the (alue read from the secific inut ort$

+it addressable$

% =irst bit has the same address as the re&ister$

% amle) .1 has address F03 in the :=/! so

.1$G or address FG3 refer to the same bit$

6in,) :=/ address


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The :+'= /e&ister

:erial .ort *ata +uffer$

C re&isters at the same location

% #ne is read-only used for readin& serial inut

data$

:erial *ata /ecei(e +uffer$

% The other is write-only used for storin& serial

outut data$ :erial *ata Transmit +uffer$

6in,) :=/ address


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Timer /e&isters % T30 and T60

The hi&h and low bytes of the 1B-bit countin& re&ister for

timer"counter T0$

There is also a T31 " T61 air for the T1 timer$

In the 805C! one more air eists T3C " T6C for the TC

timer$

/A.C3 and /A.C6 eist only in the 805C and they

are coies of the T3C and T6C re&isters$

6in,) :=/ address


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ontrol /e&isters

I. % Interrut .riority$

I % Interrut nable$

TM#* % Timer Mode$

T#2 % Timer ontrol$

TC#2 % Timer C ontrol 805C

:#2 % :erial .ort ontrol$

.#2 % .ower ontrol 8051$

4 8051 architecture

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