architecture and programming of 8051 mc1_2

7/26/2019 Architecture and Programming of 8051 MC1_2

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Architecture and programming of 8051 MCU's TOC

Chapter 1

Chapter 2

Chapter 3

Chapter 4 Chapter 5

Chapter 6

Chapter 7

Chapter 2 : 8051 Microcontroller Architecture

2.1 What is 8051 Standard?

2.2 8051 Microcontroller's pins

2.3 Input/Output Ports I/O Ports!

2." 8051 Microcontroller Me#or$ Or%anisation

2.5 S&s Special &unction e%isters!

2.( )ounters and *i#ers

2.+ ,-* ,niersal -s$nchronous eceier and *rans#itter!

2.8 8051 Microcontroller Interrupts

2. 8051 Microcontroller Poer )onsu#ption )ontrol

2.1 What is 8051 tandard!

Microcontroller #anuacturers hae een co#petin% or a lon% ti#e or attractin% choos$ custo#ers and

eer$ couple o da$s a ne chip ith a hi%her operatin% reuenc$4 #ore #e#or$ and up%raded -/

conerters appeared on the #ar6et.

7oeer4 #ost o the# had the sa#e or at least er$ si#ilar architecture 6non in the orld o

#icrocontrollers as 8051 co#patile9. What is all this aout?

*he hole stor$ has its e%innin%s in the ar 80s hen Intel launched the irst series o #icrocontrollers

called the M)S 051. :en thou%h these #icrocontrollers had uite #odest eatures in co#parison to the

ne ones4 the$ conuered the orld er$ soon and eca#e a standard or hat noada$s is called the

#icrocontroller.

*he #ain reason or their %reat success and popularit$ is a s6illull$ chosen coni%uration hich satisies

dierent needs o a lar%e nu#er o users alloin% at the sa#e ti#e constant e;pansions reers to the

ne t$pes o #icrocontrollers!.


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ersions o the 8051 a#il$. What #a6es this #icrocontroller so special and uniersal so that al#ost all

#anuacturers all oer the orld #anuacture it toda$ under dierent na#e?

-s seen in i%ure aoe4 the 8051 #icrocontroller has nothin% i#pressie in appearance>

" o OM is not #uch at all.

128 o -M includin% S&s! satisies the user's asic needs.

" ports hain% in total o 32 input/output lines are in #ost cases suicient to #a6e all

necessar$ connections to peripheral eniron#ent.

*he hole coni%uration is oiousl$ thou%ht o as to satis$ the needs o #ost pro%ra##ers or6in% on

deelop#ent o auto#ation deices. One o its adanta%es is that nothin% is #issin% and nothin% is too

#uch. In other ords4 it is created e;actl$ in accordance to the aera%e user@s taste and needs. -nother

adanta%es are -M or%aniAation4 the operation o )entral Processor ,nit )P,! and ports hich

co#pletel$ use all recourses and enale urther up%rade.

2.2 "inout #escription

"ins 1$8:Port 1 :ach o these pins can e coni%ured as an input or an output.

"in %> S - lo%ic one on this pin disales the #icrocontroller and clears the contents o #ost re%isters. In

other ords4 the positie olta%e on this pin resets the #icrocontroller.


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"in 11:*B Serial as$nchronous co##unication output or Serial s$nchronous co##unication cloc6

output.

"in 12:IC*0 Interrupt 0 input.

"in 1:IC*1 Interrupt 1 input.

"in 1(:*0 )ounter 0 cloc6 input.

"in 15:*1 )ounter 1 cloc6 input.

"in 1):W Write to e;ternal additional! -M.

"in 1&: ead ro# e;ternal -M.

"in 18* 1%:B24 B1 Internal oscillator input and output. - uartA cr$stal hich speciies operatin%

reuenc$ is usuall$ connected to these pins. Instead o it4 #iniature cera#ics resonators can also e

used or reuenc$ stailit$. Dater ersions o #icrocontrollers operate at a reuenc$ o 0 7A up to oer

50 7A.

"in 20:EC Eround."in 21$28:Port 2 I there is no intention to use e;ternal #e#or$ then these port pins are coni%ured as

%eneral inputs/outputs. In case e;ternal #e#or$ is used4 the hi%her address $te4 i.e. addresses -8F-15

ill appear on this port. :en thou%h #e#or$ ith capacit$ o (" is not used4 hich #eans that not all

ei%ht port its are used or its addressin%4 the rest o the# are not aailale as inputs/outputs.

"in 2%:PS:C I e;ternal OM is used or storin% pro%ra# then a lo%ic Aero 0! appears on it eer$ ti#e

the #icrocontroller reads a $te ro# #e#or$.

"in 0:-D: Prior to readin% ro# e;ternal #e#or$4 the #icrocontroller puts the loer address $te -0F

-+! on P0 and actiates the -D: output. -ter receiin% si%nal ro# the -D: pin4 the e;ternal re%ister

usuall$ +"7)*3+3 or +"7)*3+5 addFon chip! #e#oriAes the state o P0 and uses it as a #e#or$ chip

address. I##ediatel$ ater that4 the -D, pin is returned its preious lo%ic state and P0 is no used as a

ata


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-ll 8051 #icrocontrollers hae " I/O ports each co#prisin% 8 its hich can e coni%ured as inputs or

outputs. -ccordin%l$4 in total o 32 input/output pins enalin% the #icrocontroller to e connected to

peripheral deices are aailale or use.

Pin coni%uration4 i.e. hether it is to e coni%ured as an input 1! or an output 0!4 depends on its lo%ic

state. In order to coni%ure a #icrocontroller pin as an output4 it is necessar$ to appl$ a lo%ic Aero 0! to

appropriate I/O port it. In this case4 olta%e leel on appropriate pin ill e 0.

Si#ilarl$4 in order to coni%ure a #icrocontroller pin as an input4 it is necessar$ to appl$ a lo%ic one 1! to

appropriate port. In this case4 olta%e leel on appropriate pin ill e 5G as is the case ith an$ **D

input!. *his #a$ see# conusin% ut don't loose $our patience. It all eco#es clear ater stud$in% si#ple

electronic circuits connected to an I/O pin.


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+nput,-utput +,-/ pin

&i%ure aoe illustrates a si#pliied sche#atic o all circuits ithin the #icrocontroler connected to one o

its pins. It reers to all the pins e;cept those o the P0 port hich do not hae pullFup resistors uiltFin.

-utput pin

- lo%ic Aero 0! is applied to a it o the P re%ister. *he output &: transistor is turned on4 thus connectin%

the appropriate pin to %round.

+nput pin

- lo%ic one 1! is applied to a it o the P re%ister. *he output &: transistor is turned o and the

appropriate pin re#ains connected to the poer suppl$ olta%e oer a pullFup resistor o hi%h resistance.

Do%ic state olta%e! o an$ pin can e chan%ed or read at an$ #o#ent. - lo%ic Aero 0! and lo%ic one 1!

are not eual. - lo%ic one 0! represents a short circuit to %round. Such a pin acts as an output.

- lo%ic one 1! is loosel$9 connected to the poer suppl$ olta%e oer a resistor o hi%h resistance. Since

this olta%e can e easil$ reduced9 $ an e;ternal si%nal4 such a pin acts as an input.

"ort 0


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*he P0 port is characteriAed $ to unctions. I e;ternal #e#or$ is used then the loer address $te

addresses -0F-+! is applied on it. Otherise4 all its o this port are coni%ured as inputs/outputs.

*he other unction is e;pressed hen it is coni%ured as an output. ,nli6e other ports consistin% o pins

ith uiltFin pullFup resistor connected $ its end to 5 G poer suppl$4 pins o this port hae this resistor

let out. *his apparentl$ s#all dierence has its conseuences>

I an$ pin o this port is coni%ured as an input then it acts as i it loats9. Such an input has unli#ited input

resistance and indeter#ined potential.

When the pin is coni%ured as an output4 it acts as an open drain9.


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P1 is a true I/O port4 ecause it doesn't hae an$ alternatie unctions as is the case ith P04 ut can e

coi%ured as %eneral I/O onl$. It has a pullFup resistor uiltFin and is co#pletel$ co#patile ith **D

circuits.

"ort 2

P2 acts si#ilarl$ to P0 hen e;ternal #e#or$ is used. Pins o this port occup$ addresses intended or

e;ternal #e#or$ chip. *his ti#e it is aout the hi%her address $te ith addresses -8F-15. When no

#e#or$ is added4 this port can e used as a %eneral input/output port shoin% eatures si#ilar to P1.

"ort

-ll port pins can e used as %eneral I/O4 ut the$ also hae an alternatie unction. In order to use these

alternatie unctions4 a lo%ic one 1! #ust e applied to appropriate it o the P3 re%ister. In te#s o

hardare4 this port is si#ilar to P04 ith the dierence that its pins hae a pullFup resistor uiltFin.

"in's Current limitations

When coni%ured as outputs lo%ic Aero 0!!4 sin%le port pins can receie a current o 10#-. I all 8 its o

a port are actie4 a total current #ust e li#ited to 15#- port P0> 2(#-!. I all ports 32 its! are actie4

total #a;i#u# current #ust e li#ited to +1#-. When these pins are coni%ured as inputs lo%ic 1!4 uiltF

in pullFup resistors proide er$ ea6 current4 ut stron% enou%h to actiate up to " **D inputs o DS

series.

-s seen ro# description o so#e ports4 een thou%h all o the# hae #ore or less si#ilar architecture4 it

is necessar$ to pa$ attention to hich o the# is to e used or hat and ho.

&or e;a#ple4 i the$ shall e used as outputs ith hi%h olta%e leel 5G!4 then P0 should e aoided

ecause its pins do not hae pullFup resistors4 thus %iin% lo lo%ic leel onl$. When usin% other ports4

one should hae in #ind that pullFup resistors hae a relatiel$ hi%h resistance4 so that their pins can %ie

a current o seeral hundreds #icroa#peres onl$.

2.( Memor -rganiation

*he 8051 has to t$pes o #e#or$ and these are Pro%ra# Me#or$ and ata Me#or$. Pro%ra# Me#or$

OM! is used to per#anentl$ sae the pro%ra# ein% e;ecuted4 hile ata Me#or$ -M! is used or

te#poraril$ storin% data and inter#ediate results created and used durin% the operation o the


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#icrocontroller. ependin% on the #odel in use e are still tal6in% aout the 8051 #icrocontroller a#il$

in %eneral! at #ost a e o OM and 128 or 25( $tes o -M is used. 7oeer

-ll 8051 #icrocontrollers hae a 1(Fit addressin% us and are capale o addressin% (" 6 #e#or$. It is

neither a #ista6e nor a i% a#ition o en%ineers ho ere or6in% on asic core deelop#ent. It is a

#atter o s#art #e#or$ or%aniAation hich #a6es these #icrocontrollers a real pro%ra##ers= %ood$.

"rogram Memor

*he irst #odels o the 8051 #icrocontroller a#il$ did not hae internal pro%ra# #e#or$. It as added as

an e;ternal separate chip. *hese #odels are reco%niAale $ their lael e%innin% ith 803 or e;a#ple

8031 or 8032!. -ll later #odels hae a e $te OM e#edded. :en thou%h such an a#ount o

#e#or$ is suicient or ritin% #ost o the pro%ra#s4 there are situations hen it is necessar$ to use

additional #e#or$ as ell. - t$pical e;a#ple are so called loo6up tales. *he$ are used in cases hen

euations descriin% so#e processes are too co#plicated or hen there is no ti#e or solin% the#. In

such cases all necessar$ esti#ates and appro;i#ates are e;ecuted in adance and the inal results are

put in the tales si#ilar to lo%arith#ic tales!.

7o does the #icrocontroller handle e;ternal #e#or$ depends on the :- pin lo%ic state>


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A30In this case4 the #icrocontroller co#pletel$ i%nores internal pro%ra# #e#or$ and e;ecutes onl$ the

pro%ra# stored in e;ternal #e#or$.

A31In this case4 the #icrocontroller e;ecutes irst the pro%ra# ro# uiltFin OM4 then the pro%ra#

stored in e;ternal #e#or$.

In oth cases4 P0 and P2 are not aailale or use since ein% used or data and address trans#ission.


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*he irst loc6 consists o " an6s each includin% 8 re%isters denoted $ 0F+. Prior to accessin% an$ o

these re%isters4 it is necessar$ to select the an6 containin% it. *he ne;t #e#or$ loc6 address 20hF2&h!

is itF addressale4 hich #eans that each it has its on address 0F+&h!. Since there are 1( such

re%isters4 this loc6 contains in total o 128 its ith separate addresses address o it 0 o the 20h $te

is 04 hile address o it + o the 2&h $te is +&h!. *he third %roup o re%isters occup$ addresses 2&hF

+&h4 i.e. 80 locations4 and does not hae an$ special unctions or eatures.

Additional 4AM

In order to satis$ the pro%ra##ers= constant hun%er or ata Me#or$4 the #anuacturers decided to

e#ed an additional #e#or$ loc6 o 128 locations into the latest ersions o the 8051 #icrocontrollers.

7oeer4 it=s not as si#ple as it see#s to e *he prole# is that electronics peror#in% addressin% has

1 $te 8 its! on disposal and is capale o reachin% onl$ the irst 25( locations4 thereore. In order to

6eep alread$ e;istin% 8Fit architecture and co#patiilit$ ith other e;istin% #odels a s#all tric6 asdone.

What does it #ean? It #eans that additional #e#or$ loc6 shares the sa#e addresses ith locations

intended or the S&s 80hF &&h!. In order to dierentiate eteen these to ph$sicall$ separated

#e#or$ spaces4 dierent a$s o addressin% are used. *he S&s #e#or$ locations are accessed $

direct addressin%4 hile additional -M #e#or$ locations are accessed $ indirect addressin%.


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Memor epansion

In case #e#or$ -M or OM! uilt in the #icrocontroller is not suicient4 it is possile to add to

e;ternal #e#or$ chips ith capacit$ o (" each. P2 and P3 I/O ports are used or their addressin% and

data trans#ission.

&ro# the user=s point o ie4 eer$thin% or6s uite si#pl$ hen properl$ connected ecause #ost

operations are peror#ed $ the #icrocontroller itsel. *he 8051 #icrocontroller has to pins or data read

JP3.+! and PS:CJ. *he irst one is used or readin% data ro# e;ternal data #e#or$ -M!4 hile

the other is used or readin% data ro# e;ternal pro%ra# #e#or$ OM!.


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:en thou%h additional #e#or$ is rarel$ used ith the latest ersions o the #icrocontrollers4 e ill

descrie in short hat happens hen #e#or$ chips are connected accordin% to the preious sche#atic.

*he hole process descried elo is peror#ed auto#aticall$.

When the pro%ra# durin% e;ecution encounters an instruction hich resides in e;ternal#e#or$ OM!4 the #icrocontroller ill actiate its control output -D: and set the irst 8

its o address -0F-+! on P0. I) circuit +"7)*5+3 passes the irst 8 its to #e#or$

address pins.

- si%nal on the -D: pin latches the I) circuit +"7)*5+3 and i##ediatel$ aterards 8

hi%her its o address -8F-15! appear on the port. In this a$4 a desired location o

additional pro%ra# #e#or$ is addressed. It is let oer to read its content.

Port P0 pins are coni%ured as inputs4 the PS:C pin is actiated and the #icrocontroller

reads ro# #e#or$ chip.

Si#ilar occurs hen it is necessar$ to read location ro# e;ternal -M. -ddressin% is peror#ed in the

sa#e a$4 hile read and rite are peror#ed ia si%nals appearin% on the control outputs is short

or read! or W is short or rite!.

Addressing

While operatin%4 the processor processes data as per pro%ra# instructions. :ach instruction consists o

to parts. One part descries W7-* should e done4 hile the other e;plains 7OW to do it. *he latter

part can e a data inar$ nu#er! or the address at hich the data is stored. *o a$s o addressin%

are used or all 8051 #icrocontrollers dependin% on hich part o #e#or$ should e accessed>

#irect Addressing

On direct addressin%4 the address o #e#or$ location containin% data to e read is speciied in

instruction. *he address #a$ contain a nu#er ein% chan%ed durin% operation ariale!. &or e;a#ple>

Since the address is onl$ one $te in siAe the lar%est nu#er is 255!4 onl$ the irst 255 locations o -M

can e accessed this a$. *he irst hal o -M is aailale or use4 hile another hal is resered or

S&s.

MOV A,33h;Means: move a number from address 33 hex. to accumulator

+ndirect Addressing


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On indirect addressin%4 a re%ister containin% the address o another re%ister is speciied in instruction.

ata to e used in the pro%ra# is stored in the letter re%ister. &or e;a#ple>

Indirect addressin% is onl$ used or accessin% -M locations aailale or use neer or accessin%

S&s!. *his is the onl$ a$ o accessin% all the latest ersions o the #icrocontrollers ith additional

#e#or$ loc6 128 locations o -M!. Si#pl$ put4 hen the pro%ra# encounters instruction includin% K9

si%n and i the speciied address is hi%her than 128 +& he;.!4 the processor 6nos that indirect

addressin% is used and s6ips #e#or$ space resered or S&s.

MOV A,@R0;Means: Store the value from the register whose address is in the

R0 register

into accumulator

On indirect addressin%4 re%isters 04 1 or Stac6 Pointer are used or speci$in% 8Fit addresses. Since

onl$ 8 its are ailale4 it is possile to access onl$ re%isters o internal -M this a$ 128 locations

hen spea6in% o preious #odels or 25( locations hen spea6in% o latest #odels o #icrocontrollers!. I

an e;tra #e#or$ chip is added then the 1(Fit P* e%ister consistin% o the re%isters P*D and

P*7! is used or speci$in% address. In this a$ it is possile to access an$ location in the ran%e o

(".

2.5 pecial 6unction 4egisters 64s/

Special &unction e%isters S&s! are a sort o control tale used or runnin% and #onitorin% the

operation o the #icrocontroller. :ach o these re%isters as ell as each it the$ include4 has its na#e4

address in the scope o -M and precisel$ deined purpose such as ti#er control4 interrupt control4 serial

co##unication control etc. :en thou%h there are 128 #e#or$ locations intended to e occupied $

the#4 the asic core4 shared $ all t$pes o 8051 #icrocontrollers4 has onl$ 21 such re%isters. est o

locations are intensionall$ let unoccupied in order to enale the #anuacturers to urther deelop

#icrocontrollers 6eepin% the# co#patile ith the preious ersions. It also enales pro%ra#s ritten a

lon% ti#e a%o or #icrocontrollers hich are out o production no to e used toda$.


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A 4egister Accumulator/

- re%ister is a %eneralFpurpose re%ister used or storin% inter#ediate results otained durin% operation.

Prior to e;ecutin% an instruction upon an$ nu#er or operand it is necessar$ to store it in the accu#ulator

irst. -ll results otained ro# arith#etical operations peror#ed $ the -D, are stored in the accu#ulator.

ata to e #oed ro# one re%ister to another #ust %o throu%h the accu#ulator. In other ords4 the -

re%ister is the #ost co##onl$ used re%ister and it is i#possile to i#a%ine a #icrocontroller ithout it.

More than hal instructions used $ the 8051 #icrocontroller use so#eho the accu#ulator.

7 4egister

Multiplication and diision can e peror#ed onl$ upon nu#ers stored in the - and < re%isters. -ll other

instructions in the pro%ra# can use this re%ister as a spare accu#ulator -!.


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urin% the process o ritin% a pro%ra#4 each re%ister is called $ its na#e so that their e;act addresses

are not o i#portance or the user. urin% co#pilation4 their na#es ill e auto#aticall$ replaced $

appropriate addresses.

4 4egisters 40$4&/

*his is a co##on na#e or 8 %eneralFpurpose re%isters 04 14 2 ...+!. :en thou%h the$ are not true

S&s4 the$ desere to e discussed here ecause o their purpose. *he$ occup$ " an6s ithin -M.

Si#ilar to the accu#ulator4 the$ are used or te#porar$ storin% ariales and inter#ediate results durin%

operation. Which one o these an6s is to e actie depends on to its o the PSW e%ister. -ctie an6

is a an6 the re%isters o hich are currentl$ used.

*he olloin% e;a#ple est illustrates the purpose o these re%isters. Suppose it is necessar$ to peror#

so#e arith#etical operations upon nu#ers preiousl$ stored in the re%isters> 1H2! F 3H"!.

Oiousl$4 a re%ister or te#porar$ storin% results o addition is needed. *his is ho it loo6s in the

pro%ra#>


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MOV A,R3; Means: move number from R3 into accumulator

ADD A,R4; Means: add number from R4 to accumulator (result remains in

accumulator)

MOV R5,A; Means: temoraril! move the result from accumulator into R"

MOV A,R1; Means: move number from R# to accumulator

ADD A,R2; Means: add number from R$ to accumulator

SUBB A,R5; Means: subtract number from R" (there are R3%R4)

"rogram tatus Word "W/ 4egister

PSW re%ister is one o the #ost i#portant S&s. It contains seeral status its that relect the current

state o the )P,.


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as to independent 8Fit re%isters. *heir 1( its are pri#arl$ used or e;ternal #e#or$ addressin%.


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on appropriate pin as a olta%e 0 or 5 G! and ice ersa4 olta%e on a pin relects the state o appropriate

port it.

-s #entioned4 port it state aects peror#ance o port pins4 i.e. hether the$ ill e coni%ured as inputs

or outputs. I a it is cleared 0!4 the appropriate pin ill e coni%ured as an output4 hile i it is set 1!4

the appropriate pin ill e coni%ured as an input. ,pon reset and poerFon4 all port its are set 1!4 hich

#eans that all appropriate pins ill e coni%ured as inputs.

I/O ports are directl$ connected to the #icrocontroller pins. -ccordin%l$4 lo%ic state o these re%isters can

e chec6ed $ olt#eter and ice ersa4 olta%e on the pins can e chec6ed $ inspectin% their itsL

2.) Counters and ?imers

-s $ou alread$ 6no4 the #icrocontroller oscillator uses uartA cr$stal or its operation. -s the reuenc$

o this oscillator is precisel$ deined and er$ stale4 pulses it %enerates are ala$s o the sa#e idth4

hich #a6es the# ideal or ti#e #easure#ent. Such cr$stals are also used in uartA atches. In order to

#easure ti#e eteen to eents it is suicient to count up pulses co#in% ro# this oscillator. *hat is

e;actl$ hat the ti#er does. I the ti#er is properl$ pro%ra##ed4 the alue stored in its re%ister ill e

incre#ented or decre#ented! ith each co#in% pulse4 i.e. once per each #achine c$cle. - sin%le

#achineFc$cle instruction lasts or 12 uartA oscillator periods4 hich #eans that $ e#eddin% uartA

ith oscillator reuenc$ o 12M7A4 a nu#er stored in the ti#er re%ister ill e chan%ed #illion ti#es per

second4 i.e. each #icrosecond.

*he 8051 #icrocontroller has 2 ti#ers/counters called *0 and *1. -s their na#es su%%est4 their #ain

purpose is to #easure ti#e and count e;ternal eents.


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-ccordin%l$4 i the content o the ti#er *0 is eual to 0 *0N0! then oth re%isters it consists o ill contain

0. I the ti#er contains or e;a#ple nu#er 1000 deci#al!4 then the *70 re%ister hi%h $te! ill contain

the nu#er 34 hile the *D0 re%ister lo $te! ill contain deci#al nu#er 232.

&or#ula used to calculate alues in these to re%isters is er$ si#ple>

*70 25( H *D0 N *

Matchin% the preious e;a#ple it ould e as ollos>

3 25( H 232 N 1000

Since the ti#er *0 is irtuall$ 1(Fit re%ister4 the lar%est alue it can store is (5 535. In case o e;ceedin%

this alue4 the ti#er ill e auto#aticall$ cleared and countin% starts ro# 0. *his condition is called an

oerlo. *o re%isters *MO and *)OC are closel$ connected to this ti#er and control its operation.

?M-# 4egister ?imer Mode/


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*he *MO re%ister selects the operational #ode o the ti#ers *0 and *1. -s seen in i%ure elo4 the lo

" its it0 F it3! reer to the ti#er 04 hile the hi%h " its it" F it+! reer to the ti#er 1. *here are "

operational #odes and each o the# is descried herein.

@A?1enales and disales *i#er 1 $ #eans o a si%nal rou%ht to the IC*1 pin

P3.3!>

o 1F *i#er 1 operates onl$ i the IC*1 it is set.

o 0F *i#er 1 operates re%ardless o the lo%ic state o the IC*1 it.

C,?1selects pulses to e counted up $ the ti#er/counter 1>

o 1F *i#er counts pulses rou%ht to the *1 pin P3.5!.

o 0F *i#er counts pulses ro# internal oscillator.

?1M1*?1M0*hese to its select the operational #ode o the *i#er 1.

? 1 M 1 ? 1 M 0 M - # # C 4 + " ? + - =

0 0 0 13-bit timer

0 1 1 16-bit timer

1 0 2 8-bit auto-reload

1 1 3 plit mode

@A?0enales and disales *i#er 1 usin% a si%nal rou%ht to the IC*0 pin P3.2!>

o 1F *i#er 0 operates onl$ i the IC*0 it is set.

o 0F *i#er 0 operates re%ardless o the lo%ic state o the IC*0 it.

C,?0selects pulses to e counted up $ the ti#er/counter 0>

o 1F *i#er counts pulses rou%ht to the *0 pin P3."!.

o 0F *i#er counts pulses ro# internal oscillator.

?0M1*?0M0*hese to its select the oprtaional #ode o the *i#er 0.

? 0 M 1 ? 0 M 0 M - # # C 4 + " ? + - =

0 0 0 13-bit timer

0 1 1 16-bit timer

1 0 2 8-bit auto-reload

1 1 3 plit mode

?imer 0 in mode 0 1$it timer/


23/47

*his is one o the rarities ein% 6ept onl$ or the purpose o co#patiilit$ ith the preiuos ersions o

#icrocontrollers. *his #ode coni%ures ti#er 0 as a 13Fit ti#er hich consists o all 8 its o *70 and the

loer 5 its o *D0. -s a result4 the *i#er 0 uses onl$ 13 o 1( its. 7o does it operate? :ach co#in%

pulse causes the loer re%ister its to chan%e their states. -ter receiin% 32 pulses4 this re%ister is

loaded and auto#aticall$ cleared4 hile the hi%her $te *70! is incre#ented $ 1. *his process is

repeated until re%isters count up 812 pulses. -ter that4 oth re%isters are cleared and countin% starts

ro# 0.

?imer 0 in mode 1 1)$it timer/

Mode 1 coni%ures ti#er 0 as a 1(Fit ti#er co#prisin% all the its o oth re%isters *70 and *D0. *hat's

h$ this is one o the #ost co##onl$ used #odes. *i#er operates in the sa#e a$ as in #ode 04 ith

dierence that the re%isters count up to (5 53( as alloale $ the 1( its.


24/47

?imer 0 in mode 2 Auto$4eload ?imer/

Mode 2 coni%ures ti#er 0 as an 8Fit ti#er. -ctuall$4 ti#er 0 uses onl$ one 8Fit re%ister or countin% and

neer counts ro# 04 ut ro# an aritrar$ alue 0F255! stored in another *70! re%ister.

*he olloin% e;a#ple shos the adanta%es o this #ode. Suppose it is necessar$ to constantl$ count

up 55 pulses %enerated $ the cloc6.

I #ode 1 or #ode 0 is used4 It is necessar$ to rite the nu#er 200 to the ti#er re%isters and constantl$

chec6 hether an oerlo has occured4 i.e. hether the$ reached the alue 255. When it happens4 it is

necessar$ to rerite the nu#er 200 and repeat the hole procedure. *he sa#e procedure is

auto#aticall$ peror#ed $ the #icrocontroller i set in #ode 2. In act4 onl$ the *D0 re%ister operates as

a ti#er4 hile another *70! re%ister stores the alue ro# hich the countin% starts. When the *D0

re%ister is loaded4 instead o ein% cleared4 the contents o *70 ill e reloaded to it. eerrin% to the

preious e;a#ple4 in order to re%ister each 55th pulse4 the est solution is to rite the nu#er 200 to the

*70 re%ister and coni%ure the ti#er to operate in #ode 2.


25/47

?imer 0 in Mode plit ?imer/

Mode 3 coni%ures ti#er 0 so that re%isters *D0 and *70 operate as separate 8Fit ti#ers. In other ords4

the 1(Fit ti#er consistin% o to re%isters *70 and *D0 is split into to independent 8Fit ti#ers. *his

#ode is proided or applications reuirin% an additional 8Fit ti#er or counter. *he *D0 ti#er turns into

ti#er 04 hile the *70 ti#er turns into ti#er 1. In addition4 all the control its o 1(Fit *i#er 1 consistin%

o the *71 and *D1 re%ister!4 no control the 8Fit *i#er 1. :en thou%h the 1(Fit *i#er 1 can still e

coni%ured to operate in an$ o #odes #ode 14 2 or 3!4 it is no lon%er possile to disale it as there is no

control it to do it. *hus4 its operation is restricted hen ti#er 0 is in #ode 3.


26/47

*he onl$ application o this #ode is hen to ti#ers are used and the 1(Fit *i#er 1 the operation o

hich is out o control is used as a aud rate %enerator.

?imer Control ?C-=/ 4egister

*)OC re%ister is also one o the re%isters hose its are directl$ in control o ti#er operation.

Onl$ " its o this re%ister are used or this purpose4 hile rest o the# is used or interrupt control to e

discussed later.

?61it is auto#aticall$ set on the *i#er 1 oerlo.

?41it enales the *i#er 1.o 1F *i#er 1 is enaled.

o 0F *i#er 1 is disaled.

?60it is auto#aticall$ set on the *i#er 0 oerlo.

?40it enales the ti#er 0.

o 1F *i#er 0 is enaled.


27/47

o 0F *i#er 0 is disaled.

o; to use the ?imer 0 !

In order to use ti#er 04 it is irst necessar$ to select it and coni%ure the #ode o its operation.

eerrin% to i%ure aoe4 the ti#er 0 operates in #ode 1 and counts pulses %enerated $ internal cloc6

the reuenc$ o hich is eual to 1/12 the uartA reuenc$.

*urn on the ti#er>

*he *0 it is set and the ti#er starts operation. I the uartA cr$stal ith reuenc$ o 12M7A is

e#edded then its contents ill e incre#ented eer$ #icrosecond. -ter (5.53( #icroseconds4 the oth

re%isters the ti#er consists o ill e loaded. *he #icrocontroller auto#aticall$ clears the# and the ti#er

6eeps on repeatin% procedure ro# the e%innin% until the *0 it alue is lo%ic Aero 0!.


28/47

o; to 'read' a timer!

ependin% on application4 it is necessar$ either to read a nu#er stored in the ti#er re%isters or to

re%ister the #o#ent the$ hae een cleared.

F It is e;tre#el$ si#ple to read a ti#er $ usin% onl$ one re%ister coni%ured in #ode 2 or 3. It is suicient

to read its state at an$ #o#ent. *hat's allL

F It is so#eho co#plicated to read a ti#er coni%ured to operate in #ode 2. Suppose the loer $te is

read irst *D0!4 then the hi%her $te *70!. *he result is>

*70 N 15 *D0 N 255

:er$thin% see#s to e o64 ut the current state o the re%ister at the #o#ent o readin% as>

*70 N 1" *D0 N 255

In case o ne%li%ence4 such an error in countin% 255 pulses! #a$ occur or not so oious ut uite

lo%ical reason. *he loer $te is correctl$ read 255!4 ut at the #o#ent the pro%ra# counter as aout

to read the hi%her $te *704 an oerlo occurred and the contents o oth re%isters hae een chan%ed

*70> 1"154 *D0> 2550!. *his prole# has a si#ple solution. *he hi%her $te should e read irst4

then the loer $te and once a%ain the hi%her $te. I the nu#er stored in the hi%her $te is dierent

then this seuence should e repeated. It's aout a short loop consistin% o onl$ 3 instructions in the

pro%ra#.

*here is another solution as ell. It is suicient to si#pl$ turn the ti#er o hile readin% is %oin% on the

*0 it o the *)OC re%ister should e cleared!4 and turn it on a%ain ater readin% is inished.

?imer 0 -erflo; #etection

,suall$4 there is no need to constantl$ read ti#er re%isters. It is suicient to re%ister the #o#ent the$ are

cleared4 i.e. hen countin% starts ro# 0. *his condition is called an oerlo. When it occurrs4 the *&0 it

o the *)OC re%ister ill e auto#aticall$ set. *he state o this it can e constantl$ chec6ed ro# ithin

the pro%ra# or $ enalin% an interrupt hich ill stop the #ain pro%ra# e;ecution hen this it is set.

Suppose it is necessar$ to proide a pro%ra# dela$ o 0.05 seconds 50 000 #achine c$cles!4 i.e. ti#e

hen the pro%ra# see#s to e stopped>

&irst a nu#er to e ritten to the ti#er re%isters should e calculated>


29/47

*hen it should e ritten to the ti#er re%isters *70 and *D0>

When enaled4 the ti#er ill resu#e countin% ro# this nu#er. *he state o the *&0 it4 i.e. hether it is

set4 is chec6ed ro# ithin the pro%ra#. It happens at the #o#ent o oerlo4 i.e. ater e;actl$ 50.000

#achine c$cles or 0.05 seconds.

o; to measure pulse duration!


30/47

Suppose it is necessar$ to #easure the duration o an operation4 or e;a#ple ho lon% a deice has een

turned on? Doo6 a%ain at the i%ure illustratin% the ti#er and pa$ attention to the unction o the E-*:0 it

o the *MO re%ister. I it is cleared then the state o the P3.2 pin doesn't aect ti#er operation. I E-*:0

N 1 the ti#er ill operate until the pin P3.2 is cleared. -ccordin%l$4 i this pin is supplied ith 5G throu%h

so#e e;ternal sitch at the #o#ent the deice is ein% turned on4 the ti#er ill #easure duration o its

operation4 hich actuall$ as the oQectie.

o; to count up pulses!

Si#ilarl$ to the preious e;a#ple4 the anser to this uestion a%ain lies in the *)OC re%ister. *his ti#e

it's aout the )/*0 it. I the it is cleared the ti#er counts pulses %enerated $ the internal oscillator4 i.e.

#easures the ti#e passed. I the it is set4 the ti#er input is proided ith pulses ro# the P3." pin *0!.

Since these pulses are not ala$s o the sa#e idth4 the ti#er cannot e used or ti#e #easure#ent and

is turned into a counter4 thereore. *he hi%hest reuenc$ that could e #easured $ such a counter is

1/2" reuenc$ o used uartAFcr$stal.

?imer 1


31/47

*i#er 1 is identical to ti#er 04 e;cept or #ode 3 hich is a holdFcount #ode. It #eans that the$ hae the

sa#e unction4 their operation is controlled $ the sa#e re%isters *MO and *)OC and oth o the# can

operate in one out o " dierent #odes.

2.& UA4? Uniersal Asnchronous 4eceier and ?ransmitter/

One o the #icrocontroller eatures #a6in% it so poerul is an inte%rated ,-*4 etter 6non as a serial

port. It is a ullFduple; port4 thus ein% ale to trans#it and receie data si#ultaneousl$ and at dierentaud rates. Without it4 serial data send and receie ould e an enor#ousl$ co#plicated part o the

pro%ra# in hich the pin state is constantl$ chan%ed and chec6ed at re%ular interals. When usin% ,-*4

all the pro%ra##er has to do is to si#pl$ select serial port #ode and aud rate. When it's done4 serial

data trans#it is nothin% ut ritin% to the S


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M0F Serial port #ode it 0 is used or serial port #ode selection.

M1F Serial port #ode it 1.

M2F Serial port #ode 2 it4 also 6non as #ultiprocessor co##unication enale it.

When set4 it enales #ultiprocessor co##unication in #ode 2 and 34 and eentuall$

#ode 1. It should e cleared in #ode 0.

4=F eception :nale it enales serial reception hen set. When cleared4 serial

reception is disaled.

?78F *rans#itter it 8. Since all re%isters are 8Fit ide4 this it soles the prole# o

trans#itin% the th it in #odes 2 and 3. It is set to trans#it a lo%ic 1 in the th it.

478F eceier it 8 or the th it receied in #odes 2 and 3. )leared $ hardare i th

it receied is a lo%ic 0. Set $ hardare i th it receied is a lo%ic 1.

?+F *rans#it Interrupt la% is auto#aticall$ set at the #o#ent the last it o one $te is

sent. It's a si%nal to the processor that the line is aailale or a ne $te trans#ite. It

#ust e cleared ro# ithin the sotare.

4+F eceie Interrupt la% is auto#aticall$ set upon one $te receie. It si%nals that $te

is receied and should e read uic6l$ prior to ein% replaced $ a ne data. *his it is

also cleared ro# ithin the sotare.

-s seen4 serial port #ode is selected $ co#inin% the SM0 and SM2 its>

M 0 M 1 M - # # C 4 + " ? + - = 7 A U # 4 A?

0 0 0 8-bit hi!t "e#i$ter 1%12 the &uart' !re&uen()

0 1 1 8-bit *+"T ,etermined b) the timer 1

1 0 2 -bit *+"T 1%32 the &uart' !re&uen() .1%64 the &uart' !re&uen()/

1 1 3 -bit *+"T ,etermined b) the timer 1


33/47

In #ode 04 serial data are trans#itted and receied throu%h the B pin4 hile the *B pin output cloc6s.

*he out rate is i;ed at 1/12 the oscillator reuenc$. On trans#it4 the least si%niicant it DS< it! is

sent/receied irst.

?4A=M+?F ata trans#it is initiated $ ritin% data to the S it :CN1

and IN0 oth o the# are stored in the S)OC re%ister!. When all 8 its hae een receied4 the I it o

the S)OC re%ister is auto#aticall$ set indicatin% that one $te receie is co#plete.


34/47

Since there are no S*-* and S*OP its or an$ other it e;cept data sent ro# the S a S*-* it ala$s 0!4 8 data its DS< irst! and a S*OP it ala$s 1!. *he S*-* it is onl$

used to initiate data receie4 hile the S*OP it is auto#aticall$ ritten to the


35/47

4C+9F *he S*-* it lo%ic Aero 0!! on the B pin initiates data receie. *he olloin% to

conditions #ust e #et> it :CN1 and it IN0.


36/47

In #ode 24 11 its are trans#itted throu%h the *B pin or receied throu%h the B pin> a S*-* it

ala$s 0!4 8 data its DS< irst!4 a pro%ra##ale th data it and a S*OP it ala$s 1!. On trans#it4

the th data it is actuall$ the *


37/47

selected #ode4 oscillator reuenc$ and in so#e cases on the state o the SMO it o the S)OC

re%ister. -ll the necessar$ or#ulas are speciied in the tale>

7 A U # 4 A? 7 + ? M - #

ode 0 Fo$( % 12

ode 11 Fo$(

16 12 .256-T1/BitO,

ode 2Fo$( % 32Fo$( % 64

10

ode 31 Fo$(

16 12 .256-T1/

?imer 1 as a cloc< generator

*i#er 1 is usuall$ used as a cloc6 %enerator as it enales arious aud rates to e easil$ set. *he hole

procedure is si#ple and is as ollos>

&irst4 enale *i#er 1 oerlo interrupt.

)oni%ure *i#er *1 to operate in autoFreload #ode.

ependin% on needs4 select one o the standard alues ro# the tale and rite it to the

*71 re%ister. *hat's all.

7 A U # 4 A ? 6 - C . M B /

7 + ? M - #11052 12 147456 16 20

150 40 h 30 h 00 h 0

300 +0 h 8 h 80 h 75 h 52 h 0

600 ,0 h CC h C0 h BB h + h 0

1200 8 h 6 h 0 h , h ,5 h 0

2400 F4 h F3 h F0 h F h + h 0

4800 F3 h F h F h 1

4800 F+ h F8 h F5 h 0

600 F, h FC h 0

600 F5 h 1

1200 F, h FC h 1

38400 F h 1

76800 FF h 1

Multiprocessor Communication

-s $ou #a$ 6no4 additional th data it is a part o #essa%e in #ode 2 and 3. It can e used or

chec6in% data ia parit$ it. -nother useul application o this it is in co##unication eteen to or #ore


38/47

#icrocontrollers4 i.e. #ultiprocessor co##unication. *his eature is enaled $ settin% the SM2 it o the

S)OC re%ister. -s a result4 ater receiin% the S*OP it4 indicatin% end o the #essa%e4 the serial port

interrupt ill e %enerated onl$ i the it

Suppose there are seeral #icrocontrollers sharin% the sa#e interace. :ach o the# has its on

address. -n address $te diers ro# a data $te ecause it has the th it set 1!4 hile this it is

cleared 0! in a data $te. When the #icrocontroller - #aster! ants to trans#it a loc6 o data to one o

seeral slaes4 it irst sends out an address $te hich identiies the tar%et slae. -n address $te ill

%enerate an interrupt in all slaes so that the$ can e;a#ine the receied $te and chec6 hether it

#atches their address.

O course4 onl$ one o the# ill #atch the address and i##ediatel$ clear the SM2 it o the S)OC

re%ister and prepare to receie the data $te to co#e. Other slaes not ein% addressed leae their SM2

it set i%norin% the co#in% data $tes.

2.8 8051 Microcontroller +nterrupts


39/47

*here are ie interrupt sources or the 80514 hich #eans that the$ can reco%niAe 5 dierent eents that

can interrupt re%ular pro%ra# e;ecution. :ach interrupt can e enaled or disaled $ settin% its o the

I: re%ister. Di6eise4 the hole interrupt s$ste# can e disaled $ clearin% the :- it o the sa#e

re%ister. eer to i%ure elo.

Co4 it is necessar$ to e;plain a e details reerrin% to e;ternal interruptsF IC*0 and IC*1. I the I*0 and

I*1 its o the *)OC re%ister are set4 an interrupt ill e %enerated on hi%h to lo transition4 i.e. on the

allin% pulse ed%e onl$ in that #o#ent!. I these its are cleared4 an interrupt ill e continuousl$

e;ecuted as ar as the pins are held lo.

IE Register (Interrupt

Enable)

AF %loal interrupt enale/disale>

o 0 F disales all interrupt reuests.

o 1 F enales all indiidual interrupt reuests.


40/47

F enales or disales serial interrupt>

o 0 F ,-* s$ste# cannot %enerate an interrupt.

o 1 F ,-* s$ste# enales an interrupt.

?1F it enales or disales *i#er 1 interrupt>

o 0 F *i#er 1 cannot %enerate an interrupt.

o 1 F *i#er 1 enales an interrupt.

1F it enales or disales e;ternal 1 interrupt>

o 0 F chan%e o the pin IC*0 lo%ic state cannot %enerate an interrupt.

o 1 F enales an e;ternal interrupt on the pin IC*0 state chan%e.

?0F it enales or disales ti#er 0 interrupt>

o 0 F *i#er 0 cannot %enerate an interrupt.

o 1 F enales ti#er 0 interrupt.

0F it enales or disales e;ternal 0 interrupt>

o 0 F chan%e o the IC*1 pin lo%ic state cannot %enerate an interrupt.

o 1 F enales an e;ternal interrupt on the pin IC*1 state chan%e.

+nterrupt "riorities

It is not possile to orseen hen an interrupt reuest ill arrie. I seeral interrupts are enaled4 it #a$

happen that hile one o the# is in pro%ress4 another one is reuested. In order that the #icrocontroller

6nos hether to continue operation or #eet a ne interrupt reuest4 there is a priorit$ list instructin% it

hat to do.

*he priorit$ list oers 3 leels o interrupt priorit$>

1. esetL *he apsolute #aster. When a reset reuest arries4 eer$thin% is stopped and the

#icrocontroller restarts.

2. Interrupt priorit$ 1 can e disaled $ eset onl$.

3. Interrupt priorit$ 0 can e disaled $ oth eset and interrupt priorit$ 1.

*he IP e%ister Interrupt Priorit$ e%ister! speciies hich one o e;istin% interrupt sources hae hi%her

and hich one has loer priorit$. Interrupt priorit$ is usuall$ speciied at the e%innin% o the pro%ra#.

-ccordin% to that4 there are seeral possiilities>

I an interrupt o hi%her priorit$ arries hile an interrupt is in pro%ress4 it ill e

i##ediatel$ stopped and the hi%her priorit$ interrupt ill e e;ecuted irst.

I to interrupt reuests4 at dierent priorit$ leels4 arrie at the sa#e ti#e then the

hi%her priorit$ interrupt is sericed irst.


41/47

I the oth interrupt reuests4 at the sa#e priorit$ leel4 occur one ater another4 the one

hich ca#e later has to ait until routine ein% in pro%ress ends.

I to interrupt reuests o eual priorit$ arrie at the sa#e ti#e then the interrupt to e

sericed is selected accordin% to the olloin% priorit$ list>

1. :;ternal interrupt IC*0

2. *i#er 0 interrupt

3. :;ternal Interrupt IC*1

". *i#er 1 interrupt

5. Serial )o##unication Interrupt

+" 4egister +nterrupt "riorit/

*he IP re%ister its speci$ the priorit$ leel o each interrupt hi%h or lo priorit$!.

"F Serial Port Interrupt priorit$ it

o Priorit$ 0

o Priorit$ 1

"?1F *i#er 1 interrupt priorit$

o Priorit$ 0

o Priorit$ 1

"1F :;ternal Interrupt IC*1 priorit$

o Priorit$ 0

o Priorit$ 1

"?0F *i#er 0 Interrupt Priorit$

o Priorit$ 0

o Priorit$ 1

"0F :;ternal Interrupt IC*0 Priorit$

o Priorit$ 0

o Priorit$ 1

andling +nterrupt

When an interrupt reuest arries the olloin% occurs>

1. Instruction in pro%ress is ended.


42/47

2. *he address o the ne;t instruction to e;ecute is pushed on the stac6.

3. ependin% on hich interrupt is reuested4 one o 5 ectors addresses! is ritten to the

pro%ra# counter in accordance to the tale elo>

+ = ? 4 4 U " ? - U 4 C 9 C ? - 4 A # # 4 /

0 3 h

TF0 B h

TF1 1B h

" T 23 h

+ll addre$$e$ are in heade(imal !ormat

".

5. *hese addresses store appropriate suroutines processin% interrupts. Instead o the#4

there are usuall$ Qu#p instructions speci$in% locations on hich these suroutines reside.

(. When an interrupt routine is e;ecuted4 the address o the ne;t instruction to e;ecute is

poped ro# the stac6 to the pro%ra# counter and interrupted pro%ra# resu#es operation

ro# here it let o.

&ro# the #o#ent an interrupt is enaled4 the #icrocontroller is on alert all the ti#e. When an interrupt

reuest arries4 the pro%ra# e;ecution is stopped4 electronics reco%niAes the source and the pro%ra#

Qu#ps9 to the appropriate address see the tale aoe!. *his address usuall$ stores a Qu#p instruction

speci$in% the start o appropriate suroutine. ,pon its e;ecution4 the pro%ra# resu#es operation ro#

here it let o.

4eset

eset occurs hen the S pin is supplied ith a positie pulse in duration o at least 2 #achine c$cles

2" cloc6 c$cles o cr$stal oscillator!. -ter that4 the #icrocontroller %enerates an internal reset si%nal

hich clears all S&s4 e;cept S


43/47

ater turnin% the poer on4 electrical capacitor is ein% char%ed or

seeral #illiseconds thro%h a resistor connected to the %round. *he pin is drien hi%h durin% this process.

When the capacitor is char%ed4 poer suppl$ olta%e is alread$ stale and the pin re#ains connected to

the %round4 thus proidin% nor#al operation o the #icrocontroller. Pressin% the reset utton causes the

capacitor to e te#poraril$ dischar%ed and the #icrocontroller is reset. When released4 the hole process

is repeated

?hrough the program$ step step...

Microcontrollers nor#all$ operate at er$ hi%h speed. *he use o 12 MhA uartA cr$stal enales 1.000.000

instructions to e e;ecuted per second.


44/47

1. :;ternal interrupt sensitie to the si%nal leel should e enaled or e;a#ple IC*0!.

2. *hree olloin% instructions should e inserted into the pro%ra# at the 03he;. address!>

What is %oin% on? -s soon as the P3.2 pin is cleared or e;a#ple4 $ pressin% the utton!4 the

#icrocontroller ill stop pro%ra# e;ecution and Qu#p to the 03he; address ill e e;ecuted. *his address

stores a short interrupt routine consistin% o 3 instructions.

*he irst instruction is e;ecuted until the push utton is realised lo%ic one 1! on the P3.2 pin!. *he

second instruction is e;ecuted until the push utton is pressed a%ain. I##ediatel$ ater that4 the :*I

instruction is e;ecuted and the processor resu#es operation o the #ain pro%ra#. ,pon e;ecution o an$

pro%ra# instruction4 the interrupt IC*0 is %enerated and the hole procedure is repeated push utton is

still pressed!. In other ords4 one utton press F one instruction.

2.% 8051 Microcontroller "o;er Consumption Control

Eenerall$ spea6in%4 the #icrocontroller is inactie or the #ost part and Qust aits or so#e e;ternal si%nal

in order to ta6es its role in a sho. *his can cause so#e prole#s in case atteries are used or poer

suppl$. In e;tre#e cases4 the onl$ solution is to set the hole electronics in sleep #ode in order to

#ini#iAe consu#ption. - t$pical e;a#ple is a *G re#ote controller> it can e out o use or #onths ut

hen used a%ain it ta6es less than a second to send a co##and to *G receier. *he -*8S53 uses

appro;i#atel$ 25#- or re%ular operation4 hich doesn't #a6e it a poerFsain% #icrocontroller. -n$a$4

it doesn=t hae to e ala$s li6e that4 it can easil$ sitch the operatin% #ode in order to reduce its total

consu#ption to appro;i#atel$ "0u-. -ctuall$4 there are to poerFsain% #odes o

operation>Idleand Power Down.


45/47

+dle mode

,pon the ID it o the P)OC re%ister is set4 the #icrocontroller turns o the %reatest poer consu#erF

)P, unit hile peripheral units such as serial port4 ti#ers and interrupt s$ste# continue operatin%

nor#all$ consu#in% (.5#-. In Idle #ode4 the state o all re%isters and I/O ports re#ains unchan%ed.

In order to e;it the Idle #ode and #a6e the #icrocontroller operate nor#all$4 it is necessar$ to enale and

e;ecute an$ interrupt or reset. It ill cause the ID it to e auto#aticall$ cleared and the pro%ra#

resu#es operation ro# instruction hain% set the ID it. It is reco##ended that irst three instructions to

e;ecute no are COP instructions. *he$ don't peror# an$ operation ut proide so#e ti#e or the

#icrocontroller to stailiAe and preents undesired chan%es on the I/O ports.

"o;er #o;n mode


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SMO


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#i6roPro%V or 8051 is supported ith #i6ro)V4 #i6ro

architecture and programming of 8051 mc1_2

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