1 radiation tolerance of commercial 130nm cmos technologies for high energy physics experiments...
TRANSCRIPT
1
Radiation tolerance of commercial 130nm CMOS technologies for High Energy Physics Experiments
Federico Faccio
for the CERN(PH/MIC)-DACEL* collaboration
* DACEL is an INFN project involving the INFN sections of Bari, Bergamo, Bologna, Firenze, Padova, Pavia and Torino
VI FEE MeetingPerugia, 17-20 May 2006
F.Faccio 2
Outline
Past, present and future: 250nm CMOS with HBD approach for the LHC
experiments Motivation for moving to 130nm CMOS
Irradiation results (TID) for 3 different manufacturers (Foundries)
SEE results Conclusion
VI FEE MeetingPerugia, 17-20 May 2006
F.Faccio 3
TID effects in CMOS technologies (1)
Bird’s beak
Field oxide
Parasitic MOS
Parasitic channel
Source
Drain1. Effects in the thin gate oxide
2. Effects in the thick lateral isolation oxide (STI) between source and drain of a transistor
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F.Faccio 4
TID effects in CMOS technologies (2)
3. Effects in the isolation oxide (STI), in between n-well or diffusions
SUBSTRATE
N+ diffusionSTI OXIDE
N+ diffusion
Metal 1
+ + + + + + +STI
SUBSTRATE
N+ diffusionSTI OXIDE
N+ diffusionSTI OXIDE
N+ diffusionN+ diffusion
Metal 1
+ + + + + + +STI
VI FEE MeetingPerugia, 17-20 May 2006
F.Faccio
Past and present: 250nm CMOS
SD
G
Hardness By Design (HBD) approach has been used: ELT transistors
1.E-13
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
-0.5 0.0 0.5 1.0 1.5 2.0 2.5Vg [V]
Lo
g(I
d)
[A]
Prerad
After 13 Mrad
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F.Faccio
Past and present: 250nm CMOS
SD
Gp+ guardring
Hardness By Design (HBD) approach has been used: guardrings
N+ DRAIN N+ SOURCEOXIDE
SUBSTRATE
VDD SS
V
P+ GUARD
SSV
+ + ++++ +
+ + ++ +
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F.Faccio 7
HEP Foundry Service in 250nm CMOS
MPW service organized for more than 100 different ASICs
More than 20 different designs in production (some are multi-ASIC)
More than 2000 wafers (8-inch) produced!
Production summary
0
100
200
300
400
500
600
700
800
900
Y 1999 Y 2000 Y 2001 Y 2002 Y 2003 Y 2004 Y 2005
N o
f w
afer
s p
rod
uce
d
0
2
4
6
8
10
12
14
16
N o
f p
roje
cts
in p
rod
uct
ion
N of wafers produced
N of projects in production
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F.Faccio 8
Motivation to move to 130nm
LHC upgrades & SLHC will require higher-performance ICs, tolerant to larger TID levels
250nm is already an old process and will not stay around much longer
More-modern CMOS processes have the potential of higher TID tolerance and much better performance
What is the radiation tolerance? HBD needed?
VI FEE MeetingPerugia, 17-20 May 2006
F.Faccio 9
Outline
Past, present and future Irradiation results (TID) for 3 different
manufacturers (Foundries) Experimental details Core transistors, linear layout Core transistors, ELT I/O transistors Need for guardrings…
SEE results Conclusion
VI FEE MeetingPerugia, 17-20 May 2006
F.Faccio 10
Test structures and measurement setup
3 commercial 130nm CMOS processes: foundries A,B and C
Some are PMDs from foundry, some custom-designed test ICs
NMOS and PMOS transistors, core and I/O devices (different oxide thickness), FOXFETs
Testing done at probe station – no bonding required
Irradiation with X-rays at CERN up to 100-200Mrad, under worst case static bias
Further studies (p source, reliability, SEGR, noise, …) are under way
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F.Faccio 11
Core NMOS transistors, linear layout (1)
Wide transistors (W > 1m): When the transistor is off or
in the weak inversion regime: Leakage current appears
(for all transistor sizes) Weak inversion curve is
distorted
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
-0.5 0.0 0.5 1.0 1.5 2.0
Vg (V)
Id (
A)
Pre-rad
3Mrad
136Mrad
2d HT ann
Foundry A, 2/0.12
Narrow transistors (W < 0.8m): An apparent Vth shift (decrease)
for narrow channel transistors The narrower the transistor, the
larger the Vth shift (RINCE)
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-0.5 0.0 0.5 1.0 1.5 2.0
Vg (V)
Id (
A)
Pre-rad
3Mrad
136Mrad
2d HT ann
Foundry A, 0.16/0.12
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F.Faccio 12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09
TID (rd)
Ile
ak (
A)
N_10_10
N_10_012
N_088_012
N_053_012
N_028_012
N_016_012
annealingpre-rad
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09
TID (rd)
Ilea
k (A
)
N_10_013
N_04_013
N_024_013
N_018_013
N_014_013
pre-rad
Core NMOS transistors, linear layout (2)
Foundry C
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E+05 1.E+06 1.E+07 1.E+08 1.E+09
TID (rad)
Ilea
k (A
)
0.16/0.120.32/0.120.48/0.120.8/0.122/0.1210/110/10ELT
annealingpre-rad
Foundry A Effect on the leakage current
Peak in leakage at a TID of 1-5Mrad
Peaking dependent on dose rate and temperature, difficult to estimate in real environment
Foundry B
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F.Faccio 13
Core NMOS transistors, linear layout (3) Effect on the threshold voltage
Peak in Vth shift at a TID of 1-5Mrad (A and C)
The narrower the transistor, the larger the Vth shift (RINCE)
Peaking dependent on dose rate and temperature, difficult to estimate in real environment
-0.140
-0.120
-0.100
-0.080
-0.060
-0.040
-0.020
0.000
1.E+05 1.E+06 1.E+07 1.E+08 1.E+09
TID (rd)
V
th (
V)
N_10_10
N_10_012
N_088_012
N_053_012
N_028_012
N_016_012
Foundry C
-0.160
-0.140
-0.120
-0.100
-0.080
-0.060
-0.040
-0.020
0.000
0.020
1.E+05 1.E+06 1.E+07 1.E+08 1.E+09
TID (rad)
Vth
(V
)
016_012032_012048_01208_0122_01210_110_10ELT
annealing
Foundry A
-0.140
-0.120
-0.100
-0.080
-0.060
-0.040
-0.020
0.000
1.E+05 1.E+06 1.E+07 1.E+08 1.E+09
TID (rd)
Vth
(V
)
N_10_013
N_04_013
N_024_013
N_018_013
N_014_013
Foundry B
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F.Faccio 14
Radiation-induced edge effects - NMOS
STISTI
Depletion region
++
+ ++
+
Polysilicon gate
E field lines
--STI
STI
Depletion region
Polysilicon gate
E field lines
++
+ ++
+
Oxide trapped charge
--
--
Interface states
VGS
ID
0
Main transistor
Lateral parasitic transistor
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F.Faccio 15
Core PMOS transistors, linear layout (1) No change in the weak
inversion regime, no leakage An apparent Vth shift
(decrease) for narrow channel transistors The narrower the
transistor, the larger the Vth shift
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
-0.5 0.0 0.5 1.0 1.5 2.0
Vg (V)
Id (
A)
Pre-rad
22.5 Mrd
89.5 Mrd
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
-0.5 0.0 0.5 1.0 1.5 2.0
Vg (V)
Id (
A)
pre-rad
26 Mrd
100 Mrd
Foundry C, 0.28/0.12 Foundry B, 0.14/0.13
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
-0.5 0.0 0.5 1.0 1.5 2.0
Vg (V)
Id (
A)
Pre-rad
3Mrad
30Mrad
136Mrad
1dHT
Foundry A, 0.16/0.12
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F.Faccio 16
Radiation-induced edge effects - PMOS
STISTI
Depletion region
++
+ ++
+
Polysilicon gate
E field lines
--STI
STI
Depletion region
Polysilicon gate
E field lines
++
+ ++
+
Oxide trapped charge
++
++
Interface states
VGS
ID
0
Main transistor
Lateral parasitic transistor
VI FEE MeetingPerugia, 17-20 May 2006
F.Faccio 17
Core NMOS transistors, enclosed layout (ELT)
The radiation hardness of the gate oxide is such that practically no effect is observed – verified for 2 foundries (A up to 140Mrad, B up to 30Mrad)
NMOS ELT min/0.12
1.00E-12
1.00E-11
1.00E-10
1.00E-09
1.00E-08
1.00E-07
1.00E-06
1.00E-05
1.00E-04
1.00E-03
-0.2 0.3 0.8 1.3
Vg (V)
Id (
A)
Pre-rad
3Mrad
136Mrad
2d HT ann
Example: Foundry A
PMOS ELT min/012
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-0.2 0.3 0.8 1.3
Vg (V)
Id (
A) pre-rad
3 Mrd
40 Mrd
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F.Faccio 18
I/O transistors, linear layout
Large effect for all sizes, but more important for narrow channel transistors
Results different with Foundry, but for all enclosed layout is required already for TID levels of the order of 50-100krad (NMOS)
Effect is not negligible also for ELTs: relevant Vth shift!
1.E-13
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-0.5 0.5 1.5 2.5
Vg (V)
Id (
A)
Pre-rad
1.8Mrad
136Mrad
2d HT ann
Foundry A, NMOS 0.36/0.24
1.E-13
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
-0.5 0.5 1.5 2.5
Vg (V)
Id (
A)
Pre-rad
3Mrad
30Mrad
136Mrad
1dHT
Foundry A, PMOS 2/0.24
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F.Faccio 19
Are guardrings systematically needed? (1)
G
SUBSTRATE
N+ diffusionSTI OXIDE
S
N+ diffusion
DMetal 1
+ + + + + + +STI
G
SUBSTRATE
N+ diffusionSTI OXIDE
S
N+ diffusionSTI OXIDE
S
N+ diffusion
D
N+ diffusion
DMetal 1
+ + + + + + +STI
FoxFETs are “Field Oxide Transistors”
Good to characterize isolation properties with TID
Structures available in only 1 technology (1 only Foundry)
1. N+diffusion to N+diffusion (source/drain of two neighbor NMOS transistors)
Foxfet 200/0.18
1.E-13
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-10.00 0.00 10.00 20.00 30.00 40.00
Vg (V)
Id (
A)
ann 2 weeks
65 Mrd
25 Mrd
5 Mrd
3 Mrd
pre-rad
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F.Faccio 20
Are guardrings systematically needed? (2)
2. N+diffusion to Nwell (Nwell with PMOS logic to drain/source of NMOS logic)
SUBSTRATE
N+ diffusionSTI OXIDE
S
N+ WELL CONTACT
N WELL
DMetal 1
G
+ + + + +STI oxide
SUBSTRATE
STI OXIDE
S
STI OXIDE
S
N+ WELL CONTACT
N WELL
D
N+ WELL CONTACT
N WELL
DMetal 1
G
+ + + + +STI oxide
Foxfet 200_03
1.E-13
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-10 10 30 50 70 90Vg (V)
Id (
A)
annealing40 Mrd6 Mrd3 Mrd100 krdpre-rad
Vg=2.5V
Foxfet 200_06
1.E-13
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-10.0 10.0 30.0 50.0 70.0 90.0
Vg (V)
I (A
)
annealing40 Mrd6 Mrd3 Mrd100 krdpre-rad
Vg=2.5V
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F.Faccio 21
Without guardring Partial guardring Full guardring
Are guardrings systematically needed? (3)
Vdd Vdd
N-well
Vdd
N-wellN-well
Realistic test structure with series of Inverters + DFF along 350um, and with different separation between n-well (PMOS logic) and NMOS:
VI FEE MeetingPerugia, 17-20 May 2006
F.Faccio 22
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
TID (rad)
I (A
)
NoGuard
FullGuard
PartialGuard
Are guardrings systematically needed? (4)
VI FEE MeetingPerugia, 17-20 May 2006
F.Faccio 23
Outline
Past, present and future Irradiation results (TID) for 3 different
manufacturers (Foundries) SEE results Conclusion
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F.Faccio 24
SEE results: the SRAM circuit
16kbit SRAM test circuit designed using the SRAM generator from a commercial library provider – not dedicated rad-tolerant design!
Test performed with Heavy Ions at the Legnaro National Laboratories accelerator in June 2005
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F.Faccio 25
Heavy Ion irradiation results
Test at Vdd=1.5 and 1.25 V, results very similar
Sensitivity to very low LET values (threshold below 1.6 MeV/cm2mg)
Comparison with 0.25m memory (rad-tol design!!): Cross-section 15-30
times larger in LHC environment
1.E-10
1.E-09
1.E-08
1.E-07
0 5 10 15 20 25 30 35 40 45 50
LET (Mev/cm2mg)
Cro
ss
-se
cti
on
(c
m2/b
it)
Vdd=1.5V
Vdd=1.25V
Weibull
1.E-10
1.E-09
1.E-08
1.E-07
0 5 10 15 20 25 30 35 40 45 50
LET (MeV/cm2mg)
Cro
ss
-se
cti
on
(c
m2/b
it)
0.13um SRAM @ 1.5V
Weibull 0.13SRAM
0.25um SRAM
Weibull 0.25SRAM
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F.Faccio 26
Challenges for 130nm
Technology more expensive than ¼ micron: Strong push for first working silicon Strong push for common solutions to similar problems
Technology more complex than ¼ micron: Reduced Vdd, difficult for analog Physical effects can not be ignored: proximity effects, filling
requirements, “cheesing”, … As a consequence, design rules are considerably more
complex (impressive growth of the design manual) Larger number of tools is needed
Competence in radiation effects are also required If non-enclosed transistors are used To protect circuits from SEEs
All competences in technology, design techniques and tools necessary for a successful project are more difficult to gather in a group of small size
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F.Faccio 27
Conclusion
HBD in quarter micron has made LHC electronics possible/affordable: large scale application of HBD is a reality!
Natural radiation tolerance of 130nm better than for the quarter micron technology (not for I/O transistors), but Mrad-level still requires HBD for reliable tolerance
Large effort required to develop library, acquire tools, master the technology: Working with 130nm is MUCH more complex and
expensive; pressure to get quickly to working silicon CERN is preparing a frame contract with 1 selected
Foundry, to develop library/design kit/design flow serving the whole HEP community