library characterization techniques for 65nm and 130nm ......outline •introduction to cell...
TRANSCRIPT
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Library Characterization Techniques for 65nm and 130nm Technologies
X. Llopart
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Outline
• Introduction to cell characterization
• Liberate tool (Cadence)
• Characterization example using a combinatorial cell (AND2)
• Applications in HEP
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Disclaimer…
• My origins are full custom analog designer
• This presentation is based in my acquired knowledge using ELC and Liberate tools… but other tools are available
• My objectives are:
1) Demonstrate the advantages of using a Library characterizer tool
2) Change the way we can design chips towards digital on top designs
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Objective of Cell Characterization
• Create a set of high quality models of a standard cell library that accurately and efficiently model cell behaviour
• Theses set of models are used by several different digital design tools for different purposes
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Timing, power, signal Integrity
Timing, power, signal Integrity
Timing, power, signal Integrity
Synthesis
Floorplanning
Place & Route
Timing, Power, Signoffs
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Digital flow in deep submicron technologies
• Nanometre geometries (<65nm) require an increase number of library views: – Issues related to leakage power and process variation
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Liberate reference manual
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What is a Library Characterizer?
• Creates electrical views (timing, power and signal integrity) in industry standard formats such as Synopsys Liberty (.lib) format
• Basically, it requires only the foundry device models and the extracted cell netlists from which it will create all the required electrical views
• By automating the process for generating views, it ensures that the library's functional, timing, power and signal integrity values are both accurate and complete thus avoiding potential chip failures caused by missing or bad library data
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Library Characterizer packages
• The tools need: – Analog simulator (Hspice, Spectre,…)– Netlist of the cells (schematic, parasitic extracted…)– Device models from the technology vendor– Timing arcs definitions
• Many vendors provide today packages (bunch of scripts) which automatizes the process:– Kronos (Mentor Graphics)– Synopsys SiliconSmart– Silvaco– ELC– ALTOS– Liberate (Cadence)
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Liberate (Cadence)
• ELC (Encounter Library Characterizer) not available since January 2015
• Altos renamed to Liberate on 2014
• Europractice includes the Liberate package (Altos until last year):
– Liberate: Standard cell and complex I/O characterization
– Liberate MX: Memory characterization
– Liberate LV: Library verification package
– Liberate AMS: Mixed-Signal characterization (Oct 2014)
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Liberate Automatic Logic Recognition
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Liberate Architecture
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Netlist (.spi, scs)
Liberate(Alspice)
Device model files
Synopsys Lib files (.lib)
NLDM, CCS, ECSM, SI
Verilog files (.v)
Datasheet(.pdf, html,
txt)
External Simulator*(Hspice, Spectre,
Eldo…)
Arc definitions*
Save database for post-
processing (.ldb)
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Example AND2
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schematic layout
extracted abstract
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// Library name: cern_cmos8rf_hd_tsmc_hvtnW
// Cell name: AND2_B_XL_TSMC_HVTN
// View name: av_extracted
subckt AND2_B_XL_TSMC_HVTN A B GND VDD Z
c1 (VDD GND) capacitor c=2.00781e-16
c2 (A GND) capacitor c=1.72585e-16
c3 (B GND) capacitor c=1.40005e-16
c4 (Z GND) capacitor c=5.9908e-17
c5 (net58 GND) capacitor c=2.56284e-17
c6 (net09 GND) capacitor c=9.28723e-17
c7 (\1\:A GND) capacitor c=1.16705e-16
c8 (\1\:B GND) capacitor c=6.54007e-17
c9 (\5\:net09 GND) capacitor c=6.22271e-17
....
rj10 (net09 \3\:net09) resistor r=31.2646 c=0
rj12 (\3\:net09 \5\:net09) resistor r=22.4521 c=0
rj11 (\3\:net09 \4\:net09) resistor r=19.2893 c=0
TPB (\8\:net09 \1\:B \5\:VDD VDD) pch l=1.3e-07 w=3.2e-07 ad=0.0608p \
as=0.22828p pd=0.7u ps=2.37u nrd=0.59375 nrs=2.22925 sa=2.95e-07 sb=8.8e-07 m=1
TPA (\6\:VDD \1\:A \8\:net09 VDD) pch l=1.3e-07 w=3.2e-07 ad=0.2669p \
as=0.0608p pd=2.37u ps=0.7u nrd=2.60645 nrs=0.59375 sa=8.05e-07 sb=3.7e-07 m=1
M0 (\1\:VDD net09 \2\:Z VDD) pch l=1.3e-07 w=6.5e-07 ad=0.3715p \
as=0.28275p pd=2.57u ps=2.17u nrd=0.87929 nrs=0.669231 sa=4.35e-07 sb=1.22989e-06 m=1
TNB (net58 \4\:B \4\:GND GND) nch_hvt l=1.3e-07 w=3e-07 ad=0.057p \
as=0.22687p pd=0.68u ps=2.37u nrd=0.633333 nrs=2.52083 sa=2.95e-07 sb=9.85e-07 m=1
TNA (\9\:net09 \3\:A net58 GND) nch_hvt l=1.3e-07 w=3e-07 ad=0.1425p \
as=0.057p pd=1.55u ps=0.68u nrd=1.58333 nrs=0.633333 sa=8.05e-07 sb=4.75e-07 m=1
M1 (\1\:GND \5\:net09 \1\:Z GND) nch_hvt l=1.3e-07 w=3e-07 ad=0.347p \
as=0.1215p pd=2.57u ps=1.41u nrd=3.85556 nrs=1.35 sa=4.05e-07 sb=1.05854e-06 m=1
ends AND2_B_XL_TSMC_HVTN
// End of subcircuit definition.
// Library name: cern_cmos8rf_hd_tsmc_hvtnW
// Cell name: AND2_B_XL_TSMC_HVTN
// View name: schematic
subckt AND2_B_XL_TSMC_HVTN A B GND VDD Z
M0 (Z net09 VDD VDD) pch l=130n w=650n ad=221f as=221f pd=1.98u \
ps=1.98u nrd=292.308m nrs=292.308m sa=340n sb=340n m=1
TPA (net09 A VDD VDD) pch l=130n w=320n ad=108.8f as=108.8f pd=1.32u \
ps=1.32u nrd=593.75m nrs=593.75m sa=340n sb=340n m=1
TPB (net09 B VDD VDD) pch l=130n w=320n ad=108.8f as=108.8f pd=1.32u \
ps=1.32u nrd=593.75m nrs=593.75m sa=340n sb=340n m=1
M1 (Z net09 GND GND) nch_hvt l=130n w=300n ad=102f as=102f pd=1.28u \
ps=1.28u nrd=633.333m nrs=633.333m sa=340n sb=340n m=1
TNB (net58 B GND GND) nch_hvt l=130n w=300n ad=102f as=102f pd=1.28u \
ps=1.28u nrd=633.333m nrs=633.333m sa=340n sb=340n m=1
TNA (net09 A net58 GND) nch_hvt l=130n w=300n ad=102f as=102f pd=1.28u \
ps=1.28u nrd=633.333m nrs=633.333m sa=340n sb=340n m=1
ends AND2_B_XL_TSMC_HVTN
// End of subcircuit definition.
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AND2 netlist
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Liberate Example Tcl File set rundir $env(PWD)
set CORNER tt
set VOLTAGE 1.2
set TEMPERATURE 25
set cell AND2_B_XL_TSMC_HVTN
# Create the directories Liberate will write to.
exec mkdir -p ${rundir}/LDB
exec mkdir -p ${rundir}/LIBRARY
exec mkdir -p ${rundir}/DATASHEET
exec mkdir -p ${rundir}/VERILOG
set_operating_condition -voltage $VOLTAGE -temp $TEMPERATURE
## Load template information for each cell ##
source ${rundir}/TEMPLATE/cern_cmos8rf_hd_tsmc_hvtnW_v120_tt_25C_hvtn.tcl
read_spice $rundir/MODELS/hspice/include_$CORNER\.sp
read_spice -format spectre ${rundir}/CELLS/cern_cmos8rf_hd_tsmc_hvtnW_nwsx.sch.scs
char_l ibrary -ecsmn -ecsmp -si -cells ${cells} -thread 8
write_ldb ${rundir}/LDB/$SOURCE_LIBRARY\_$VOLTAGE\V\_$TEMPERATURE\C_$CORNER.ldb
write_library -overwrite -ecsmn -si ${rundir}/LIBRARY/$SOURCE_LIBRARY\_$VOLTAGE\V\_$TEMPERATURE\C_$CORNER\_ecsm_si.lib
write_verilog ${rundir}/VERILOG/$SOURCE_LIBRARY\_$VOLTAGE\V\_$TEMPERATURE\C_$CORNER\.v
write_datasheet -format html -dir ${rundir}/DATASHEET/$SOURCE_LIBRARY\_$VOLTAGE\V\_$TEMPERATURE\C_$CORNER test
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Setup Variables
Setup Directories
Define temperature and default voltage
Load template information for each cell
Read device models
Read cell netlist
Characterize Library
Save characterization database for post-processing (.ldb)
Generates a .lib with ccs or/and ecsm, si
Generates a Verilog description (.v)
Generates datasheet (txt, html or pdf)
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if {[ALAPI_active_cell "AND2_A_XL_TSMC_HVTN"]} {define_cell \
-input { A B } \-output { Z } \
-pinlist { A B Z } \-delay delay_template_7x7 \-power power_template_7x7 \-si_immunity si_immunity_template_7x7 \AND2_A_XL_TSMC_HVTN
define_leakage -when "!A&!B" AND2_A_XL_TSMC_HVTNdefine_leakage -when "A&!B" AND2_A_XL_TSMC_HVTNdefine_leakage -when "!A&B" AND2_A_XL_TSMC_HVTNdefine_leakage -when "A&B" AND2_A_XL_TSMC_HVTN
# power arcs from => A hiddendefine_arc \
-type hidden \-vector {Rxx} \
-pin A \AND2_A_XL_TSMC_HVTN
# power arcs from => A hiddendefine_arc \
-type hidden \-vector {Fxx} \-pin A \AND2_A_XL_TSMC_HVTN
# power arcs from => B hiddendefine_arc \
-type hidden \-vector {xRx} \-pin B \
AND2_A_XL_TSMC_HVTN
# power arcs from => B hiddendefine_arc \
-type hidden \
-vector {xFx} \-pin B \AND2_A_XL_TSMC_HVTN
# delay arcs from A => Z positive_unate combinationaldefine_arc \
-vector {RxR} \-related_pin A \
-pin Z \AND2_A_XL_TSMC_HVTN
# delay arcs from A => Z positive_unate combinationaldefine_arc \
-vector {FxF} \-related_pin A \-pin Z \AND2_A_XL_TSMC_HVTN
# delay arcs from B => Z positive_unate combinationaldefine_arc \
-vector {xRR} \-related_pin B \-pin Z \
AND2_A_XL_TSMC_HVTN
# delay arcs from B => Z positive_unate combinationaldefine_arc \
-vector {xFF} \
-related_pin B \-pin Z \AND2_A_XL_TSMC_HVTN
}
define_template -type delay \-index_1 {0.0224 0.0608 0.12 0.32 0.72 1.6 3.0 } \-index_2 {0.0014 0.003 0.0062 0.0125 0.0251 0.0504 0.101 } \delay_template_7x7
define_template -type power \-index_1 {0.0224 0.0608 0.12 0.32 0.72 1.6 3.0 } \-index_2 {0.0014 0.003 0.0062 0.0125 0.0251 0.0504 0.101 } \power_template_7x7
define_template -type si_immunity \-index_1 {0.224 0.608 1.2 3.2 7.2 16.0 30.0 } \-index_2 {0.0014 0.003 0.0062 0.0125 0.0251 0.0504 0.101 } \si_immunity_template_7x7
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Define_cell and define_arc
Cell Definition
Leakage
Dynamic power arcs
Delay arcs
Templates
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cell (AND2_A_XL_TSMC_HVTN) {area : 0;cell_leakage_power : 0.14561;leakage_power () {
value : 0.0891823;when : "!A&!B";
}leakage_power () {value : 0.129436;
when : "A&!B";}leakage_power () {value : 0.146063;when : "!A&B";
}leakage_power () {value : 0.217761;when : "A&B";
}
pin (Z) {direction : output;ecsm_gndres : 2.84782;ecsm_noise_cap : 0.000606332;ecsm_vddres : 7.98722;
function : "(A * B)";max_capacitance : 0.101;output_voltage : "DC_0";timing () {related_pin : "A";
timing_sense : positive_unate;timing_type : combinational;cell_rise (delay_template_7x7) {
index_1 ("0.0224, 0.0608, 0.12, 0.32, 0.72, 1.6, 3");index_2 ("0.0014, 0.003, 0.0062, 0.0125, 0.0251, 0.0504, 0.101");
values ( \"0.0778087, 0.0943178, 0.126192, 0.188057, 0.311119, 0.557708, 1.05057", \"0.0864114, 0.102866, 0.134701, 0.196585, 0.319701, 0.566341, 1.05924", \"0.0989374, 0.115341, 0.147097, 0.208953, 0.332114, 0.578826, 1.07177", \"0.124335, 0.141053, 0.172989, 0.234982, 0.358065, 0.604813, 1.09784", \
"0.150635, 0.168129, 0.200259, 0.261964, 0.385234, 0.63214, 1.12516", \"0.175095, 0.19526, 0.229331, 0.291785, 0.4152, 0.66214, 1.15554", \"0.181677, 0.205527, 0.244012, 0.30901, 0.434542, 0.683591, 1.17743" \
);}
……..
`timescale 1ns/10ps
`celldefine
module AND2_A_XL_TSMC_HVTN (Z, A, B);
output Z;
input A, B;
// Function
and (Z, A, B);
// Timing
specify
specparam tpd_A_Z = 0;
specparam tpd_B_Z = 0;
(A => Z) = tpd_A_Z;
(B => Z) = tpd_B_Z;
endspecify
endmodule
`endcelldefine
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Output files AND2 .lib / .v
.lib .v
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Datasheet output AND2
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Cadence Library Validation
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Liberate LV (Library Verification)
• Data consistency library checking
• compare_library:– Compares in two libraries textually and graphically
– CCS or ECSM delay vs NLDM
– Supports functional overlap
• validate_data_range– Check data is within range, not zero, negative etc
• validate_monotonicity– Ensures that library tables are monotonically increasing
• validate_sdf– Check SDF back-annotation to Verilog/VHDL simulation
data consistency
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compare library
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• Comparison of AND2 cell schematic vs extracted view
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PVT: Process
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• Comparison of AND2 gate
Comparison 1.2V ss/tt 25C Comparison 1.2V ff/tt 25C
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PVT: Voltage
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• Comparison of AND2 gate
Comparison 1.1V vs 1.2V tt 25C Comparison 1.3V vs 1.2V tt 25C
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PVT: Temperature
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• Comparison of AND2 gate
Comparison 1.2V tt 80C/25C Comparison 1.2V tt -20C/25C
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130nm CMOS radiation corner
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• 100 MRad and 400 MRad 130nm models developed by G. Ripamonti (CERN)
• BUFFER_C cell
Comparison preRad/100 Mrad Comparison preRad/400 Mrad
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Liberate LV Validation - Timing and Power
• Compares Spice vs STA (ETS, Tempus, PrimeTime)– Text, Excel or Html reporting and Graphical comparison display (lcplot)
– Arbitrary chain length, user controllable interconnect RC and fanout
– All slews/loads or defined slews/loads or interpolated or extrapolated slew/load
• Also supports STA vs Monte Carlo simulation
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validate_library exampleset rundir $env(PWD)set CORNER ttset SPECTRE_MODELS_FILE "${rundir}/MODELS/tsmc13rf_$CORNER\.scs"set SPECTRE_CMD "/eda/cadence/2014-15/RHELx86/MMSIM_13.11.252/bin/spectre"
set_operating_condition -voltage 1.2 -temp 25
set cells {AND2_A_XL_TSMC_HVTN}set modelspectre $SPECTRE_MODELS_FILEset subckts ${rundir}/CELLS/lat.scs
set_var extsim_cmd "$SPECTRE_CMD -64"set_var extsim_cmd_option " +aps +spice +mt=2 +lqt 0 +errpreset=conservative -format psfbin"set_var extsim_deck_dir "${rundir}/temp/Spectre_decks_$CORNER"
# ETS based flowvalidate_library \
-dir TEMPUS \-timer tempus \-subckts $subckts \-model $modelspectre \-extsim spectre \-extsim_format spectre \-chain_length 10 \-format htm \-timing_models ecsm \-wire_res 100 \-wire_cap 0.010 \-cells ${cells} \LIBRARY/cern_cmos8rf_hd_tsmc_hvtnW_liberate_1.2V_25C_tt_ecsm_si.l ib
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Number of combinatorial elements in the chain
Resistance in Ohms
Capacitance in pF
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10 AND2 cells R=10Ω and C=100fF
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10 Ω 10 Ω
100 fF
10 Ω 10 Ω
100 fF
10 Ω 10 Ω
100 fF
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10 AND2 cells R=1Ω and C=10fF
October 1, 2015 X. Llopart - TWEPP 2015 27
1 Ω 1 Ω
10 fF
1 Ω 1 Ω
10 fF
1 Ω 1 Ω
10 fF
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Liberate AMS (from October 2014)
• Liberate AMS characterizes large macro blocks containing complex custom digital and analog components like PLLs, Serdes, Data Converters,… for timing, power and noise
• Timing arcs generated by designer
• Tool is able to partition the design and simulate only the time path involved time efficient characterization
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Applications for HEP
• Re-characterize cells:
– New PVT corners (temperature, voltage, corner)
– New Models (radiation models)
– Modify input slew or output load templates
• Characterize new cells:
– New Library: CERN 130nm HD library,…
– Complex combinatorial gates: SEU voters,…
– Synchronous cells: Dynamic flip-flops, SEU DFF,…
– To improve digital verification accuracy (GBT/ALPIDE)
• Characterize new mixed-mode blocks
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Examples of Library characterization
• Medipix3 (2011)
• Timepix3 (2013)
• VeloPix (2015)
• GBT serializer (in the appendix)
• ALPIDE (in the appendix)
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Medipix chip family
X. Llopart - TWEPP 2015
0.01
0.1
1
10
0 100 200 300 400 500 600 700
Tra
ns
isto
r d
en
sit
y p
er
pix
el
[trt
s/µ
m2]
CMOS process [nm]
Medipix1 (1998)
Medipix2 (1998)
Timepix (2006)
Clicpix (2013)
October 1, 2015 31
55 µm pixels
170 µm pixels
25 µm pixels
Timepix3 (2013)
Medipix3RX (2011)
Full Custom digital PixelSynthesized digital Pixel
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Medipix3.0
• Medipix3.0 (130nm) pixel was designed in Full Custom mode
– Pixel architecture required that the basic cell was formed by 4 pixels
– >1 year to layout the pixel
– Digital verification done by gate level simulation only
• Gates characterized “by hand”
• Chip debugging showed failure in some operating modes due to poor characterization of cells
October 1, 2015 X. Llopart - TWEPP 2015 32
Medipix3.0 (2009)
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Medipix3.0 pixel counter (24 bits) + control logic
• Synthesized using the CERN IBM 130nm Standard Cell Library (CMOS8RF)
• Area is too big (52 x 33.6) → ~60% pixel area
• High static (leakage) power consumption:
33
55 μm
VDD TempLeakage
in cellleakageIn Chip
1.4 V 125 C 22.5 μW 1.5 W !!!
1.5 V 25 C 223 nW 14.6 mW
1.6 V -55 C 470 pW 30 μW
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A high density low power 130 nm digital library
• The Medipix3RX redesign required significant changes in the digital part of the pixel (designed as a full custom layout)
• Foundry standard digital cell 130nm library available– Too big cells: The foundry digital library has large cells since is targeted for
a general purpose and high speed design ~800MHz !!– High static leakage power: The foundry digital library used regular
transistors
• A custom made high density library (SC_130nm_XL) was designed with the initial idea of using it in the Medipix3RX pixel but with a huge potential impact in later developments (Timepix3, Velopix…)
• Main actions:– Reduce cells height → No need for big buffers (speed)– Keep all transistor small or minimum size (W/L=0.28/0.12)– ADD NV and PV layers → Low power transistors (no area penalty)
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CERN 130nm HD Library
• Physical specs:– “Mainly” Low power transistors– Row Height is fixed to 2.4 µm– Well Tap library
• Maximum frequency < ~700 MHz (@1.5V)
• Encounter Library Characterizer (ELC) used:– Full Synopsis library:
• lib, ecsm, ecsm_si and ccs• delays, static and dynamic power• Corners:
– 1.2V : -55C FF, 25C TT and 125C SS– 1.5V : -55C FF, 25C TT and 125C SS
– Verilog library– LEF files – HTML documentation
• ~50 cells available in the library
6 µm
4.8
µm
Minimum DFF available in default CERN Standard
Cell 130nm library
5.6 µm
2.4
µm
Minimum DFF In the custom made High
density 130nm libraryx2 smaller !!!
1.8
µm
3.8 µm
Minimum DFF available in a commercial Standard
Cell 65nm library x4 smaller !!!
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CERN HD Special cells (I)
• Cells with “non-standard” functional behaviour can be integrated
2.4
µm
3.6 µm
VOTERI_B_XL(VeloPix)
NOR5_A_XL (Medipix3RX)
2.8 µm
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9.6
µm
18 µm
CERN HD Special cells (II)
• Cells with non-standard row height are also possible to integrate:– Row height multiple (2.4 µm)
– Pitch length multiple (0.4 µm)
4.8
µm
14.8 µm
640MHz VCO(Timepix3)
CLK_Q_RVT_XL(Timepix3)
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Medipix3 pixel counter (24 bits) + control logic
• Synthesized using the SC_130nm_XL library
• Area (52 x 16.8) → ~29% pixel area
• Low cell leakage power
38
55 μm
VDD TempLeakage
in cellleakageIn Chip
1.5 V 25 C 2.5 nW 163 μW
1.2 V 25 C 1.15 nW 75.3 μW
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Medipix3.0 vs Medipix3RX
October 1, 2015 X. Llopart - TWEPP 2015 39
110 μm 110 μm
Medipix3.0 (2009):• Full Custom design• Timing problems due to
poor cell characterization
Medipix3RX (2011): • Used SC_130nm_XL• Mixed-mode design• Design worked as simulation
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Medipix3 Counter Specs
October 1, 2015 X. Llopart - TWEPP 2015 40
Medipix3.0 Medipix3RX
Counter TypeConfigurable Binary Ripple Counterwith full dynamic range coverage
Configurable Linear Feedback Shift Register (LFSR) with full dynamic range coverage
Binary output YES NO
Data and Clock multiplexing YES NO
Pixel Counter Depths
2x1bit (1)2x4bit (15)
2x12bit (4095)1x24bit (16777216)
2x1bit (1)2x6bit (63)
2x12bit (4095)1x24bit (16777216)
Overflow control YES (1,4,12 and 24 bits) YES (1,6,12 and 24 bits)
LFSR Decoding No
1 bit6 bit [5:0] mode LUT[64] → [5] ⊕ [4]12 bit [11:0] mode LUT[4096] → [11] ⊕ [5] ⊕ [3] ⊕[0]24 bit [23:0] mode → 2x12 bit LUT[4096]
Glitch ControlNarrow Disc pulses (Hits at Threshold)
Multi-HitShutter ON/OFF
Narrow Disc pulses (Hits at Threshold)Multi-Hit
Shutter ON/OFF
Layout Full custom Synthesized + automatic Place and Route
RoutingLocal Routing: M1 to M4
Global Routing: M5Power distribution: M6,M7,M8
Local Routing: M1 to M4Global Routing: M4
Power distribution: M5,M6,M7
Layout size per pixel (mean) ~1100 µm2 (~36.4% pixel area) ~1075 µm2 (~35.6% pixel area)
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Timepix3 motivation
• Main driving requirements:1. Simultaneous TIME (TOA) and CHARGE (TOT) information per pixel2. Minimize dead time → Event-by-event readout and 0-supressed3. Monotonic TOT in both detection polarities4. Improve time measurements resolution
• Experience gained in the design of the Medipix3RX chip (2011):– Technology (130nm CMOS)– Building blocks recycled (CERN’s HD Standard Cell library, DACs, …)
• Designed by CERN, Nikhef and Bonn University with the support of the Medipix3 Collaboration
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Full Custom Design Synthesized, P&R Design
Timepix3 Pixel Schematic
X. Llopart - TWEPP 2015
Global threshold (LSB= ~10e-)
Front-end (Analog)
LeakageCurrentcompensation
Preamp
Inputpad
1 pixel
VCO@640MHz
Super pixel (Digital)
Controlvoltage
Common for 8 pixels
640MHz
TpA TpB
TestBit MaskBit
Front-end (Digital)
Counters &
Latches
clock(40MHz)
Time stamp
14-bits
Synchronizer&
Clock gating
OP Mode
4-bit LocalThreshold
~50mV/ke-
TOA (14-bit) FTOA (4-bit)TOT (10-bit)TOA & TOT
TOA (14-bit) FTOA (4-bit)TOA
iTOT (14-bit) PC (10-bit)PC & iTOT3fF
3fF
Deserializer[1x31]
Super pixel FIFO
[2x31]
Data outto EOC
37-
bit
s
clock(40MHz)
Token arbitration
31-b
its
handshake
October 1, 2015 42
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Tim
epix
3 F
loo
rpla
n
X. Llopart - TWEPP 2015October 1, 2015
Reset DACOutExtDAC
BandGapGlobal DACs
EoC
[0]
PLLx 2,4,8 and 16
Output Block
PP
ul[0
]
DataInEnableInT0_SyncShutter
EnablePowerPulsingExtTPulse
SLVS_TERM
DataOut[7:0]ClkOutData
ClkIn40PLLOut
Clk
Ou
t4
0,8
0,1
60
or
32
0
Pix
el M
atri
x
E-Fuses32 bits
VDDA/GNDA
VDDPLL/GNDPLL
Sup
erPixel[0
]
Sup
erPixel[0
]
Sup
erPixel[6
3]
Sup
erPixel[6
3]
Sup
erPixel[0
]Su
perP
ixel[63
]
Bus Controller48 bit bus
VDDA33
VDD/GND
Pixel MatrixData controller
Clk
40
Per
iph
ery
Buffered Bias Voltage
OscBias640
Slo
w C
on
tro
l&
Co
mm
and
D
eco
der
Analog Periphery Control Logic
IOP
ads
Res
et
EoC
[1]
PP
ul[1
]
PP
ul[2
]
OscB[2]
EoC
[12
6]
EoC
[12
7]
PP
ul[1
27
]
OscB[63]
PP
ul[1
28
]
OscB[0]
14100 µm
14
08
0 µ
m1
26
0 µ
m8
70
µm
43
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Timepix3 Pixel Logic design strategy
• Use CERN HD Library
• Special cells:– CLK_Q_RVT_XL: Fully integrated inside HD Library
– VCO: • Abstract view
• Capacitive IO definitions inside dedicated .lib file
• Full digital chip verification– SDF signoff back annotated delays
– 3 corners:• 1.5V tt 25C
• 1.6V ff -55C
• 1.4V ss 125C
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Timepix3 Periphery Integration
• Digital on top design• All analog full custom blocks require previous instantiation
in Encounter:– Abstract view LEF, DEF– Liberty Library (.lib)– Liberate AMS not used (it didn’t exist) but it would have help if
available…
• The full periphery can be then integrated together inside the digital flow
• Full digital data path verification (with SDF) from discriminator output (pixel) to output IO pads
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14100 µm
16
21
0 µ
m
Sen
siti
ve A
rea
(14
08
0 µ
m)
Active Periphery (1260 µm)
Pad extenders (870 µm)
Timepix3 Layout
X. Llopart - TWEPP 2015
Double column:2x256pixels64 super pixels
55 µm
55
µm
Super Pixel (SP):• 2x4 pixels• 110x220 μm2
Full Pixel Matrix:256x256 pixels128 double columns
8192 VCOs (640MHz)177 Mtransistors
Active Periphery
Pad Extenders:Removed if TSV
Analog Front-End:• 13x55 μm2
• <25% pixel area
VCO (FTOA):• 9.6x20 μm2
• < 0.8% SP area
IO Pad on digital area:• Careful shielding• Pad is ½ of Timepix
October 1, 2015 46
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Pixel Data readout
• Data readout in Data Driven and Frame Based readout mode works as predicted in post-layout digital simulations
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
0 50 100 150 200 250
Eve
nt
rate
(M
Hz)
Event number
TT1.5V25CSS1.4V125CFF1.6V-55CMeasured
Frame based Full column readout
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Timepix3 testbeam data
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Swiss technology comparison
October 1, 2015 X. Llopart - TWEPP 2015 49
Timepix (2006) Timepix3 (2013)
Thanks to the CERN HD Library !!!
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Introduction
• VeloPix: Hybrid pixel detector (HPD) Readout ASIC for the LHCb VELO upgrade
• The ASIC reads out all bunch crossings at 40 MHz
• Installation planned for LS2
October 1, 2015 X. Llopart - TWEPP 2015 50
VeloPixASICs
The VELO upgrade: Approx. 2.85 Tbit/s 26 module pairs 624 ASICs 41 Mpixels*
*Nokia Lumia 1020 (2013) also has 41 MP camera
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VELOpix
• Pixel upgrade to LHCb VELO (Installation during LS2)
• Based heavily on experience with Timepix3 but with some important differences
– Up to 800Mhits/s/chip (cf 80Mhits/s/chip)
– 4 serialisers at 5Gbps each binary hit information only
• Change of technology decided 1 year ago: IBM 130nm TSMC 130nm
– New HD library developed (IBM TSMC):
• Power supply: 1.5 V 1.2 V
• Devices used PMOSHVT/NMOSHVT PMOS/NMOSHVT improves radiation robustness and balances driving strength
• Track pitch: 0.4 x 0.4 µm 0.41 x 0.46 µm due to different min pitch rules and via sizes
• Status:
– Submission of full chip foreseen in 2015
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IBM TSMC
October 1, 2015 X. Llopart - TWEPP 2015 52
VOTERI_B_IBM_XL(VeloPix)
• >60 cells in CERN TSMC HD library• Characterized and verified with Liberate tool
2.4
µm
3.6 µm
VOTERI_B_TSMC_XL(VeloPix)
2.4
6 µ
m
3.68 µm
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VELOpix MultiSuperPixel 2x16 pixels
October 1, 2015 X. Llopart - TWEPP 2015 53
880 µm
• TMR in pixel configuration bits and in all control logic
• M1-M4 local and global routing and M5-M8 dedicated to power distribution
• ~5000 gates– 35% memory (flip-flops or latches)
– 55% logic
– 311 voters
• 4% smaller that Timepix3 pixel digital block 2.88µm extra for the analog FE block.
78.72 µm
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Conclusions
• What library characterization enables?– Mixed-mode designs true digital verification– Allows modification or addition of new cells in the digital library– Complete std cell provider library files add dynamic power,
noise…– Add specific PVT corner to match application operating
condition (radiation models)– Integrate analog blocks inside digital flow (Liberate AMS)
• For analog designers (my case) helps to understand/trust the digital flow…
• All these tools are based in trusted device models and parasitic circuit extractions:– Silicon verification is required if any of above is not trusted
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Acknowledgments
• T. Hemperek (Bonn University) transfer me his ELC knowledge used in FEI4 chip
• S. Bonacini (CERN) help me through out digital flow understanding
• P. Moreira (GBT) and C. Marin (ALPIDE)
• Cadence for allowing to use some of their original material
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Spare slides
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Liberate
October 1, 2015 X. Llopart - TWEPP 2015 57
Netlist (.spi, scs)
Liberate(Alspice)
Device model files
Synopsys Lib files (.lib)
NLDM, CCS, ECSM, SI
Verilog files (.v)
Datasheet(.pdf, html,
txt)
External Simulator*(Hspice, Spectre,
Eldo…)
Arc definitions*
Save database for post-
processing (.ldb)
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ECSM model
• ECSM: effective current source model:– Uses characterized measurements of current and voltage (I/V
curves) over multiple time intervals, with different combinations of input slew and output loading capacitance.
– These I/V curves are used to create a more accurate output driver model, where each driver is represented as a voltage-controlled current source.
• Models the effects of timing, noise, power, and variation
October 1, 2015 X. Llopart - TWEPP 2015 58
DC
Vout
Driver ModelDriver Model
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Timing Cell Arc Concepts
• All delay information in a library refers to an input-to-output pin pair or an output-to-output pin pair defined as:
– intrinsic delay: The fixed delay from input to output pins
– transition delay: The time it takes the driving pin to change state. Transition delay attributes represent the resistance encountered in making logic transitions
– slope sensitivity: The incremental time delay due to slow change of input signals
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DeSerializer Architecture in the GBTx
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1/3(SKC)
Up
Down
S0
Sp
CK1/2
dataOdd
dataEven
phCntClock2400MHz
dataIn
rxOddReg[59:0]
rxEvenReg[59:0]
Data Re-Sampler
Phase/FreqDetector
ChargePump
LoopFilter
VCO
1-to-3SREG
3-to-15SREG
15-to-60SREG
60REG
1/5 1/4
1-to-3SREG
3-to-15SREG
15-to-60SREG
60REG
clock40MHz
3
3
15
15
60
60
skip
Cyc
le
(240 MHz) (800 MHz) (160 MHz) (40 MHz)
clock80MHz
rxSelectDataInPhase CDR PLLDES 2/120
clock160MHz
Fast dynamic logic “Macro Cell”
1. Full custom logic: DFF, gates, …2. Characterized in ELC (2013)3. “Hand” net list4. Verilog Simulation5. P&R in Encounter6. Timing extracted 7. Back annotation8. Verilog simulation9. Spice simulation
P. Moreira
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ALPIDE MATRIX READ-OUT CIRCUIT
ALICE | 02/12/2014 | César Marin
C. Marin
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OUTLINE
• Priority Encoder Read-Out basic Cell.
• Comparison & differences between pALPIDEV1&V2 &pALPIDE V3.
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C. Marin
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MOTIVATIONS
• Zero Suppressed Read-out
• Read-out only the fired pixels.• Encoded Address.
• Read-out on the same pixel area.
• Fast Read-out.
• Low Power
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ALPIDE matrix read-out circuit
• ALPIDE is the new ultra low-power, CSA-based MAPS for the ALICE Upgrade
• ALPIDE matrix read-out circuit Motivation
– Zero Suppressed Read-out
• Read-out only the fired pixels Encoded Address
– Read-out on the same pixel area
– Fast Read-out
– Low Power
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C. Marin
October 1, 2015
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PRIORITY ENCODER READ-OUTBasic block
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COMPARISONS & DIFFERENCES BETWEENImplementation in pALPIDE V1 & V2
66
• Pixel size: 28 x 28 µm2
• 1024 columns x 512 rows
• Full custom ELC and ALTOS– Custom latch as Storage Element.– Priority encoder circuit per double column
• Fired pixels address encoded of 10 bits every clock cycle
• Max. Freq 10 Mhz
• Manual placement & Routing on 4 Metal Layers.
• Characterization used only for digital simulations
• Net capacitance extracted using liberty files and generating SDF for post layout simulations
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COMPARISONS & DIFFERENCES BETWEENImplementation in pALPIDE V3
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C. Marin
• Pixel size: 29.24 x 26.88 µm2
• 1024 columns x 512 rows
• 3 Full custom FF as Storage Element ALTOS
• Priority encoder circuit per double implemented with TowerJazz STD cells library
• Fired pixels address encoded of 10 bits every clock cycle
• Max. Freq 50 Mhz
• Seimi-automatic Placed & Routed on 4 Metal Layers– Analog Full Custom– Digital P&R flow
• The custom FFs has been characterized modeled and simulated on digital environment
• Digital pixel logic implemented using standard cells from ToweJazz
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Liberate Automatic Logic Recognition
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NLDM, CCS and ECSM formats
• NLDM: non-linear delay model– Input transition vs capacitive load time table
– Valid if technology >=130nm
• New physical effects (<130nm) mean that the NLDM is no longer accurate enough:
– Input capacitances have become more complex
– Interconnect net impedance dominates cell delay
– Voltage drop across the device can have a significant effect on delays
• CCS Composite current source (ccsn, ccsp)
• ECSM Effective current source model (ecsmn, ecsmp)
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Timing Arcs
• Timing arc is a component of a timing path• Types of arcs:
– Cell Arcs: Between an input pin and output pin of a cell (defined in Liberty files (.lib) )• Combinatorial cells (INV, NAND…) IO arcs• Sequential cells (DFF, LAT…) Edge sensitive (clk↑, clk↓), Reset,…
– Net Arcs: Between driver pin of a net and load pin of a net• Calculated inside P&R tool requires parasitic RC technology information
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Cell arcs
A1B1
Z1
A2B2
Z2
Net arcs
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Timing Cell Arc Concepts
• Timing arcs can be delay arcs or constraint arcs
– Delay timing arcs:• Each timing arc has a startpoint and an endpoint:
– The startpoint can be an input, output, or inout pin
– The endpoint is always an output pin or an inout pin
– Constraint timing arcs:• between two input pins:
– such as a setup, hold, recovery or removal constraint related_pin
• Timing arc generation and definition must be understood in case cell recognition is not achieved
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RVT vs LP : VDD vs Power @25C
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0.6 V 0.8 V 1 V 1.2 V 1.4 V 1.6 V
1nA
100pA
10pA
1pA
30
27.5
25
22.5
20
17.5
15
12.5
RVT
LP
RVT/LP
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RVT vs LP : Temp vs Power @VDD=1.2V
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1000
100
10
1
-75 °C -50 °C -25 °C 0 °C 25 °C 50 °C 75 °C 100 °C
10nA
1nA
100pA
10pA
1pA
RVT
LP
RVT/LP
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Simulated Delay
• @ VDD=1.5 the rise/fall times difference between Rvt and LP are:
– ~3ps (0 → 1)
– ~10ps (1 → 0)
• At lower VDDs the delays are more important
741 V 1.25 V 1.5 V 1.75 V
5ps
10ps
15ps
20ps
25ps
30ps
35ps
100ps
200ps
300ps
400ps
500ps
600ps
700ps
No Load
10fF Load
RVT
LP
RVT
LP
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Medipix3RX counter using SC_130nm_XL library
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RX & PC
+ M1
+ M2
110 µm
19.2
µm
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