32 bit alu chip design using ibm 130nm process technology

ALU Chip Design Project #6

The University of Texas at Dallas

Department of Electrical Engineering

EECT 6325 VLSI Design

“ALU CHIP DESIGN”

Team Members:

1) Bharat Biyani (2021152193)

2) Gaurav Kasar (2021177056)

3) Zarin Tasnim Pulam (2021186931)

1


INDEX

Sr.No DESCRIPTION PAGE

1 Introduction 3

2 Block Diagram 3

3 Operation of ALU 4

4 VHDL code 4

5 Synthesized Verilog code 8

6 Cell count report 11

7 Individual gate design 13

8 Layout of ALU 14

9 Schematic of ALU 15

10 DRC Result 15

11 LVS Result 16

12 Prime time report 17

13 Waveform 23

14 Tradeoff and Conclusion 24

2


INTRODUCTION

The report deals with generating the complete layout of the ALU by combining the created cell library into a logic, using the Encounter tool. All the cells are designed to occupy 4 contacts in n-diff and 6 contacts in p-diff.

In the presented project, we have designed a 16 bit Arithmetic and Logical unit which processes the given inputs and gives an output corresponding to the operation selected using VHDL code. The design consists of two 16-bit input lines, a 4-bit select line, a clock input and a 32-bit output line. The operations implemented are 11 which would be presented in the document. The inputs are processed and the output is generated only on falling edge of the clock. The diagram gives the clear understanding of the relation between inputs and output based on the select lines. The VHDL code was simulated in the Modelsim and the output waveforms were also verified for the given set of input values.

Inputs : Ip1 [16:0], Ip2[16:0], Clk, Cnt[3:0]Output : Result [31:0]

BlOCK DIAGRAM

3

Ip1 [15:0]

Clk

Ip2 [15:0]

asdsd

ALU Result [31:0]

Cnt [3:0]


OPERATIONS OF ALU

The following operations are performed by this ALU:

1) Arithmetic: Addition, Subtraction, Multiplication, Square of a number, Sum of N terms, Increment and Decrement, parity Checker

2) Logical: AND, OR, XOR, Negation, 3) Shift operations: Left Shift, Right Shift4) Conversion : Binary to Grey conversion

We started our design by writing VHDL code. We synthesized our code using SYNOPSYS tool and number of cells were checked using a dummy library in the phase 2 of the project and also checked with our design library in the phase 6 of the project.

Below is our VHDL codes and synthesized VERILOG code. We have also included cell final count report which was generated at the end of phase 6 of the project.

VHDL CODE-- Defining Library functionslibrary IEEE;Use IEEE.STD_LOGIC_1164.ALL;Use IEEE.NUMERIC_STD.ALL;Use IEEE.STD_LOGIC_ARITH.ALL;Use IEEE.STD_LOGIC_UNSIGNED.ALL;-- Defining the Entity of ALU-- Initializing the Input and OUPUT PortsEntity ALU_n15 is Port( Ip1 : IN Std_Logic_Vector(15 Downto 0); Ip2 : IN Std_Logic_Vector(15 Downto 0); Cnt : IN Std_Logic_Vector(3 Downto 0); Clk : IN Std_logic; Result: OUT Std_Logic_Vector(31 Downto 0));End ALU_n15;-- Working of the Entity ALUArchitecture Behavior of ALU_n15 is-- Defining the signal type state_type is (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15); Signal next_s: state_type := s15;Begin Process(Ip1, Ip2, Cnt, Clk, next_s)-- Defining the temporary Variables to store the data Variable temp : Std_Logic; Variable temp1: Std_Logic_Vector(15 Downto 0); Variable temp2: Std_Logic_Vector(31 Downto 0); Variable temp3: Std_Logic_Vector(16 Downto 0); Variable Sum : Std_Logic_Vector(31 Downto 0); Variable g : Integer; Begin -- Code for detecting rising edge of Clock If Clk = '1' and Clk'event Then-- Defining the case statement to cover all range of Cnt signal If Cnt <= "0000" Then --- For performing "Addition" operation next_s <= s0; Elsif Cnt <= "0001" Then --- For performing "Substraction" operation

4


next_s <= s1; Elsif Cnt <= "0010" Then --- For performing "Multiplication" operation next_s <= s2; Elsif Cnt <= "0011" Then --- For performing "And" Operation next_s <= s3; Elsif Cnt <= "0100" Then --- For performing "Or" Operation next_s <= s4; Elsif Cnt <= "0101" Then --- For performing "Xor" Operation next_s <= s5; Elsif Cnt <= "0110" Then --- For performing "Not" Operation of Ip2 next_s <= s6; Elsif Cnt <= "0111" Then --- For performing "Increment by 1" operation of Ip2 next_s <= s7; Elsif Cnt <= "1000" Then --- For performing "Decrement by 1" operation of Ip2 next_s <= s8; Elsif Cnt <= "1001" Then --- For performing "left Shift by 1" operation of Ip2 next_s <= s9; Elsif Cnt <= "1010" Then --- For performing "Right Shift by 1" operation of Ip2 next_s <= s10; Elsif Cnt <= "1011" Then --- For performing "Parity Checker" operation of Ip2 next_s <= s11; Elsif Cnt <= "1100" Then --- For performing "Binary to Grey" Conversion of Ip2 next_s <= s12; Elsif Cnt <= "1101" Then --- For performing "Square" operation of Ip2 next_s <= s13; Elsif Cnt <= "1110" Then --- For performing "Sum of first N terms" operation(N = Ip2) next_s <= s14; Else next_s <= s15; End If; -- code of finite state machine Case next_s is

-- Code for Addition of Ip1 and Ip2-- Sum variable to store Sum and temp variable to store Carry When s0 => temp := '0'; For i in 0 to 15 Loop Sum(i) := Ip1(i) XOR Ip2(i) XOR temp; temp := (Ip1(i) AND Ip2(i)) OR (Ip2(i) AND temp) OR (temp AND Ip1(i)); End loop; Sum(16) := temp; Sum(31 Downto 17) := "000000000000000"; Result <= Sum; -- Code for Subtraction of Ip1-Ip2-- Sum variable to store subtraction and temp variable to store Borrow When s1 => temp := '0'; If Ip2 = "0000000000000000" Then Sum(15 Downto 0) := Ip1; Sum(31 Downto 16) := "0000000000000000"; Result <= Sum; Else temp1 := NOT(Ip2); --- performing 2's Complement of Ip2 temp1 := temp1 + "0000000000000001"; For i in 0 to 15 Loop Sum(i) := Ip1(i) XOR temp1(i) XOR temp; temp := (Ip1(i) AND temp1(i)) OR (temp1(i) AND temp) OR (temp AND Ip1(i)); End Loop;-- Assigning the sign to output signal as per the borrow(result is positive or negative) If temp = '0' Then Sum(31 Downto 16) := "1111111111111111"; Else Sum(31 Downto 16) := "0000000000000000"; End If; Result <= Sum; End If; -- Code for Multiplication of Ip1 and Ip2 (each bit of Ip1 with complete Ip2) When s2=>

temp := '0'; temp2 := "0000000000000000" & Ip2; For i in 0 to 15 Loop If temp2(0)='1' Then --- if the 0th bit of Ip2 is 1

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temp3 := ('0' & Ip1) + ('0' & temp2(31 Downto 16)); temp2 := temp3 & temp2(15 Downto 1);

Else --- if the 0th bit of Ip2 is 0 temp2 := '0' & temp2(31 Downto 1);

End If; End Loop; Sum := temp2; Result <= Sum;

-- Code for AND function of Ip1 and Ip2 When s3 => temp := '0'; For i in 0 to 15 Loop Sum(i):= Ip1(i) AND Ip2(i); End Loop; Sum(31 Downto 16) := "0000000000000000"; Result <= Sum; -- Code for OR function of Ip1 and Ip2 When s4=> temp := '0'; For i in 0 to 15 Loop Sum(i):= Ip1(i) OR Ip2(i); End Loop; Sum(31 Downto 16) := "0000000000000000"; Result <= Sum;

-- Code for XOR function of Ip1 and Ip2 When s5 => temp := '0'; For i in 0 to 15 Loop Sum(i):= Ip1(i) XOR Ip2(i); End Loop; Sum(31 Downto 16) := "0000000000000000"; Result <= Sum;

-- Code for NOT function of Ip2 When s6 => temp := '0'; For i in 0 to 15 Loop Sum(i):= NOT(Ip2(i)); End Loop; Sum(31 Downto 16) := "0000000000000000"; Result <= Sum; -- Code for Increment by 1 of Ip2 When s7 => temp := '0'; temp1 := Ip2 ;-- Checking whether the Ip2 is already maximum If Ip2 = "1111111111111111" then Sum(31 Downto 17) := "000000000000000"; Sum(16) := '1'; Sum(15 Downto 0) := "0000000000000000"; Else-- Increment by 1 temp1 := temp1 + "0000000000000001"; Sum(31 Downto 16) := "0000000000000000"; Sum(15 Downto 0) := temp1; End If; Result <= Sum;

-- Code for Decrement by 1 of Ip2 When s8 => temp := '0'; temp1 := Ip2;-- Checking whether the Ip2 is already minimum If Ip2 = "0000000000000000" Then Sum(31 Downto 0) := "11111111111111111111111111111111"; Else-- Decrement by 1 temp1 := temp1 - "0000000000000001"; Sum(15 Downto 0) := temp1; Sum(31 Downto 16) := "0000000000000000"; End If; Result <= Sum;

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-- Code for Left Shift of Ip2 When s9 => temp1 := Ip2 ; temp := temp1(15); g := 15; for i in 0 to 14 Loop temp1(g) := temp1(g-1); g := g - 1; End Loop; temp1(0) := '0'; Sum(16) := temp; Sum(15 Downto 0) := temp1; Sum(31 Downto 17) := "000000000000000"; temp := '0'; Result <= Sum;

-- Code for Right Shift of Ip2 When s10 => temp1 := Ip2 ; temp := temp1(0); For i in 0 to 14 Loop temp1(i) := temp1(i+1); End Loop; temp1(15) := '0'; Sum(15 Downto 0) := temp1; Sum(31 Downto 16) := "0000000000000000"; temp := '0'; Result <= Sum;

-- Code for Parity Checker-- Result signal will be '1' if odd number of 1's in Ip2-- Result signal will be '0' if even number of 1's in Ip2 When s11 => temp := '0'; temp1 := Ip2; For i in 1 to 15 Loop temp1(i) := temp1(i-1) XOR temp1(i); End Loop; If temp1(15) = '1' Then Sum := "00000000000000000000000000000001"; Else Sum := "00000000000000000000000000000000"; End If; Result <= Sum;

-- Code for Binary to Gray Conversion When s12 => temp := '0'; temp1 := Ip2; Sum(15) := temp1(15); For i in 0 to 14 Loop Sum(i) := temp1(i+1) XOR temp1(i); End Loop; Sum(31 Downto 16) := "0000000000000000"; Result <= Sum; -- Code for Square Function When s13 => temp := '0'; temp1 := Ip2; Sum := temp1 * temp1; Result <= Sum; -- Code for Sum of N Terms When s14 => temp1 := Ip2;-- Detect the Boundry Condition i.e. Ip1 = 65535 If temp1 = "1111111111111111" Then temp2 := temp1 * (temp1 - 1);-- Add the Offset temp2 := temp2 + "00000000000000011111111111111110"; Else temp2 := temp1 * (temp1 + 1); End if; temp := temp2(0);-- Code to divide the temp2 value by 2 For i in 0 to (30) Loop

7


temp2(i) := temp2(i+1); End Loop; temp2(31) := '0'; Sum := temp2 ; Result <= Sum; -- Code for unallocated Control Bits When s15 => Sum := "00000000000000000000000000000000"; Result <= Sum; End Case; --- End of Case statements End If; End Process; --- End Process End Behavior;

SYNTHESIZED VERILOG CODE

Header:module inv(inb, outb);input inb;output outb;assign outb = ~inb;endmodule

module nand2(a, b, outb);input a, b;output outb;assign outb = ~(a & b);endmodule

module nor2(a, b, outb);input a, b;output outb;assign outb = ~(a | b);endmodule

module xor2(a, b, outb);input a, b;output outb;assign out = (a ^ b);endmodule

module aoi22(a, b, c, d, outb);input a, b, c, d;output outb;assign outb = ~((a & b) | (c & d));endmodule

module oai3222(a, b, c, d, e, f, g, h, i, outb);input a, b, c, d, e, f, g, h, i;output outb;assign outb = ~((a | b | c) & (d | e) & (f | g) & (h | i));endmodule

module mux21(a, b, s, outb);input a, b, s;output outb;assign outb = (((~s)&a) | (s & b));endmodule

module dff( d, clock, reset, q);input d, clock, reset;output q;reg q;always @(negedge clock or reset) if (reset == 1'b1) q = 1'b0; else q = d;

endmodul

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NETLIST:

module ALU_n15 ( Ip1, Ip2, Cnt, Clk, Result ); input [15:0] Ip1; input [15:0] Ip2; input [3:0] Cnt; output [31:0] Result; input Clk; wire N126, N127, N128, N129, N977, N978, N979, N980, N981, N982, N983, N984, N985, N986, N987, N988, N989, N990, N991, N992, N1008, n975, n976, n977, n978, n979, n980, n981, n982, n983, n984, n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597,

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n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857,

.

.

.

. nand2 U5364 ( .a(Ip1[3]), .b(Ip2[0]), .outb(n5347) ); inv U5365 ( .inb(n5435), .outb(n5434) ); nor2 U5366 ( .a(n5348), .b(n5345), .outb(n5435) ); nand2 U5367 ( .a(Ip1[2]), .b(Ip2[1]), .outb(n5345) ); nand2 U5368 ( .a(n2135), .b(n5436), .outb(n5348) ); nand2 U5369 ( .a(n5342), .b(n5344), .outb(n5436) ); nand2 U5370 ( .a(Ip1[2]), .b(Ip2[0]), .outb(n5344) ); nand2 U5371 ( .a(n2112), .b(n2113), .outb(n5342) ); nor2 U5372 ( .a(n2070), .b(n1104), .outb(n2113) ); inv U5373 ( .inb(Ip1[1]), .outb(n2070) ); nor2 U5374 ( .a(n2146), .b(n1160), .outb(n2112) ); inv U5375 ( .inb(Ip2[1]), .outb(n2071) ); inv U5376 ( .inb(Ip1[0]), .outb(n2146) ); inv U5377 ( .inb(n2069), .outb(n2135) ); nand2 U5378 ( .a(Ip1[1]), .b(Ip2[1]), .outb(n2069) ); nand2 U5379 ( .a(Ip1[15]), .b(Ip2[1]), .outb(n5397) ); nand2 U5380 ( .a(Ip1[15]), .b(Ip2[2]), .outb(n5294) ); nand2 U5381 ( .a(Ip1[15]), .b(Ip2[3]), .outb(n5095) ); nand2 U5382 ( .a(Ip1[15]), .b(Ip2[4]), .outb(n5089) ); nand2 U5383 ( .a(Ip1[15]), .b(Ip2[5]), .outb(n4890) ); nand2 U5384 ( .a(Ip1[15]), .b(Ip2[7]), .outb(n4680) ); nand2 U5385 ( .a(Ip1[15]), .b(Ip2[9]), .outb(n4470) ); nand2 U5386 ( .a(Ip1[15]), .b(Ip2[11]), .outb(n4260) ); nand2 U5387 ( .a(Ip1[15]), .b(Ip2[13]), .outb(n4038) ); nand2 U5388 ( .a(n2153), .b(n2147), .outb(n1472) ); nor2 U5389 ( .a(n1004), .b(n994), .outb(n2147) ); nor2 U5390 ( .a(n1021), .b(n1024), .outb(n2153) );endmodule

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CELL COUNT REPORT

11


****************************************Report : cellDesign : ALU_n15_1Version: D-2010.03-SP3Date : Sun Dec 15 15:33:58 2013**************************************** Attributes: b - black box (unknown) h - hierarchical n - noncombinational r - removable u - contains unmapped logic Cell Reference Library Area Attributes--------------------------------------------------------------------------------Result_reg[0] dff lib_all 76.800003 nResult_reg[1] dff lib_all 76.800003 nResult_reg[2] dff lib_all 76.800003 nResult_reg[3] dff lib_all 76.800003 nResult_reg[4] dff lib_all 76.800003 nResult_reg[5] dff lib_all 76.800003 nResult_reg[6] dff lib_all 76.800003 nResult_reg[7] dff lib_all 76.800003 n

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.

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lib_all 15.360000 U5379 nand2 lib_all 15.360000 U5380 nand2 lib_all 15.360000 U5381 nand2 lib_all 15.360000 U5382 nand2 lib_all 15.360000 U5383 nand2 lib_all 15.360000 U5384 nand2 lib_all 15.360000 U5385 nand2 lib_all 15.360000 U5386 nand2 lib_all 15.360000 U5387 nand2 lib_all 15.360000 U5388 nand2 lib_all 15.360000 U5389 nor2 lib_all 15.360000 U5390 nor2 lib_all 15.360000 next_s_reg[0] dff lib_all 76.800003 nnext_s_reg[1] dff lib_all 76.800003 nnext_s_reg[2] dff lib_all 76.800003 nnext_s_reg[3] dff lib_all 76.800003 n--------------------------------------------------------------------------------Total 4531 cells 74242.560727

***** End Of Report ****

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INDIVIDUAL GATE DESIGN

As a part of project phase 4 and 5, individual logic gates of our cell library was generated using cadence software. The layout, abstract views and schematics and the output waveforms were verified for the following logic gates

1. Inverter2. NAND gate3. NOR gate4. AOI21 gate5. OA322 gate6. XOR gate7. Multiplexer8. D-flipflop

We have already submitted layout, schematic and waveform of individual logic gates stating the correct functionality.

PLACING AND ROUTING

Cadence Encounter is used for the automatic placement and routing of synthesized verilog netlist. DRC and LVS are performed to check for errors .

Symbol View:

13


FINAL LAYOUT

14


FINAL SCHEMATIC

15


DRC RESULT

LVS REPORT

16


PRIME TIME REPORT

Primetime result values are highlighted in the above report. . Summary of auto genetated report by prime time are mentioned in below report:

PrimeTime (R) PrimeTime (R) SI PrimeTime (R) PX Version D-2010.06-SP1 for suse64 -- Jul 15, 2010 Copyright (c) 1988-2010 by Synopsys, Inc. ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys, Inc.and may be used and disclosed only as authorized in a license agreementcontrolling such use and disclosure.

################################################################ Define search path verilog file and library and variables###############################################################set search_path "~/cad/files/"~/cad/files/source variables1reset################################################################ link library################################################################set link_library $library_file#set target_library $library_fileset link_library [list $library_file ]~/cad/files/library.dbset target_library [list $library_file ]~/cad/files/library.db################################################################ link design###############################################################remove_design -allError: Nothing matched for designs: there are none loaded (SEL-005)0read_verilog $verilog_file

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Loading verilog file '/home/eng/b/bxb125030/cad/files/mainVCode_syn.v'1################################################################ Define IO parameters###############################################################set_driving_cell -lib_cell $driving_cell -input_transition_rise $input_transition -input_transition_fall $input_transition [all_inputs]Loading db file '/home/eng/b/bxb125030/cad/files/library.db'Linking design ALU_n15...Information: Issuing set_operating_conditions for setting analysis mode on_chip_variation. (PTE-037)set_operating_conditions -analysis_type on_chip_variation -library [get_libs {library.db:lib_all}] 1set_load $load [all_outputs]1###############################################################################################################################define the clock - for comb circuit we may not need to use any clock###############################################################create_clock -name clk -period $clock_period [get_ports $clock_pin_name]1set_clock_transition -rise -max $input_transition [get_clocks clk]1set_clock_transition -fall -max $input_transition [get_clocks clk]1################################################################ set condition###############################################################set timing_slew_propagation_mode worst_slewworst_slewset timing_report_unconstrained_paths truetrueset power_enable_analysis truetrueset_disable_timing [get_ports $reset_pin_name]Warning: No port objects matched 'reset' (SEL-004)Error: Nothing matched for ports (SEL-005)Error: Nothing matched for object_list (SEL-005)

################################################################ analyze delay and power###############################################################check_timingWarning: Some timing arcs have been disabled for breaking timing loops

or because of constant propagation. Use the 'report_disable_timing'command to get the list of these disabled timing arcs. (PTE-003)

Information: Checking 'no_input_delay'.Warning: There are 36 ports with no clock-relative input delay specified.Since the variable 'timing_input_port_default_clock' is 'true',a default input port clock will be assumed for these ports.

Information: Checking 'no_driving_cell'.Information: Checking 'unconstrained_endpoints'.Warning: There are 32 endpoints which are not constrained for maximum delay.

Information: Checking 'unexpandable_clocks'.Information: Checking 'latch_fanout'.Information: Checking 'no_clock'.Information: Checking 'partial_input_delay'.Information: Checking 'generic'.Information: Checking 'loops'.Information: Checking 'generated_clocks'.Information: Checking 'pulse_clock_non_pulse_clock_merge'.Information: Checking 'pll_configuration'.0update_timing1report_timing -transition_time -delay min_max -capacitance -input_pins

****************************************Report : timing

-path_type full-delay_type min_max-input_pins-max_paths 1-transition_time-capacitance

Design : ALU_n15

18


Version: D-2010.06-SP1Date : Thu Dec 12 19:37:35 2013****************************************

Startpoint: Cnt[0] (input port) Endpoint: next_s_reg[0] (falling edge-triggered flip-flop clocked by clk') Path Group: clk Path Type: min

Point Cap Trans Incr Path ----------------------------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f Cnt[0] (in) 4.77 10.34 4.83 4.83 f next_s_reg[0]/d (dff) 10.34 0.00 4.83 f data arrival time 4.83

clock clk' (fall edge) 20.00 0.00 0.00 clock network delay (ideal) 0.00 0.00 next_s_reg[0]/clock (dff) 0.00 f library hold time 2.60 2.60 data required time 2.60 ----------------------------------------------------------------------------- data required time 2.60 data arrival time -4.83 ----------------------------------------------------------------------------- slack (MET) 2.23

Startpoint: Ip2[1] (input port) Endpoint: Result_reg[30] (falling edge-triggered flip-flop clocked by clk') Path Group: clk Path Type: max

Point Cap Trans Incr Path ----------------------------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 input external delay 0.00 0.00 r Ip2[1] (in) 140.12 236.49 195.05 195.05 r U1081/inb (inv) 236.49 0.00 195.05 r U1081/outb (inv) 21.67 65.16 71.20 266.26 f U5374/b (nor2) 65.16 0.00 266.26 f U5374/outb (nor2) 12.24 61.04 80.95 347.21 r U5371/a (nand2) 61.04 0.00 347.21 r U5371/outb (nand2) 11.85 33.79 48.03 395.24 f U5369/a (nand2) 33.79 0.00 395.24 f U5369/outb (nand2) 4.80 28.20 32.57 427.81 r U5368/b (nand2) 28.20 0.00 427.81 r U5368/outb (nand2) 15.91 32.09 44.49 472.30 f U5366/a (nor2) 32.09 0.00 472.30 f U5366/outb (nor2) 4.82 39.89 52.72 525.02 r U5365/inb (inv) 39.89 0.00 525.02 r U5365/outb (inv) 4.35 14.29 20.56 545.58 f U5363/a (aoi22) 14.29 0.00 545.58 f U5363/outb (aoi22) 9.39 49.78 61.54 607.13 r U5358/inb (inv) 49.78 0.00 607.13 r U5358/outb (inv) 11.46 22.53 32.74 639.87 f U5267/b (xor2) 22.53 0.00 639.87 f U5267/outb (xor2) 7.36 26.79 70.83 710.70 f U5266/b (xor2) 26.79 0.00 710.70 f U5266/outb (xor2) 11.71 33.85 77.14 787.84 f U5250/a (aoi22) 33.85 0.00 787.84 f U5250/outb (aoi22) 16.93 7.37 86.90 874.74 r U5161/b (xor2) 67.37 0.00 874.74 r U5161/outb (xor2) 7.68 53.49 83.42 958.17 r U5160/a (xor2) 53.49 0.00 958.17 r U5160/outb (xor2) 12.36 67.30 105.93 1064.10 r U5159/inb (inv) 67.30 0.00 1064.10 r U5159/outb (inv) 4.35 19.00 23.46 1087.56 f U5143/a (aoi22) 19.00 0.00 1087.56 f U5143/outb (aoi22) 16.93 67.37 80.26 1167.82 r U5058/b (xor2) 67.37 0.00 1167.82 r

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U5058/outb (xor2) 7.68 53.11 83.42 1251.24 r U5057/a (xor2) 53.11 0.00 1251.24 r U5057/outb (xor2) 12.36 67.27 105.87 1357.11 r U5056/inb (inv) 67.27 0.00 1357.11 r U5056/outb (inv) 4.35 18.99 23.46 1380.57 f U5040/a (aoi22) 18.99 0.00 1380.57 f U5040/outb (aoi22) 16.93 67.37 80.26 1460.83 r U4950/b (xor2) 67.37 0.00 1460.83 r U4950/outb (xor2) 7.68 53.11 83.42 1544.25 r U4949/a (xor2) 53.11 0.00 1544.25 r U4949/outb (xor2) 12.36 67.27 105.87 1650.12 r U4948/inb (inv) 67.27 0.00 1650.12 r U4948/outb (inv) 4.35 18.99 23.46 1673.58 f U4932/a (aoi22) 18.99 0.00 1673.58 f U4932/outb (aoi22) 16.93 67.37 80.26 1753.84 r U4846/b (xor2) 67.37 0.00 1753.84 r U4846/outb (xor2) 7.68 53.11 83.42 1837.26 r U4845/a (xor2) 53.11 0.00 1837.26 r U4845/outb (xor2) 12.36 67.28 105.87 1943.13 r U4844/inb (inv) 67.28 0.00 1943.13 r U4844/outb (inv) 4.35 18.99 23.46 1966.59 f U4828/a (aoi22) 18.99 0.00 1966.59 f U4828/outb (aoi22) 16.93 67.37 80.26 2046.85 r U4733/b (xor2) 67.37 0.00 2046.85 r U4733/outb (xor2) 7.68 53.11 83.42 2130.27 r U4732/a (xor2) 53.11 0.00 2130.27 r U4732/outb (xor2) 12.36 67.27 105.87 2236.14 r U4731/inb (inv) 67.27 0.00 2236.14 r U4731/outb (inv) 4.35 18.99 23.46 2259.60 f U4715/a (aoi22) 18.99 0.00 2259.60 f U4715/outb (aoi22) 16.93 67.37 80.26 2339.86 r U4630/b (xor2) 67.37 0.00 2339.86 r U4630/outb (xor2) 7.68 53.11 83.42 2423.28 r U4629/a (xor2) 53.11 0.00 2423.28 r U4629/outb (xor2) 12.36 67.27 105.87 2529.15 r U4628/inb (inv) 67.27 0.00 2529.15 r U4628/outb (inv) 4.35 18.99 23.46 2552.61 f U4612/a (aoi22) 18.99 0.00 2552.61 f U4612/outb (aoi22) 16.93 67.37 80.26 2632.87 r U4516/b (xor2) 67.37 0.00 2632.87 r U4516/outb (xor2) 7.68 53.11 83.42 2716.28 r U4515/a (xor2) 53.11 0.00 2716.28 r U4515/outb (xor2) 12.36 67.27 105.87 2822.16 r U4514/inb (inv) 67.27 0.00 2822.16 r U4514/outb (inv) 4.35 18.99 23.46 2845.62 f U4498/a (aoi22) 18.99 0.00 2845.62 f U4498/outb (aoi22) 16.93 67.37 80.26 2925.87 r U4413/b (xor2) 67.37 0.00 2925.87 r U4413/outb (xor2) 7.68 53.11 83.42 3009.29 r U4412/a (xor2) 53.11 0.00 3009.29 r U4412/outb (xor2) 12.36 67.27 105.87 3115.17 r U4411/inb (inv) 67.27 0.00 3115.17 r U4411/outb (inv) 4.35 18.99 23.46 3138.63 f U4395/a (aoi22) 18.99 0.00 3138.63 f U4395/outb (aoi22) 16.93 67.37 80.26 3218.88 r U4299/b (xor2) 67.37 0.00 3218.88 r U4299/outb (xor2) 7.68 53.11 83.42 3302.30 r U4298/a (xor2) 53.11 0.00 3302.30 r U4298/outb (xor2) 12.36 67.27 105.87 3408.18 r U4297/inb (inv) 67.27 0.00 3408.18 r U4297/outb (inv) 4.35 18.99 23.46 3431.63 f U4281/a (aoi22) 18.99 0.00 3431.63 f U4281/outb (aoi22) 16.93 67.37 80.26 3511.89 r U4196/b (xor2) 67.37 0.00 3511.89 r U4196/outb (xor2) 7.68 53.11 83.42 3595.31 r U4195/a (xor2) 53.11 0.00 3595.31 r U4195/outb (xor2) 12.36 67.27 105.87 3701.18 r U4194/inb (inv) 67.27 0.00 3701.18 r U4194/outb (inv) 4.35 18.99 23.46 3724.64 f U4178/a (aoi22) 18.99 0.00 3724.64 f U4178/outb (aoi22) 16.93 67.37 80.26 3804.90 r U4082/b (xor2) 67.37 0.00 3804.90 r U4082/outb (xor2) 7.68 53.11 83.42 3888.32 r U4081/a (xor2) 53.11 0.00 3888.32 r U4081/outb (xor2) 12.36 67.27 105.87 3994.19 r U4080/inb (inv) 67.27 0.00 3994.19 r

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U4080/outb (inv) 4.35 18.99 23.46 4017.65 f U4064/a (aoi22) 18.99 0.00 4017.65 f U4064/outb (aoi22) 16.93 67.37 80.26 4097.91 r U4061/a (nand2) 67.37 0.00 4097.91 r U4061/outb (nand2) 4.32 24.95 33.97 4131.88 f U4059/b (aoi22) 24.95 0.00 4131.88 f U4059/outb (aoi22) 16.93 67.37 89.17 4221.06 r U4056/a (nand2) 67.37 0.00 4221.06 r U4056/outb (nand2) 4.32 24.95 33.97 4255.03 f U4054/b (aoi22) 24.95 0.00 4255.03 f U4054/outb (aoi22 16.93 67.37 89.17 4344.20 r U4051/a (nand2) 67.37 0.00 4344.20 r U4051/outb (nand 4.32 24.95 33.97 4378.18 f U4049/b (aoi22) 24.95 0.00 4378.18 f U4049/outb (aoi22 16.93 67.37 89.17 4467.35 r U4046/a (nand2) 67.37 0.00 4467.35 r U4046/outb (nand 4.32 24.95 33.97 4501.32 f U4044/b (aoi22) 24.95 0.00 4501.32 f U4044/outb (aoi22 16.93 67.37 89.17 4590.50 r U4041/a (nand2) 67.37 0.00 4590.50 r U4041/outb (nand2) 4.32 24.95 33.97 4624.47 f U4039/b (aoi22) 24.95 0.00 4624.47 f U4039/outb (aoi22) 16.93 67.37 89.17 4713.64 r U4036/a (nand2) 67.37 0.00 4713.64 r U4036/outb (nand2) 4.32 24.95 33.97 4747.61 f U4034/b (aoi22) 24.95 0.00 4747.61 f U4034/outb (aoi22) 16.93 67.37 89.17 4836.79 r U4031/a (nand2) 67.37 0.00 4836.79 r U4031/outb (nand2) 4.32 24.95 33.97 4870.76 f U4029/b (aoi22) 24.95 0.00 4870.76 f U4029/outb (aoi22) 16.93 67.37 89.17 4959.93 r U4026/a (nand2) 67.37 0.00 4959.93 r U4026/outb (nand2) 4.32 24.95 33.97 4993.91 f U4024/b (aoi22) 24.95 0.00 4993.91 f U4024/outb (aoi22) 16.93 67.37 89.17 5083.08 r U3992/b (xor2) 67.37 0.00 5083.08 r U3992/outb (xor2) 7.68 53.49 83.42 5166.50 r U3991/a (xor2) 53.49 0.00 5166.50 r U3991/outb (xor2) 12.36 67.28 105.93 5272.44 r U3990/inb (inv) 67.28 0.00 5272.44 r U3990/outb (inv) 4.35 18.99 23.46 5295.90 f U3910/a (aoi22) 18.99 0.00 5295.90 f U3910/outb (aoi22) 16.93 67.37 80.26 5376.15 r U3907/a (nand2) 67.37 0.00 5376.15 r U3907/outb (nand2) 4.32 24.95 33.97 5410.13 f U3905/b (aoi22) 24.95 0.00 5410.13 f U3905/outb (aoi22) 16.93 67.37 89.17 5499.30 r U3902/a (nand2) 67.37 0.00 5499.30 r U3902/outb (nand2) 4.32 24.95 33.97 5533.27 f U3900/b (aoi22) 24.95 0.00 5533.27 f U3900/outb (aoi22) 16.93 67.37 89.17 5622.45 r U3897/a (nand2) 67.37 0.00 5622.45 r U3897/outb (nand2) 4.32 24.95 33.97 5656.42 f U3895/b (aoi22) 24.95 0.00 5656.42 f U3895/outb (aoi22) 9.39 48.84 72.73 5729.15 r U3891/inb (inv) 48.84 0.00 5729.15 r U3891/outb (inv) 11.46 22.28 32.49 5761.64 f U3876/b (xor2) 22.28 0.00 5761.64 f U3876/outb (xor2) 7.46 30.06 70.83 5832.47 f U3875/a (xor2) 30.06 0.00 5832.47 f U3875/outb (xor2) 11.81 32.31 86.16 5918.63 f U3782/a (aoi22) 32.31 0.00 5918.63 f U3782/outb (aoi22) 16.93 67.37 86.23 6004.86 r U3779/a (nand2) 67.37 0.00 6004.86 r U3779/outb (nand2) 4.32 24.95 33.97 6038.83 f U3777/b (aoi22) 24.95 0.00 6038.83 f U3777/outb (aoi22) 13.70 59.40 82.10 6120.93 r U3775/a (nor2) 59.40 0.00 6120.93 r U3775/outb (nor2) 4.42 20.93 29.94 6150.87 f U3774/inb (inv) 20.93 0.00 6150.87 f U3774/outb (inv) 9.20 22.06 31.84 6182.72 r U1154/a (nand2) 22.06 0.00 6182.72 r U1154/outb (nand2) 7.36 19.15 29.25 6211.97 f U1153/b (xor2) 19.15 0.00 6211.97 f U1153/outb (xor2) 4.10 19.41 65.90 6277.87 f U1152/d (aoi22) 19.41 0.00 6277.87 f

21


U1152/outb (aoi22) 4.80 37.73 42.58 6320.46 r U1151/b (nand2) 37.73 0.00 6320.46 r U1151/outb (nand2) 4.77 17.99 30.91 6351.37 f Result_reg[30]/d (dff) 17.99 0.00 6351.37 f data arrival time 6351.37

clock clk' (fall edge) 0.00 6400.00 6400.00 clock network delay (ideal) 0.00 6400.00 Result_reg[30]/clock (dff) 6400.00 f library setup time -39.70 6360.30 data required time 6360.30 ----------------------------------------------------------------------------- data required time 6360.30 data arrival time -6351.37 ----------------------------------------------------------------------------- slack (MET) 8.93

1update_powerInformation: Checked out license 'PrimeTime-PX' (PT-019)Warning: Neither event file or switching activity data present for power estimation. The command will propagate switching activity values for power calculation. (PWR-246)Information: Running averaged power analysis... (PWR-601)1report_power

****************************************Report : Averaged PowerDesign : ALU_n15Version: D-2010.06-SP1Date : Thu Dec 12 19:37:37 2013****************************************

Attributes ---------- i - Including register clock pin internal power u - User defined power group

Internal Switching Leakage TotalPower Group Power Power Power Power ( %) Attrs--------------------------------------------------------------------------------io_pad 0.0000 0.0000 0.0000 0.0000 ( 0.00%) memory 0.0000 0.0000 0.0000 0.0000 ( 0.00%) black_box 0.0000 0.0000 0.0000 0.0000 ( 0.00%) clock_network 3.116e-04 4.094e-05 8.268e-10 3.526e-04 (23.11%) iregister 2.908e-05 1.679e-06 3.284e-07 3.109e-05 ( 2.04%) combinational 5.384e-04 5.984e-04 4.893e-06 1.142e-03 (74.85%) sequential 0.0000 0.0000 0.0000 0.0000 ( 0.00%)

Net Switching Power = 6.410e-04 (42.02%) Cell Internal Power = 8.791e-04 (57.63%) Cell Leakage Power = 5.222e-06 ( 0.34%) ---------Total Power = 1.525e-03 (100.00%)

1Information: Defining new variable 'driving_cell'. (CMD-041)Information: Defining new variable 'library_file'. (CMD-041)Information: Defining new variable 'verilog_file'. (CMD-041)Information: Defining new variable 'input_transition'. (CMD-041)Information: Defining new variable 'clock_period'. (CMD-041)Information: Defining new variable 'load'. (CMD-041)Information: Defining new variable 'reset_pin_name'. (CMD-041)Information: Defining new variable 'clock_pin_name'. (CMD-041)1pt_shell>

22


WAVEFORM

23


TRADE- OFFS

1. There is trade - off between total power and the frequency of clock, if you increase the frequency of clock, total power dissipation also increases.2. There is a trade off between the width of the nmos to that of Energy Delay product (EDP). The width of the nmos is very high in order to achieve minimum Energy Delay product (EDP). Hence optimum value of the width was chosen.3. In the D-flip flop design; there is trade off between height and width of DFF to that of number of M2 used in designing the layout. M2 count increases as you reduce the height. Hence a reasonable height is chosen.

FINAL DATA

Sr No. Parameters Values1 Area of overall System 0.28 x 10-6 m2

2 Cell count without fillers 4531

3 Frequency of Clock 1.5 GHz

4 Total power 1.525mW

5 Number of operations 15

CONCLUSION

Considering the number of operation our ALU can perform, the designed ALU has very low total power. In addition to that our system works on 1.5GHz frequency, which is very efficient.

24