1 adf4193 low phase noise, fast settling pll frequency synthesizer
TRANSCRIPT
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ADF4193
Low Phase Noise, Fast Settling PLL Frequency Synthesizer
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BASED ON
A 10s Fast Switching PLL Synthesizer for a GSM/EDGE
Base-Station
ByMike Keaveney, Patrick Walsh,
Mike Tuthill, Colin Lyden, Bill Hunt
ISSCC 2004 / SESSION 10 / CELLULAR SYSTEMS AND BUILDING BLOCKS / 10.6
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FUNCTIONAL BLOCK DIAGRAM
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50Ω
52Ω
No connection here
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FEATURES• New fast settling fractional-N PLL architecture• Single PLL replaces ping-pong synthesizers• 0.5 degree RMS phase error at 2 GHz RF output• Digitally programmable output phase• RF input range up to 3.5 GHz• 3-wire serial interface• On-chip low noise differential amplifier• Phase noise figure of merit –216 dBc/Hz• Loop filter design possible using ADI SimPLL
APPLICATIONS• GSM/EDGE base stations• PHS base stations• Instrumentation and test equipment
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Background – GSM Base-station Synthesizer Requirements
• Switch frequency in 10s => Wide PLL BW
• Low Phase Noise during Data Burst• Low Spurious during Data Burst } => Narrow PLL BW
547s30s
Tx @ f2Tx @ f1 Tx @ f3
PA o/p power
~10s for Tx Synth. to switch
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Phase Noise & Lock Time Simulations
320kHz BW:Lock Time: 6.3s
5 s/div.
1805
1880
0 5 10 15-50
0
50
40kHz Loop BW:Lock Time: 120s
No cycle slip ifBW>0.8*Fstep/2N[Cicero JSSC’00]
Ph
ase
(Deg
.)F
req
ue
ncy
(M
Hz)
50 s/div.
0 50 100 150-50
0
50
1805
1880
Ph
ase
No
ise
(d
Bc
/Hz)
1kHz 1MHz
-140
-100
N=1880/1040.8*75M/(2N)=528k
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8x Bandwidth Switching
NF(s)IK CPV
..
2Gain Loop
Wide BW: 64x ICP & R/8Narrow BW: 1x ICP & R
0dB
36dB
-180o
-135o
8f0f0
[Ref: Crowley ‘78]
64x ICP
1x ICP
N
Charge Pump Cell Array,ICP<63..0>
CP
CZ
R/8
7R/8
FoutPFD
Fref sKV
PLL Static Phase Error
At Balance: ICP = ICP
5º @ 1.85GHz 7.5ps ( 0.065º @ 26MHz)
With = 3ns, for < 7.5ps, requires ICP mismatch < 0.25%
Charge Balance:
Fref
Fdiv
Matched
UPDOWN
Mismatched
ICP ICP +ICP
-ICP
10
64x → 1x ICP
mismatch = 10%
= 200°
IdealTime (5s / div.)
ICP Envelope
Conventional Charge Pump PLL
1x0 64x
N
PFD
ICP<63..0>UP
DN
200°/div.
0
Output Phase (simulation)
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Differential Charge Pump Concept• Better Up/Down Matching
– Same Type Devices
– Symmetric Layout
• Charge Injection is Common Mode to Vtune
• Requires– Low Noise Diff-amp
– CMFB
• Matching improved but still residual mismatch due to process ( ~= 0.5%)
Vbias2
DNn
UPp
Vbias1
UPn
DNp
CPO+ CPO–
Vtune
+ –
mp1 mp2
mn1 mn2
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Charge Pump Cell with Chopped Outputs
Vbias1
UPp1
mp1
DNp2 DNp1
mp2
UPp2
Vbias2
DNn1
mn1
UPn2 UPn1
mn2
DNn2
CPO+ CPOB–~2V ~2V
5V
Fref
UP1,DN1UP2,DN2
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Chopped Up/Down Signal Paths from PFD
Chopped Output Charge
Fref
Fdiv
D QRB
D QRB
UP1, DN2
DN1, UP2
Fref
Fdiv
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Diff-Amp
• PLL suppresses DC errors & 1/f noise.
• Want zero IIN mismatch MOS i/p’s
• Noise > 40kHz → FM sidebands < 7nV/Hz required @ Vout
-130
-100
Phase Noise
40kHz
CPO –
CPO +Vref
Vout
5mA5mA
10000.5
500 500
500 500
–+
10000.5
• Pulse Stretch circuit → Fast leading edge, current controlled trailing edge → Control current mirrored to both up and down pulses.
Common Mode Feedback Loop
UP
DN
CPO+
CPO–
UPpDNp
UPnDNn
UPDN
+–
+–~2V
200A
ChargePump
+
_PFD
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UPDN
UPpDNp
} from PFD
UPnDNn
CMFB Pulse Stretch Signals
} to PMOS switches
} to NMOS switches
Differential CP output
Common Mode output
Phase info from PFD remains intact
Proposed Fast Locking PLL
Fref
FoutD
D
ChargePump<64:1>
Mod-130
2C1
R2/16
2C2
7R2/16
2C1
R2/16
2C2
7R2/16
÷ N / N+1
Fast LockControl
–+
C3
R3
External
External
+
–
R3/7
Open R2 & R3 switches when ICP is @ 1x
ICP Reduction with Compensation
MUX10
X2
Z-1
2
+
FRAC Out
X2
+–+
1
+1
3
3
130
16
0
X2
ICP
(mA)
Fref
17 18Time (µs)
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Measured: Phase Lock Time
75 MHz jump from 1880 to 1805 MHz
Time (s)
Pha
se (
De
gre
es)
-25
-15
-5
5
15
25
-10 10 30 50 70 90 110 130 150
Start
Chopping Off vs. Chopping On
Measured:~1% ICP mismatch change 20° phase step w/o chopping
-40
-20
0
20
40
-10 10 30 50 70 90
Time (s)
WideBW
NarrowBW
Pha
se (
De
gre
es) Chopping Off
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Fout = 1860MHz, Fref = 26MHz, Chopping @ Fref/2External VCO (Vari-L 1843T)
Measured: Output Phase Noise
DCS-1800 Tx LO Mask
dBc/
Hz
RMS Phase Error (SSB) = 0.25°
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Chopping @ Fref/2, (with 2% measured ICP mismatch)
Measured: Spur Side-Band Levels
Fout = 1872.4 MHz (N = 72 2/130)
-100
-80
-60
-40
-20
0
1872 1877 1882 1887
Frequency (MHz)
dBc
Integer Boundary Spurs:-75dBc @ f = +/- 400kHz
Chopping:<-95dBc @ f = 13MHz
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Die Photo
ChargePumpArray
Modulator
N
PFD
SerialInterface
Tim
ers
&C
ontr
ol
Diff-Amp
CMFB
BGR
R
LockDetect Loop
FilterSwitches
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Lock Time 10 s
RMS Phase Error 0.25 deg.
Idd: Charge Pump (5V) 33 mA
Diff-amp (5V) 30 mA
Remainder of chip (3V) 20 mA
Fractional Spurs (worse case at integer boundaries):
-75 dBc @ 400kHz
-85 dBc @ 600kHz
Spur due to Chopping @ Fref/2:
Reference Spur:
< -95 dBc @ 13MHz
< -95 dBc @ 26MHz
Chip Size 2.29 x 2.32 mm
Technology 0.35 BiCMOS w/ 5V options
Package 5x5mm 32 lead LFCSP
Performance Summary
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Summary• Static Phase Error due to Up to Down Mismatch
in the PFD and Charge Pump blocks can be eliminated using a chopping scheme.
• Loop Gain Changes during BW switching can be digitally compensated for in the Modulator.
• A PLL based synthesizer can jump over the full TX band in <10s and still meet the phase noise and spurious requirements for a GSM and EDGE base-station.