A Fast-Hopping Single-PLL 3-Band MB-OFDM UWB Synthesizer

Remco C. H. van de Beek, Member, IEEE, Domine M. W. Leenaerts, Fellow, IEEE, and

Gerard van der Weide

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Presented by Romi Fan

AbstractAbstract

• A 3-band (mode 1) multiband-OFDM UWB synthesizer implemented in a 0.25-um SiGe BiCMOS process.

• Crucial in the design is a divide-by-5 frequency divider that generates quadrature signals at a frequency of 528 MHz .

• The 0.44 mm2 fully integrated synthesizer consumes 52mW from a 2.7 V supply. Out-of-band spurious tones are below 50 dBc .

• The measured frequency transition time is well below the required 9.5 ns.

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OFDM : Orthogonal Frequency Division Multiplexing

Outline

IntroductionIntroductionThe single-PLL ArchitectureThe single-PLL Architecture

◦A.Divide-by-1.5A.Divide-by-1.5◦B.Divide-by-5B.Divide-by-5

MeasurementsVCO DesignVCO DesignConclusion

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LTCC 　 Low-Temperature Cofired Ceramics SAW Surface Acoustic Wave ISM Industrial Scientific Medical U-NII Unlicensed National Information InfrastructureUWB UltraWideBand BPF Bandpass Filter

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f(t)=A Bcosωtcos(ωt+θ)

IntroductionIntroduction

• UWB is now becoming an industrial standard in the 3–10 GHz frequency range under IEEE802.15.3a (WPAN) .

• The multi-band OFDM alliance (MBOA) proposal divides the spectrum into 14 channels (bands) with a spacing of 528 MHz [1], [2] (see Fig. 1), using quadrature phase shift keying (QPSK)-OFDM, where high data rates of up to 480 Mb/s are achieved .

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IntroductionIntroduction

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IntroductionIntroductionTo allow co-existence with WLAN applications

operating in 2.4 GHz ISM (e.g., IEEE 802.11b/g and Bluetooth) and 5 GHz ISM (e.g., IEEE 802.11a), spurious tones in or near these frequency ranges should be below 45 dBc and 50 dBc, respectively, to avoid harmful down-conversion of strong out-of-band interferers into the wanted bands. In-band spurious tones should be below 30 dBc to allow co-existence with other UWB systems.

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IntroductionIntroduction[5] D. Leenaerts et al.,“A SiGe BiCMOS 1 ns fast hopping frequency

synthesizer for UWB radio,” in IEEE ISSCC Dig. Tech. Papers, 2005,pp. 202–203.PLL&BiCmos performance

[6] C.-C. Lin and C.-K. Wang,“A regenerative semi-dynamic frequency divider for mode-1 MB-OFDM UWB hopping carrier generation,” in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 206–207.Dividers

[7] A. Ismail and A. Abidi,“A 3.1 to 8.2 GHz direct conversion receiver for MB-OFDM UWB communication,” in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 208–209.BiCmos performance

[8] B. Razavi et al.,“A 0.13umCMOS UWBtransceiver,” in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 216–217.

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Introduction Ref[5]Introduction Ref[5]

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Introduction Ref[6]Introduction Ref[6]

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Introduction Ref[7]Introduction Ref[7]

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Introduction Ref[8]Introduction Ref[8]

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Introduction Introduction

• Miller dividerTai-Cheng Lee and Yen-Chuang Huang,“A Miller Divider Based Clock Generator for MBOA-UWB Application,” in Symposium on VLSI Circuits Digest of Technical Papers, 2005, pp. 34–37.

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The single-PLL ArchitectureThe single-PLL Architecture

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The single-PLL ArchitectureThe single-PLL ArchitectureA.Divide-by-1.5A.Divide-by-1.5

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The single-PLL ArchitectureThe single-PLL ArchitectureB.Divide-by-5B.Divide-by-5

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The single-PLL ArchitectureThe single-PLL ArchitectureB.Divide-by-5B.Divide-by-5

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The single-PLL ArchitectureThe single-PLL ArchitectureB.Divide-by-5B.Divide-by-5

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The single-PLL ArchitectureThe single-PLL ArchitectureB.Divide-by-5B.Divide-by-5

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VCO DesignVCO Design

• The 7920 MHz LC-oscillator uses an on-chip inductor for low phase noise and power dissipation. The 0.6 nH single-turn differential inductor is realized using the 3 um-thick top metal layer on a deep trench isolation g rid.

• The VCO consumes 4.8 mA from a 2V on-chip supply regulator. The measured VCO phase noise is -97 dBc/Hz at an offset frequency of 1 MHz.

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VCO DesignVCO Design

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LCfc 2

1

Measurements• The synthesizer has been implemented in a 0.25-um

SiGe BiCMOS process with an NPN ft of 70 GHz.

• The synthesizer (excluding the 1.056 GHz clock generator and the 50 Ω measurement buffers) draws 19.3 mA from a 2.7 V supply (52 mW).

• The close-in phase noise is below 90 dBc/Hz and the VCO phase noise is below 120 dBc/Hz at 10 MHz offset.

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Measurements

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Measurements

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Measurements

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Conclusion

The 52 mW power dissipation is better than other reported BiCMOS solutions and is close to the 45 mW reported for the CMOS concept in [8](105mW).

The spurious tones performance of the proposed divide-by-7.5 is better than the one reported in [6] where levels of -20 dBc were reported. The complete design enables co-operability with WLAN/WPAN applications in the 2.4 GHz and 5 GHz frequency bands.

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IMD-1

Via-1

Metal-1

ILD

Contact

N & PWell

Gate&Gox

Plug-2

Metal-2

NMOSPMOS

I/OPMOS Resistor

CorePMOS

CoreNMOS

CapacitorI/O

NMOS

STI

Plug-1

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Thanks for your attention.