dual pll frequency synthesizer with on-chip · pdf filedual pll frequency synthesizer with...

Parameter MB15U36

RF frequency of operation, max. 2.0 GHz

IF/RF frequency of operation, max 1.2 GHz

Low power supply voltage 3 - 5.5V

Low power supply current 6.0 mA @ 3V

Prescaler divide ratios RF1, RF2 = 64/65 or 128/129

Power-saving function 10µA typical

MB15U36Dual PLL Frequency Synthesizerwith On-Chip Prescaler

Packages

• 18-bit programmable divider:– Binary 7-bit swallow counter: 0 to 127– Binary 11-bit programmable counter: 3 to 2047

• Software selectable charge pump current:– Do output ±1.0 or ±4.0 mA @ VCC = 3V

• Evaluation Kits available

DescriptionThe Fujitsu MB15U36 dual PLL is a serial input frequencysynthesizer with 2.0 GHz and 1.2 GHz prescalers.Theprescalers both have a selectable dual modulus division ratioof 64/65 or 128/129 enabling pulse swallow operation. TheMB15U36 utilizes a refined charge pump design (Fujitsu’sSuper Charger)that provides fast tuning along with lowspurious noise and phase noise characteristics. The MB15U36is ideally suited for digital mobile communications, includingGSM, DCS1800, PCS1900, IS-136, IS-95 and ISM-bandapplications.

Features• Very low spurious and phase noise characteristics

• Wide operating voltage: 3.0 to 5.5 volts

• Low operating current: 6.0 mA @ VCC = 3 volts (typical)

• Power-saving current: 10µA (typical)

• Wide operating temperature: –40 to +85°C

• Plastic 20-pin SSOP package

• Reference counter:– 15-bit programmable divider: 3 to 32767

20-pin plastic SSOP,FPT-20P-M03

MB15U36

Fujitsu Microelectronics, Inc. 3

Table of ContentsPin Descriptions: MB15U36 ................................................................................................................................................... 4

Block Diagram: MB15U36 ..................................................................................................................................................... 5

Absolute Maximum Ratings .................................................................................................................................................... 6

Recommended Operating Conditions........................................................................................................................................ 6

Handling Precautions...................................................................................................................................................... 6

Electrical Characteristics ........................................................................................................................................................ 7

Measurement Circuit (fin, OSCIN Input Sensitivity) .................................................................................................................... 9

Typical Electrical Characteristics ........................................................................................................................................... 10

Reference Information ................................................................................................................................................... 13

Functional Descriptions ....................................................................................................................................................... 14

Serial Data Input .......................................................................................................................................................... 14

Table 1: Control Bits ..................................................................................................................................................... 14Shift Register Configuration for the Programmable Reference Counter .......................................................................... 14Shift Register Configuration for the Programmable Counter ........................................................................................ 15

Table 2: Binary 14-bit Programmable Reference Counter Data Setting................................................................................. 15Table 3: Phase Comparator Phase Switching Data Setting.................................................................................................. 15Table 4: Charge Pump Current Setting ............................................................................................................................ 16

Table 5: Charge Pump Output Impedance Setting ............................................................................................................. 16Table 6: LD/fOUT Output Select Data Setting.................................................................................................................... 16Table 7: Binary 11-bit Programmable Counter Data Setting............................................................................................... 16

Table 8: Binary 7-bit Swallow Counter Data Setting ......................................................................................................... 17Table 9: Prescaler Data Setting ...................................................................................................................................... 17

Power Saving Mode (Intermittent Mode Control Circuit) ........................................................................................................ 17

Table 10: Power Save Internal Shutdown Logic.................................................................................................................. 17

Serial Data Input Timing ..................................................................................................................................................... 18

Table 11: Timing Parameters.......................................................................................................................................... 18

Power-ON Timing Diagram ........................................................................................................................................... 18

Phase Detector Output Waveform .......................................................................................................................................... 19

Application Example ........................................................................................................................................................... 20

Application Example: Fastlock Mode ..................................................................................................................................... 21

Ordering Information .......................................................................................................................................................... 22

Package Dimensions ........................................................................................................................................................... 23

Dual PLL Frequency Synthesizer with On-Chip Prescaler

4 Fujitsu Microelectronics, Inc.

Pin Descriptions: MB15U36Pin No.

Pin Name I/O DescriptionsSSOP

1 Vcc1 – Power supply voltage input pin for the RF1-PLL section, the shift register, and the oscillator input buffer. When poweris OFF, latched datafor RF1-PLL is lost.

2 Vp1 I Power supply for the RF1-PLL charge pump. (Independent of pin 19)

3 Do1 O Charge pump output for the RF1-PLL section. Phase detector characteristics can be reversed using the FC-bit.

4 GND1 – Ground for the RF1-PLL section.

5 fin1 I Prescaler input for the RF1-PLL. Connection to an external VCO should be via AC coupling.

6 Xfin1 I Prescaler complimentary input for the RF1-PLL section. This pin should be grounded via a small capacitor.


8 OSCIN I External TCXO reference oscillator input or connection to crystal. TCXO should be connected via AC coupling.

9 OSCOUT O Oscillator output or connection to crystal.

10 LD/fOUT O Lock detect signal output (LD) or phase comparator monitoring output (fout). The output signal is selected by the LDS and FDS bits in theserial programming data.

11 Clock I Clock input for the 22-bit shift register. One bit of data is shifted into the shift register on a rising edge of the clock.

12 Data I Serial data input. Data is transferred to the corresponding latch (RF1-ref counter, RF1-prog. counter, RF2-ref. counter, RF2-prog. counter)according to the control bits settings in the serial programming data.

13 LE I Load enable signal input. When the LE bit is set to “H”, data in the shift register is transferred to the corresponding latch ac cording to thecontrol bits settings in the serial programming data.


15 Xfin2 I Prescaler complimentary input for the RF2-PLL section. This pin should be grounded via a small capacitor.

16 fin2 I Prescaler input for the RF2-PLL. Connection to an external VCO should be via AC coupling.


18 Do2 O Charge pump output for the RF2-PLL section. Phase detector characteristics can be reversed using the FC-bit.

19 Vp2 I Power supply for the RF2-PLL charge pump. (Independent of pin 2)

20 Vcc2 – Power supply voltage input pin for the RF2-PLL section. When power is OFF, latched data for RF2-PLL is lost.

(FPT-20P-M03)

Vcc1

Vp1

Do1

GND1

fin1

Xfin1

GND1

OSCIN LE

Data

Clock

18

17

16

15

14

13

12

11

1

2

3

4

5

6

7

8

TOPVIEW

9

10

20

19

OSCOUT

LD/fOUT

GND2

fin2

Xfin2

GND2

Do2

Vcc2

Vp2

MB15U36


Block Diagram: MB15U36

11Clock

12Data

13LE

6Xfin1

fin1

OSCIN

fin2

2-bit latch 7-bit latch 11-bit latch

2-bit latch

Latch selector

22-bit shift register

7-bit latch 11-bit latch

Phasecomp.

(RF2-PLL)

Lock Detect(RF2-PLL)

Lock Detect(RF1-PLL)

Charge pump(RF2-PLL)

Phasecomp.

(RF1-PLL)

Charge pump(RF1-PLL)

5-bit latch 15-bit latch

Binary 7-bitswallow counter

(RF2-PLL)

Binary 15-bitprogrammable ref.counter (RF2-PLL)

Binary 11-bitprogrammable

counter (RF2-PLL)

Binary 7-bitswallow counter

(RF1-PLL)

Binary 11-bitprogrammable

counter (RF1-PLL)

Prescaler(RF2-PLL)

64/65, 128/129

Prescaler(RF1-PLL)

64/65, 128/129

PSSW

VCC2 GND2

20 14

fpRF218 Do2

LDRF2

Selector

3 Do1

OR10 LD/fout

fpRF1

frRF1

CN1

CN2

frRF2

frRF1

fpRF2

fpRF1

Vcc1 GND2

16

8

1 4

FC CMC ZC LDS FDS

15-bit latch

Binary 15-bitprogrammable ref.

counter (RF1-PLL)

5-bit latch

FC CMC ZC LDS FDS

LDRF2

LDRF1

PSSW

9

5

17

LDRF1

7

frRF2

OSCOUT

2

Vp1

19

Vp2

Xfin2 15



Absolute Maximum Ratings

WARNING: Semiconductor devices can be permanently damaged by the application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceedthese ratings.

Recommended Operating Conditions

*1: Prescaler divide ratio is only 64/65 (SW = “L”) at RF1.

WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device’s electrical characteristics are warranted when operated within theseranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affec t reliability and could result in devicefailure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditionsare advised to contact their Fujitsu representative beforehand.

Handling Precautions• This device should be transported and stored in anti-static containers

• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded.Cover workbenches with grounded conductive mats.

• Always turn the power supply off before inserting or removing the device from its socket.

• Protect leads with a conductive sheet when handling or transporting PC boards with devices.

Parameter Symbol Rating Unit Note

Power supply voltageVcc1,2 –0.5 to +6.5 V

Vp1,2 –0.5 to +6.5 V

Input voltage VI –0.5 to +6.5 V

Output voltage VO –0.5 to +6.5 V

Storage temperature TSTG –55 to +125 °C

Parameter SymbolValue

Unit NoteMin. Typ. Max.

Power supply voltageVcc 3.0 5.0 5.5 V Vcc1 = Vcc2

Vp 3.0 5.0 5.5 V Vcc1 = Vcc2 *1

Input voltage VI GND – VCC V

Operating temperature Ta –40 – +85 °C

MB15U36


Electrical Characteristics

(VCC =3.0 to 5.5V,Ta = –40 to +85°C)

Parameter Symbol ConditionValue

UnitMin. Typ. Max.

Power supply current

Icc1*1 fin1 = 2000 MHzfosc = 12 MHz

Vcc = 5V – 6.0 – mA

Vcc = 3V – 3.5 – mA

Icc2*2 fin2 = 1200 MHzfosc = 12 MHz

Vcc = 5V – 3.0 – mA

Vcc = 3V – 2.5 – mA

Power saving currentIps1 Vcc1 current at PS bitRF1, RF2 =“H” – 0.1*3 10 µA

Ips2 Vcc1 current at PS bit RF2 =“H” – 0.1*3 10 µA

Operating frequency fin1*4 RF1-PLL 100 – 2000 MHz

fin2*4 RF2-PLL 50 – 1200 MHz

fOSC 500mVp-p minimm 3 – 40 MHz

Input sensitivity

fin RF1-PLL PfinRF1- PLL50Ω load system(Refer to measurement circuit.)

–10 – +2 dBm

finRF2-PLL PfinRF2-PLL50Ω load system(Refer to measurement circuit.)

–10 – +2 dBm

OSCIN VOSC 0.5 – VCC Vp-p

Input voltageData, Clock,LE

VIH VCC × 0.8 – –V

VIL – – VCC × 0.2

Input current

Data, Clock,LE

IIH*5 VIH = Vcc –1.0 – +1.0µA

IIL*5 VIL = Vcc –1.0 – +1.0

OSCIN

IIH VIH = Vcc 0 – +100µA

IIL*5 VIL = Vcc –100 – 0

Output voltageLD/fOUT

VOH IOH = –1 mA Vcc –0.4 – –V

VOL IOL = 1 mA – – 0.4

Do1, Do2VDOH IOH = –0.5 mA Vcc –0.4 – –

VVDOL IOL = 0 .5 mA – – 0.4

High impedance cutoffcurrent

Do1, Do2 IOFFVCC = Vp = 5.0V0.5V ≤ VDO ≤ Vp – 0.5V

– – 3.0 nA

Output current

LD/fOUTIOH*5 VCC = 5.0V –1.0 – – mA

IOL VCC = 5.0V – – 1.0 mA

Do1, Do2

IDOH*5VCC = Vp = 5.0V CMC bit = “L” – –1.25 – mA

VCC = Vp = 3.0V CMC bit = “L” – –1.0 – mA

IDOLVCC = Vp = 5.0V CMC bit = “L” – 1.25 – mA

VCC = Vp = 3.0V CMC bit = “L” – 1.0 – mA

IDOH*5 VCC = Vp = 5.0V CMC bit = “H” – –5.0 – mA

VCC = Vp = 3.0V CMC bit = “H” – –4.0 – mA

IDOL VCC = Vp = 5.0V CMC bit = “H” – 5.0 – mA

VCC = 3.0V CMC bit = “H” – 4.0 – mA



*1: Conditions: Vcc1 = 5.0V, Ta = +25°C, in locking state.*2: Conditions: Vcc2 = 5.0V, Ta = +25°C, in locking state.*3: Conditions: Vcc = 5.0V, fOSC = 12.8MHz (-2dBm),Ta = +25°C*4: AC coupling, 1000pF capacitor is connected under the condition of min. operating frequency.*5: The symbol “–” (minus) means direction of current flow.*6: VCC = 5.0 V, Ta = +25°C (|I3| – |I4|)/[(|I3| + |I4|)/2] X 100(%)*7: VCC = 5.0 V, Ta = +25°C [(|I2| – |I1|)/2]/[(|I1| + |I2|)/2] X 100(%) (Applied to each IDOL, IDOH)*8: VCC = 5.0 V, [|IDO(85°C) – IDO(–40°C)|/2]/[|IDO(85°C) + IDO(–40°C)|/2] X 100(%) (Applied to each IDOL, IDOH)

Charge pump currentcharacteristics

IDOL/IDOH IDOMT*6 VDO = VCC/2 – 3 – %

IDO vs VDO IDOVD*7 0.5V ≤ VDO ≤ VCC – 0.5V – 15 – %

IDO vs Ta IDOTA*8 –40×C ≤ Ta ≤ +85°C,VDO = Vp/2 – 10 – %

Parameter Symbol ConditionValue

UnitMin. Typ. Max.

I1

I1

I3I2

I2 I4

IDOL

IDOH

0.5 Vcc/2 VccVcc − 0.5 V

Charge Pump Output Voltage (V)

MB15U36


Measurement Circuit (For Measuring Input Sensitivity of fin and OSCin)

1000 pF

1000 pF

From Controller

OSCIN Xfin1

9 8 7 6 5 4 3 2

12 13 14 15 16 17 18 19

fin1OSCOUT GND1 GND1 Do1 Vp1

1000 pF

LE Xfin2 fin2Data GND2 GND2 Do2 Vp2

MB15U36

1

20

10

11

Vcc1LD/fOUT

Clock Vcc2

.1 µF .1 µF

.1 µF.1 µF

Oscilloscope

1000 pF

Sig. Gen.

Sig. Gen.

1000 pFSig. Gen.

50

50 Ω

Ω

Ω50

fOUT



Typical Electrical Characteristics: MB15U36

VfinRF2 VS. finRF2

-50

-40

-30

-20

-10

0

10

0 500 1000 1500 2000

finRF2 [MHz]

Vfin

RF

2[d

Bm

]

Vfin[dBm]@5.5VVfin[dBm]@5.0VVfin[dBm]@4.5VVfin[dBm]@3.0V

VfinRF1 VS. finRF1

-50

-40

-30

-20

-10

0

10

0 500 1000 1500 2000 2500 3000

finRF1 [MHz]

Vfin

RF

1[d

Bm

]

Vfin[dBm]@5.5V

Vfin[dBm]@5.0V

Vfin[dBm]@4.5VVfin[dBm]@3.0V

Input Sensivity of fin (RF1) versus Input Frequency

Input Sensivity of OSCIN versus Input Frequency

Input Sensivity of fin (RF2) versus Input Frequency

PfinRF1 vs. finRF1

Pfin

RF

1(d

Bm

)

P fin (dBm )@ 5.5VPfin(dBm)@5.0VPfin(dBm)@4.5VPfin(dBm)@3.0V

Pfin(dBm )@ 5.5VPfin(dBm)@5.0VPfin(dBm)@4.5VPfin(dBm)@3.0V

SPEC

SPEC

finRF1 (MHz)

PfinRF2 vs. finRF2

Pfin

RF

2(d

Bm

)

finRF2 (MHz)

Vfosc VS. fosc

-50

-40

-30

-20

-10

0

10

0 50 100 150 200 250

fosc [MHz]

VO

SC

[dB

m]

VOSCin[dBm]@5.5V

VOSCin[dBm]@5.0VVOSCin[dBm]@4.5VVOSCin[dBm]@3.0V

S P E C

P O S C(dBm )@ 5.5VPO SC(dBm)@5.0VPO SC(dBm)@4.5VPO SC(dBm)@3.0V

PfinOSC vs. finRF2

Pfin

OS

C(d

Bm

)

MB15U36


Typical Electrical Characteristics: MB15U36Conditions: Ta = +25°C

Do output current: 1 x Do mode

IDOL VS. VDOL

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

0 0.5 1 1.5 2 2.5 3

Vcc=5V

Vcc=3V

“L” level output voltage o— Í“ d— ¬IDOL(mA)

“L”

leve

lout

putv

olta

geV

DO

L(V

IDOH VS. VDOH

0

1

2

3

4

5

6

7

8

-3-2.5-2-1.5-1-0.50

Vcc=5V

Vcc=3V

“H” level output voltage IDOH (mA)

“H”

leve

lout

putv

olta

geV

DO

H(V

“H”l

evel

outp

utvo

ltage

V DOH

(V)

“H” level output current IDOH (mA)

IDOH - VDOH

“L”l

evel

outp

utvo

ltage

V DOL

(V)

“L” level output current IDOL (mA)

IDOL - VDOL



Typical Electrical Characteristics: MB15U36Conditions: Ta = +25°C

Do output current: 4 x Do mode

IDOH VS. VDOH

0

1

2

3

4

5

6

7

8

-8-7-6-5-4-3-2-10

Vcc=5V

Vcc=3V

“H” level output voltage IDOH (mA)

"H”

leve

lout

putv

olta

geV

DO

H(V

IDOL VS. VDOL

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

0 1 2 3 4 5 6 7 8

Vcc=5V

Vcc=3V

“L” level output voltage IDOL (mA)

“L”

leve

lout

putv

olta

geV

DO

L(V

“H”l

evel

outp

utvo

ltage

V DOH

(V)

“H” level output current IDOH (mA)

IDOH - VDOH

“L”l

evel

outp

utvo

ltage

V DOL

(V)

“L” level output current IDOL (mA)

IDOL - VDOL

MB15U36


Reference Information: MB15U36

(1760.000 MHz → 1800.000 MHz, within ± 1kHz)

Typical plots measure with the test circuit are shown below. Each plot shows lock up time, phase noise, and reference leakage.

-80.3 dBc

RF PLL Lock Up Time = 387µs(1800.000 MHz → 1760.000 MHz, within ± 1kHz)

RF PLL Lock Up Time = 442µs

RF PLL Phase Noise@ max within loop band = -66.5 dBc/Hz

RF PLL Reference Leakage@ 200 kHz offset = -80.3 dBc

S G

Spect rumAnalyzer

OSC IN

fin Do LPF

V C O

Test Circuit fV C O = 1780 MHzK V = 58 MHz/Vfr = 200 KHzfO S C = 10 MHz

V C C = VP = 3.0VV V C O = 5.0VTa = +25 °CCP: 1mA mode

3.3KΩ

6800Ω

6800pF

150pF750pF

LPF



Functional DescriptionsThe VCO output frequency can be calculated using the following equation:

fVCO = (M x N) + A x fOSC ÷ R (A < N)

fVCO: Output frequency of external voltage controlled oscillator (VCO)M: Preset divide ratio of dual modulus prescaler (64 or 128 for RF1-PLL or RF2-PLL2)N: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)A: Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)fOSC: Reference oscillation frequencyR: Preset divide ratio of binary 14-bit programmable reference counter (3 to 32,767)

Serial Data InputSerial data is entered using the Data, Clock, and LE pins. The serial data controls the programmable reference counters and the programmablecounters separately.

Binary serial data is entered through the Data pin when the LE pin is held low. One bit of data is shifted into the shift register on the risingedge of the Clock. When the LE signal pin is taken high, entered data is latched into the appropriate counters according to the control bitsettings as follows:

Table 1. Control Bits

Shift Register Configuration

Control BitsDestination of Serial Data

CN1 CN2

L L The programmable reference counter for the RF2-PLL

L H The programmable reference counter for the RF1-PLL

H L The programmable counter and the swallow counter for the RF2-PLL

H H The programmable counter and the swallow counter for the RF1-PLL

Programmable Reference Counter

CNT1, 2 Control bits [Table 1]R1 to R15 Divide ratio setting bits for the programmable reference counter (3 to 32,767) [Table 2]FC Phase control bit for the phase detector [Table 3]CMC Charge pump current select bit [Table 4]ZC Forced high impedance control for the charge pump [Table 5]LDS/FDS LD/fOUT signal select bits [Table 6]

Note: Input Data with MSB first.

CN1

1 2

R1

3

R3

4

R4

5

R5

6

R6

7

R7

8

R8

9

R9

10

R10

11

R11

12

R12

13

R13

14

R14

15

R15

16

FC

17

LSB MSBData Flow

CN2

R2

18

C Z

19

L

20

F

21 22

MC

C DS

DS

MB15U36


Functional Descriptions

Table 2. Binary 15-bit Programmable Reference Counter Data Setting

Note: Divide ratio less than 3 is prohibited.

Table 3. Phase Comparator Phase Switching Data Setting

Notes: 1) Z = High-impedance2) The FC bit should be set depending upon the VCO and LPF polarity

DivideRatio(R)

R15

R14

R13

R12

R11

R10

R9

R8

R7

R6

R5

R4

R3

R2

R1

3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

4 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

. . . . . . . . . . . . . . . .

32767 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

DoRF1-PLL,RF2-PLL

FCRF1-PLL,RF2-PLL = “H” FCRF1-PLL,RF2-PLL = “L”

fr > fp H L

fr = fp Z Z

fr < fp L H

VCO polarity (1) (2)

CNT1, 2 Control bits [Table 1]N1 to N11 Divide ratio setting bits for the programmable counter (3 to 2,047) [Table 7]A1 to A7 Divide ratio setting bits for the swallow counter (0 to 127) [Table 8]SW Divide ratio setting bit for the prescalers [Table 9]

(64/65 or 128/129 for the RF1-PLL and RF2-PLL)PS Power saving mode control bit [Table 10]Note: Input Data with MSB first.

Programmable Counter

C

N

1

1 2 3 4

A

1

5

A

2

6

A

3

7

A

4

8

A

5

9

A

6

10

A

7

11

N

1

12

N

2

13

N

3

14

N

4

15

N

5

16

N

6

17

LSB MSBData Flow

C

N

2

18

N

7

N

8

19

N

9

20

N

10

21

N

11

22

S

W

P

S

VCO input voltage

VCO outputfrequency

(1)

(2)




Table 4. Charge Pump Current Setting (CMC)

Table 5. Charge Pump Output Impedance Setting (ZC)

Table 6. LD/fout Output Select Data Setting

Note: X = Don’t care

Table 7. Binary 11-bit Programmable Counter Data Setting

Note: Divide ratio less than 3 is prohibited.

CMC Current Value

L 1 x Do

H 4 x Do

ZC Do Output Impedance

L Normal output

H High impedance

LDSRF1 LDSRF2 FDSRF1 FDSRF2 LD/fOUT Output Signal

L L L L Disabled

L H L L LD signal (RF2 lock detect)

H L L L LD signal (RF1 lock detect)

H H L L LD signal (RF1/RF2 lock detect)

X L L H fOUT (Output frRF2)

X L H L fOUT (Output frRF1)

X H L H fOUT (Output fpRF2)

X H H L fOUT (Output fpRF2)

L L H H Fastlock

L H H H RF2 counter reset

H L H H RF1 counter reset

H H H H RF1/RF2 counter reset

DivideRatio(N)

N11

N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

3 0 0 0 0 0 0 0 0 0 1 1

4 0 0 0 0 0 0 0 0 1 0 0

. . . . . . . . . . . .

2047 1 1 1 1 1 1 1 1 1 1 1

MB15U36



Table 8. Binary 7-bit Swallow Counter Data Setting

Note: Divide ratio (A) range = 0 to 127

Table 9. Prescaler Data Setting (SW)

Power-Saving Mode (Intermittent Mode Control)• The intermittent mode control circuit greatly reduces the PLL power consumption by shuting down various internal functions, as

shown in Table 10, depending upon the settings of the power save (PS) bits. Setting the PS bits to “H” enters the corresponding PLLinto the power-saving mode. See the Electrical Characteristics chart for the specific value of current when in the power-saving mode.

• The phase detector output, Do, becomes high impedance.• Serial data can be entered while in the power-saving mode.• Setting the PS pins “L” releases the power-saving mode, returning the selected PLL to normal operation.

Note: When power (VCC) is first applied, the device must be in standby mode, PS = High, for at least 1µs.

Table 10. Power Save Internal Shutdown Logic (PS)

DivideRatio(A)

A7

A6

A5

A4

A3

A2

A1

0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 1

. . . . . . . .

127 1 1 1 1 1 1 1

PrescalerDivide Ratio

SW = “L” SW = “H”

RF1-PLL 64/65 128/129

RF2-PLL 64/65 128/129

PSRF2 PSRF1 RF2-PLL Counters RF1-PLL Counters OSC Input Buffer

H H OFF OFF OFF

L H ON OFF ON

H L OFF ON ON

L L ON ON ON



Serial Data Input Timing

LSBMSB

1st data 2nd data

Control bit Invalid data

Clock

Data

LE

t7

t1 t2 t3

t4 t5

t6

Table 11. Timing Parameters

Notes: 1) On the rising edge of the clock, one bit of the data is transferred into the shift register.

2) LE should be set to “L” when the data is transferred into the shift register.

Parameter Min. Typ. Max. Unit Parameter Min. Typ. Max. Unit

t1 20 – – ns t5 100 – – ns

t2 20 – – ns t6 20 – – ns

t3 30 – – ns t7 100 – – ns

t4 30 – – ns

Power-ON Timing

(1) PS = H (power-saving mode) at Power-ON(2) Input serial data 1µs later after power supply remains stable (VCC > 2.2V).(3) Release power-saving mode (PS: H Æ L) 100ns later after setting serial data.

ONOFF

VCC

ClockDataLE

PS

(1) (2) (3)

tV ≥ 1 µS

tPS ≥ 100 nS

MB15U36


Phase Detector Output Waveform

Notes: 1) Phase error detection range: –2π to +2π2) Pulses on Do signal during locked state are output to prevent dead zone.

tWU

frRF1-PLL, RF2-PLL

fpRF1-PLL, RF2-PLL

tWL

LD

(FC bit = “H”)

DoRF1-PLL, RF2-PLL Z

L

(FC bit = “L”)

Z

H

DoRF1-PLL, RF2-PLL



Application Example

VCO LPF

TCXO

3V

1000 pF

OUTPUT

1000 pF

From Controller

OSCIN Xfin1

9 8 7 6 5 4 3 2

12 13 14 15 16 17 18 19


3V1000 pF

VCO LPF

OUTPUT


MB15U36

1

20

10

11

Vcc1LD/fOUT

Clock Vcc2

1000 pF

3V

3V

Lock Detect

.1 µF .1 µF

.1 µF.1 µF

1000 pF

Notes: 1) Package Type: 20-pin SSOP2) Clock, Data, LE: Insert a pull-down or pull-up resistor as needed to prevent oscillation when the terminals are left open.

MB15U36


Application Example: Fastlock Mode

LPF

TCXO

3V

1000 pF

OUTPUT

1000 pF

From Controller

OSCIN Xfin1

9 8 7 6 5 4 3 2

12 13 14 15 16 17 18 19


3V1000 pF

VCO LPF

OUTPUT


MB15U36

1

20

10

11

Vcc1LD/fOUT

Clock Vcc2

1000 pF

3V

3V

.1 µF .1 µF

.1 µF.1 µF

1000 pF

VCO

Notes: 1) Package Type: 20-pin SSOP

2) Clock, Data, LE: Insert a pull-down or pull-up resistor as needed to prevent oscillation when the terminals are left open

3) The Fastlock mode is controlled by the LDS/FDS bits and the CMCRF1 bit. When the CMCRF1 bit is set to “H” (the RF1 charge pump current is increased4x normal mode), the LD/fout pin (open drain output) is “L”, enabling the parallel resistor in the loop filter. This effectively increases the LPF bandwidth,allowing the loop to lock faster. After the loop has locked onto a new frequency, the CMCRF1 bit is set to “L”, forcing the LD/fout output pin into a highimpedance state and returning the LPF bandwidth back to its original value.



Usage PrecautionsTo protect against damage by electrostatic discharge, note the following handling precautions:

• Store and transport devices in conductive containers.• Use properly grounded workstations, tools, and equipment.• Turn off power before inserting or removing this device into or from a socket.• Protect leads with conductive sheet when transporting a board mounted device.

Ordering Information

Part Number Package

MB15U36PFV 20-pin, Plastic SSOP (FPT-20P-M03)

MB15U36


Package Dimensions

0.50±0.20(.020±.008)

0.10±0.10(.004±.004)(STAND OFF)

0 10°

Details of "A" part

5.85(.230)REF

6.50±0.10(.256±.004)*

0.65±0.12

5.40(.213)4.40±0.10 6.40±0.20NOM(.252±.008)(.173±.004)

*

(.0256±.0047) .006 -.001+.002

-0.02+0.05

0.15

.009 -.002+.004

-0.05+0.10

0.22

.049 -.004+.008

-0.10+0.20

1.25

0.10(.004)

"A"

INDEX

(Mounting height)

D im ensions in m m (inches)

* T hese dim ensions do not inc lude res in protrus ion(FPT-20P-M03)20-pin, Plastic SSOP

FUJITSU MICROELECTRONICS, INC.Corporate Headquarters3545 North First Street, San Jose, California 95134-1804Tel: (800) 866-8608 Fax: (408) 922-9179E-mail: [email protected] Web Site: http://www.fujitsumicro.com

1999 Fujitsu Microelectronics, Inc. All rights reserved.

All company and product names are trademarks or registeredtrademarks of their respective owners.

With respect to any information contained in this document,Fujitsu makes no warranties, express, implied or otherwise,including but not limited to warranty of merchantability or offitness for a particular purpose, or warranty that suchinformation shall be free from errors or that such errors shallbe corrected, or warranty that such information shall be freefrom infringement or patents, patent applications, copyrights,semiconductor chip protection rights, trade secrets and otherproprietary or legal rights of a third party. In no event willFujitsu be responsible for any incidental or consequentialdamages arising out of use of this information.

The information in this document does not convey any licenseunder the copyrights, patent rights, or trademarks claimed andowned by Fujitsu Limited, its subsidiaries, or FujitsuMicroelectronics, Inc.

Fujitsu Microelectronics, Inc. reserves the right to changeproducts or specifications without notice.

No part of this publication may be copied or reproduced inany form, or by any means, or transferred to any third partywithout prior written consent of Fujitsu Microelectronics, Inc.

Printed in U.S.A.

TC-DS-20806-5/99

dual pll frequency synthesizer with on-chip · pdf filedual pll frequency synthesizer with...

Documents