verilog tutorial - ucsbstrukov/ece154afall2016/labs/verilog6.pdf · verilog tutorial adapted from...
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Verilog Tutorial
Adapted from Krste Asanovic
Verilog Fundamentals
• History
• Data types
• Structural Verilog
• Functional Verilog
Originally designers used manual translation + bread boards for verification
Hardware design languages enabled logic level simulation and verification
Once design were written in HDLs tools could be used for automatic translation
Primary Verilog data type is a bit-vector where bits can take on one of four values
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The Verilog keyword wire is used to denote a standard hardware net
Verilog includes ways to specify bit literals in various bases
Verilog Basics
• Data types
• Structural Verilog
• Functional Verilog
A Verilog module includes a module name and a port list
A Verilog module includes a module name and a port list
A module can instantiate other modules creating a module hierarchy
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A module can instantiate other modules creating a module hierarchy
A module can instantiate other modules creating a module hierarchy
Verilog supports connecting ports by position and by name
Let’s review how to turn our schematic diagram into structural Verilog
Let’s review how to turn our schematic diagram into structural Verilog
Verilog Fundamentals
• Data types
• Structural Verilog
• Functional Verilog
– Gate level
– Register transfer level
– High-level behavioral
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Functional Verilog can roughly be divided into three abstraction levels
Gate-level Verilog uses structural Verilogto connect primitive gates
Continuous assignments statementsassign one net to another or to a literal
Using continuous assignments to implement an RTL four input mutliplexer
Verilog RTL includes many operators in addition to basic boolean logic
Verilog RTL operators
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Always blocks have parallel inter-block and sequential intra-block sematics
Always blocks have parallel inter-block and sequential intra-block sematics
Always blocks have parallel inter-block and sequential intra-block sematics
Always blocks have parallel inter-block and sequential intra-block sematics
Always blocks have parallel inter-block and sequential intra-block sematics
Continuous and procedural assignment statements are very different
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Always blocks can contain more advanced control constructs
What happens if the case statement is not complete?
What happens if the case statement is not complete?
So is this how we make latches and flip-flops?
To understand why we need to know more about Verilog execution semantics
To understand why we need to know more about Verilog execution semantics
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To understand why we need to know more about Verilog execution semantics
To understand why we need to know more about Verilog execution sematics
To understand why we need to know more about Verilog execution sematics
To understand why we need to know more about Verilog execution semantics
To understand why we need to know more about Verilog execution semantics
To understand why we need to know more about Verilog execution sematics
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To understand why we need to know more about Verilog execution sematics
We didn’t model what we expected due to Verilog execution semantics
Non-blocking procedural assignments add an extra event queue
Non-blocking procedural assignments add an extra event queue
The order of non-blocking assignments does not matter
Common patterns for latch and flip-flop inference
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Writing Good Synthesizable VerilogBehavioral Verilog is used to model the
abstract function of a hardware
Verilog can be used to model the high-level behavior of a hardware block
Delay statements should only be used in test harnesses
System tasks are used for test harnesses and simulation management
Which abstraction is the right one?
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Examples Mux4: Gate-level structural Verilog
Mux4: Using continuous assignments Mux4: Behavioral style
Mux4: Using always blockMux4: Always block permit more
advanced sequential idioms
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Parametrized mux4 Flip-flops
Flip-flops with reset Register
Register in terms of Flip-flops Static Elaboration: Generate
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A simple state machine for valid/ready signals
Implementing the control logic finite state machine in Verilog
Implementing the control signal outputs for the finite state machine
Implementing the state transitions for the finite state machine
Take away points