verilog tutorial-3e using 13.4
DESCRIPTION
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1
Toma Sacco
Tutorial
Example: Single Digit BCD adder
1. From Xilinx ISE Design Tools, start Project Navigator
2. From File select New Project3. In the dialog window enter the project name and brose to the folder where you want your work to be stored. Make sure none of the folders in the path has a space in their names.
4. press Next
5. Press next after selecting the device and the simulator
6. Press Finish
7. From project select New Source8. On the dialog window select Verilog Module and enter file name and press next
9. on the dialog window enter the ports specifying their size and type and press next
10. check the information and press finish
11. Complete and save the module code. Then click synthesize. Correct any syntax errors you might have.
12. click view Technology Schematic
click OK
If you click on the diagram you will see the details of the implementation.
13. from project select New Source14. on the dialog window select Verilog Test Fixture and enter the file name
15. click next
16. click next
17. click finish
18. Modify and save the code. Then click Behavioral Check Syntax.
19. If you have no errors; click on Simulate Behavioral Verilog Model
You could set the simulation time in the box. Click restart-simulation and then click run for the specified time.To change the format of the numbers displayed on the waveform, right click on the signal and from Radix select the desired format.
Repeat 9 to 22 for the Binary to LCD interface subsystem.
Copy the LCD interface Verilog description from the provided text file ( LCDI_5BC.txt
) and paste it in the LCD module.
Repeat 9 to 22 for the system.
Click Next
Click Next
Click Finish
To add internal signals to simulation, right click on the device system and select expand. Then you could drag any signal to simulation area.
20. from project select New Source21. on the dialog window select Implementation constraints file and enter the file name
Click next
Click finish
22. Select the file system and then from User Constraints click on I/O Pin Planning (PlanAhead)-Post-Synthesis.
Click No
23. Assign the pins and save the file. To assign the pin for a given signal; select the signal in the I/O ports window then you could assign the pin and its attributes.
Another way to enter the pins is using the editor
Here is the text file generate by this step:
24. Click Implement Design25. Click Generate Programming file
26. Connect the power and USB cable to the FPGA board27. Double click Configure Target Device.
Click OK
28. From file select new project
Click Yes
Click OK
Click Yes
29. select your bit file and click Open
Click No
30. click Bypass
31. Click Bypass
Click OK32. Right click the device you want to program and select Program
33. Click OK
34. Test your system by entering different numbers:
EY
LCDI
X
40
datain
C9
clk
L17
L18
M18
control[0]
control[1]
control[2]
EX
Y
4
EX
Load
4
cout
EY
sum
4
Single Digit BCD Adder
Load
data
4
Select Simulation
R15
R16
P17
M15
dataout[0]
dataout[1]
dataout[2]
dataout[3]
data
I/O Ports pins and properties