Digital Circuit Design and Language

Verilog Tutorial(Basic)

Chang, Ik JoonKyunghee University

Design FlowDesign Specification

Behavioral Description

RTL Description (HDL)

Functional Verificationand Testing

Logic Synthesis

Gate-Level Netlist

Physical Layout

Layout Verification

Logical Verificationand Testing

Floor Planning Automatic Place & Route

Implementation

Why Hardware Description Language (HDL)?

+ Abstraction• Separation between logical design and physical

implementation• Easy to migrate technology

+ Advantage in Verification + Similar to computer programming

• Easy for debugging• Good for maintenance

Applicable to Analog and Full Custom Digital?

Abstraction Levels in Verilog Behavioral or Algorithmic Level Most upper level Similar to C language

Dataflow Level Showing the data flow between registers

Gate Level Describing Gate-to-Gate connection

Switch Level

RTL Level Design = Behavioral + Dataflow

Language Concept

User Identifiers

Comments

Logic Value Set in VerilogValue 설명

0 Logically ‘0’ (Connected to GND)

1 Logically ‘1’ (Connected to VDD)

x Unknown (i.e. Confliction between ‘0’ and ‘1’)

z High impendence

Verilog uses only 4 logic values

Number Expression in Verilog

Number Expression in Verilog (Cont.)

Structural Data Type: Net Hardware wires driven by logic

When unconnected, the net is equal to ‘z’ High impedance

Various types of nets Refer to the following slide

Type Meaningwire Only connection tri wire with high impedance

wor Many wires are connected to single net. The function of this wire is ‘OR’

trior wor + high impedance

wand Many wires are connected to single net. The function of this wire is ‘AND’

triand wand + high impedancetrireg Net with capacitor(registering value + high impedance)

supply1 Strongly connected to VDDsupply0 Strongly connected to GND

tri1 Connected to VDD, but having high impedancetri0 Connected to GND, but having high impedance

Structural Data Type: Net (Cont.)

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Structural Data Type: Net (Cont..)

Structural Data Type: Register Variables storing values Does not represent real hardware register / flip-flop

(no clock), but can be implemented as them Only one data type : reg

Retaining its value until assigning a new value

Structural Data Type : Vectors Represent Buses

Left: MSB, Right: LSB busA → Little Endian, busB → Big Endian Slice Management

Vector Assignment (By Position)

Behavioral Data Type: Integer, Real and Time

+ Register Data Type+ Declaration

• Integer m; // m is not initialized. Negative value can be assigned (unlike reg).

• real r; // r is initialized as ‘0’.• time my_time; //special data type for measuring simulation time• r = 2.9; m = r; // m is rounded to 3

+ Use of the time data type• my_time = $time; // getting current simulation time

+ Simulation time ≠ Real Time

Behavioral Data Type: Array and Memory

+ Declaration• Integer counter[1:5]; //5 integers• reg var[31:0]; // 32 1-bit registers • reg [7:0] mem[0:1023]; // 1024 8-bit registers, called as Memory• integer matrix [0:3] [0:4]; // multi-dimensional array• counter = 0 legal or illegal?

+ What is different from Vector?

+ Memory = Array of Vector reg

Behavioral Data Type: String+ Implemented with reg

+ Escaped char:

OperatorOperator Type Operator Meaning Example

Arithmetic Operator

+ add assign ADD=A + B- subtract assign SUB=A - B* multiply assign MUL=A * B/ divide assign DIV=A / B

% modulo assign REM=A % B

EqualOperator

== equal return value = 0, 1, x=== equal including x/z return value = 0, 1!= not equal return value = 0, 1, x

!== Not equal including x/z return value = 0, 1

< Less than return value = 0, 1, x<= Less than or equal return value = 0, 1, x> Great than return value = 0, 1, x

>= Greater than or equal return value = 0, 1, x

Operator (Cont.)Operator Type Operator Meaning Example

Logical Operator&& Logical AND if (A && B) …

|| Logical OR if (A || B)…! Logical NOT if (!A)…

Bitwise Operator

~ Bitwise NOT ~(1011) = (0100)& Bitwise AND (1011) & (0011)=(0011)| Bitwise OR (1011) | (0011)=(1011)^ Bitwise XOR (1011) ^ (0011)=(1000)

^~, ~^ Bitwise XNOR (1011) ~^ (0011)=(0111)

Reduction Operator

& Reduction AND &(0101) = “0”

| Reduction OR |(0101) = “1”

~& Reduction NAND ~&(0101) = “1”

~| Reduction NOR ~|(0101) = “0”

^ Reduction XOR ^(0101) = “0”

~^, ^~ Reduction XNOR ~^(0101) =“1”

Operator (Cont..)Operator Type Operator Meaning Example

Shift Operator>> Right Shift 0101_1001=1011_0011>>1

<< Left Shift 0110_0110=1011_0011<<1

Others

{ } concatenation {0011,{{01},{10}}=0011_0110

{{ }} replication A=1’b1; Y={4{A}} = 4’b1111

? : Conditional Y=(A==B) ? A:B (A==B, Y=A else Y=B)

Operator Precedence