verilog entry and simulation tutorial

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Verilog Entry and Simulation Tutorial

Table Of Contents Verilog Entry and Simulation Tutorial .............................................................................................. 1

Introduction .................................................................................................................................. 1 Design Entry................................................................................................................................. 1 Simulation .................................................................................................................................. 26 Simulation with Testbench......................................................................................................... 30

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Introduction

The purpose of this tutorial is to familiarize users with the design cycle based on the Verilog language. Though some of the files are initially created using State Machine and Block Diagram Editors, the generated code describing design functionality is pure Verilog. By accomplishing the following tutorial, you will create a frequency meter comprised of the following models:

binary counter the control state machine control.asf the hexadecimal to LED digital display decoder binary to BCD code converter the measuring unit built upon the above mentioned components

Design Entry

1. After starting the Active-HDL environment you will see the Getting Started window that either lets you create a new workspace or create an existing one. Since you will create a new project, check the Create new workspace option and accept it by clicking the OK button. The New Workspace wizard will be invoked. The wizard has only one step. In this step you need to provide the name and location of new workspace.

Make sure that the Add New Design to Workspace option is selected and click the OK button. After the new workspace is created, the New Design Wizard will be invoked. 2. In the first window of the New Design Wizard, you need to define how you would like to create the design resources. Check the Create an empty design option and click the Next button. 3. In the next window, you specify additional information on configuration of the Block Diagram and set Verilog as the default HDL language. Additionally, you can choose the programmable device family and the synthesis and implementation tools that can be used to implement the current project (if the Flow Manager is enabled). Click the Next button.

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4. This will open the New Design Wizard window for creating the new design source files. Next, type the name of the design and set its location. In the Type the design name field, type the name tutorial_Verilog and leave the default location of the design folder suggested by Active-HDL. Along with the design, the working library will be created. This library will contain all models compiled during the design creation.

After filling in the fields, advance to the next window by clicking Next. 5. In the last window of the New Design Wizard press the Finish button to accomplish the design creation stage. 6. As you can see in the Design Browser window, a new empty design has been created along with a working library named after the design: tutorial_Verilog.

10-bit Counter 7. Now we are ready to create project resources. Double-click the Add New File icon located in the Design Browser window. In the Add New File window switch to the Wizards tab and click on the Verilog Source Code Wizard icon. Next, click the OK button. 8. The Wizard is invoked to guide you through the creation process. Make sure that the Add the generated file to the design box is checked.

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Verilog Entry Tutorial

In the New Source File Wizard window you have to define the new created file name and optionally a module name.

Type cnt_10b in the first field and click the Next button. 9. The counter has the following ports:

CLK bit input ENABLE bit input RESET bit input FULL bit output COUNT 10-bit output

To add a new port to a unit, click the New button and type its name in the Name filed selecting the direction in the Port direction box. For the multi-bit ports such as COUNT , specify the range by clicking the index arrows in the Array Indexes field as shown in the figure. IMPORTANT ! Make Sure that all port names are entered with capital letters.

For multi-bit outputs such as the COUNT port, you also need to specify its range by clicking the Array Indexes arrows as shown in the figure. Set the COUNT port range to 9:0. To finish the declaration part, click the Finish button. 10. After clicking the Finish button, the automatically generated resource file is opened in the HDL Editor window.

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As you can see in the figure above, the skeleton Verilog file contains port declarations and empty architecture requiring your modification. Insert the cursor below the // -- Enter your statements here -- // line as shown in the figure and type the following declarations:

reg [9:0] COUNT_I; reg FULL_I;

11. The counter code is incomplete without the behavior description. To complete it, insert the following code below previously inserted declarations:

always @ (posedge CLK or posedge RESET) begin if (RESET) // asynchronous reset begin COUNT_I = 10'b0000000000; FULL_I = 1'b0; end else // active clock edge begin

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if (ENABLE) begin if (COUNT_I == 10'b1111111111) FULL_I = 1'b1; else COUNT_I = COUNT_I + 1; end end end assign COUNT = COUNT_I; assign FULL = FULL_I;

The below HDL Editor window displays the full counter contents.

12. Such modified code is complete and ready for compilation. To compile the file, right-click its name in the Design Browser window and choose the Compile option from the pop-up menu.

The compilation process log displayed in the Console window is shown below.

13. A successful compilation is checked by the green check mark next to the file name and reported in the Console window. There is also a sign next to the compiled file, allowing branch

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expanding of the entity-architecture pair. The Design Browser contents are shown in the following figure.

Notice how the compiled module has been automatically attached to a working library.

Hexadecimal to LCD converter 14. To create the decoder, you need to create a new source file. To add a new file to the design, double-click the Add New File option in the Design Browser window. This will open the Add New File window that lets you choose the creation method. Switch to the Wizards tab and select the Verilog Source Code Wizard by clicking the OK button. 15. The Wizard is invoked to guide you through the creation process. Make sure that the Add the generated file to the design box is checked. Advance to the next window clicking the Next button. 16. Here, you need to specify the name of the file and optionally the name of the module. Type the hex2led name in the first field as shown in the figure.

Click the Next button to go further. 17. In this step you will declare the module ports. After clicking the New button, type the port name in the Name field and specify its direction in the Port direction box. Enter the following ports using the above method:

HEX in, 4-bit [3:0], LED out,7-bit [6:0]

To set the ports ranges use the Array Indexes arrows according to the above mentioned values.

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Upon entering the above listed ports, finish the port declaration part by clicking the Finish button. 18. The results are shown in the Design Browser window. There is a new hex2led.v file.

19. The newly created file is automatically opened in the HDL Editor window.

Type the below assignment describing the decoder behavior below the // -- Enter your statements here -- // line:

assign LED =(HEX == 4'b0001) ? 7'b1001111 : // 1 (HEX == 4'b0010) ? 7'b0010010 : // 2 (HEX == 4'b0011) ? 7'b0000110 : // 3 (HEX == 4'b0100) ? 7'b1001100 : // 4 (HEX == 4'b0101) ? 7'b0100100 : // 5 (HEX == 4'b0110) ? 7'b0100000 : // 6

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(HEX == 4'b0111) ? 7'b0001111 : // 7 (HEX == 4'b1000) ? 7'b0000000 : // 8 (HEX == 4'b1001) ? 7'b0000100 : // 9 7'b0000001; // 0

20. Such a modified file needs to be compiled. You can compile files by clicking the Compile

toolbar button or using the pop-up menu Compile command in the Design Browser. This will compile the file opened in the HDL Editor window.

The results are displayed in the Design Browser window.

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Binary to BCD Converter 21. Now, you will create a binary to BCD code converter. Double-click the Add New File branch in the Design Browser. Select the Empty Files tab and choose the Verilog Source Code wizard. In the Name field, type bin2bcd.

22. Accepting the described actions with the OK button adds a new bin2bcd file to the design and opens it automatically in the HDL Editor.

23. To enter the converter description use the Language Assistant window by clicking the button located in the main Active-HDL toolbar. Navigate to the Tutorial branch and locate the bin2bcd model. Right click its name and choose the Use option from the pop-up menu.

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24. This inserts the converter code to the bin2bcd.v file. At this point you may save the file by using the Ctrl+S keyboard shortcut or the File | Save menu option. An example of the converter code is shown in the figure.

25. Compile the file using the Compile button located in the main toolbar. The results are visible in the Design Browser window where a new bin2bcd branch is attached to the bin2bcd.v file.

Top-Level Diagram 26. Using the 10-bit counter and the binary to BCD code converter description you can now create a top-level file binding these components. Double-click the Add New File option in the Design Browser window and switch to the Wizards tab in the Add New File window. Choose the Block Diagram Wizard and select the OK button. 27. The New Source File Wizard window is invoked. Make sure that the Add the generated file to the design box is checked. Click the Next button to advance to the next window. 28. The schematic you create can be converted into three different file formats: EDIF, VHDL and Verilog. In your case, select Verilog and click the Next button. 29. You need to enter the name of the file and the optional module name. Type the freq_m in the first field as seen in the figure and hit the Next button.

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30. At this point you need to specify the module ports. After clicking the New button, type the port name in the Name field and specify its direction in the Port direction box. For the multi-bit outputs such as: LED_A, LED_B, LED_C and LED_D specify their range by clicking the index arrows in the Array Indexes field as shown in the figure. Enter the following ports using the described method above: Inputs:

F_INPUT single bit PATTERN single bit RESET single bit START single bit F_CONV single bit

Outputs: FULL - single bit LED_D - 7-bit vector- [6:0] LED_C - 7-bit vector- [6:0] LED_B - 7-bit vector- [6:0] LED_A - 7-bit vector- [6:0]

Finish the step by clicking the Finish button. 31. The Design Browser window displays a new freq_m.bde file.

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The Block Diagram Editor window is automatically open with the port terminals specified by the wizards.

Control module 32. The Block Diagram Editor contains the terminals of the diagram created with the wizard help. The Block Diagram Editor lets you create an empty symbol and place it on a diagram to enable later source specification using Verilog or State Diagram file. This methodology is called top-down designing and you will utilize this technique to build the controlling automata.

To draw an empty symbol on a diagram use the Fub button located in the main Block Diagram Editor toolbar. Anchor the top-left corner clicking once with the left mouse button and while holding it down drag the mouse pointer creating a rectangle, releasing the mouse button at the end. An example of a drawn fub is presented in the following figure.

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Switch to the Select mode, right-click the fub and choose the Properties option from the pop-up menu. In the Fub Properties window, change fub name into control and accept changes with OK button.

33. Notice that the drawn symbol contains no pins. In the next few steps you will build the sources for the symbol placed on the schematic. Right-click the fub and choose the Push option from the pop-up menu.

34. As a result the Create New Implementation window appears. Choose the State Diagram icon and then click the OK button.

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35. This will attach a newly created control.asf file to the current design. In the first step, create the state diagram ports. To place the terminals in the diagram click the

Input Port button located in the main toolbar. Using this button each time, place three input terminals in the upper declarative part of the state diagram as shown in the figure.

36. Similarly to input ports, define the output terminals. To do this, use the Output Port

button and place three output ports.

37. Change the Port1 terminal name to CLK by double-clicking its label. Save the settings using the Ctrl + S keyboard shortcut.

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38. Similarly, change the names of other input ports to CLK, START, RESET and output ports to GATE, END_MEASURE, ENABLE, respectively. The results are presented in the following figure.

The CLK input terminal serves as a clocking signal. To change the port mode to clock, right-click its name and choose the Properties option from the pop-up menu.

39. In the Port Properties window, check the Clock box and accept changes with the OK button.

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As a result, the CLK signal symbol contains a small waveform. 40. The complete automata will be comprised of three states. To place a new state on the

diagram, use the State button. Place five states on the diagram, each time clicking the State button.

41. At this point, change the names of the created states. Double-click the S1 label and change its name to IDLE as shown in the figure.

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In the same way, modify the name of the remaining states: OPEN_GATE, CLOSE_GATE, CONVERT, END_CYCLE, respectively.

42. To draw the transitions between states, use the Transition button. To draw a transition, click within one state and drag the line dropping the transition within another state. Draw the transitions as shown in the figure. Note: To draw a transition from a state to itself, click the state once and then move slightly within the state and click once again. This will create a smooth loop transition.

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43. Now define the conditions of the states transitions. To place the conditions on the diagram,

click the Condition button. Now click the transition for which the condition needs to be set. Type the condition in the box that appears on the transition. A transition condition set between the IDLE and START states is shown in the figure.

44. The next step in drawing the state diagram is to set the output values in each state. This is

achieved with the State Action button located in the toolbar. Click it once and drag the line with a small circle at the end of the line, dropping the small circle over the selected state. Now type the assignments in the active box using the Verilog syntax. An exemplary assignment is shown below.

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45. Using the method described above, specify all output value assignments as shown in the following figure.

46. The drawn diagram requires a reset signal. This is accomplished with the Reset button located in the toolbar. Click this button and place the reset symbol next to the IDLE state. Now connect it with the state using the Transition function.

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47. This finishes the drawing stage. The last thing to do is to set the reset condition. Click the empty area in the diagram and choose the Properties... option from the pop-up menu.

48. In the Machine Properties window, switch to the Reset tab and change the signal type from Synchronous to Asynchronous in the Type field.

Accept the change with the OK button. Save such created diagrams using the Ctrl + S keyboard

shortcut. Moreover, you may compile prepared diagrams by using the Compile button located in the main toolbar. 49. Switch to the Block Diagram Editor window by clicking the freq_m.bde tab in the lower part of the Active-HDL environment. Since the symbol contains no ports, you will need to compare it with

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its contents to apply latest changes. Right-click the symbol and choose Compare Symbol with Contents from the pop-up menu.

50. Close the opened Compare Interfaces window with the OK button.

51. The symbol is automatically updated and terminals are created according to the state machine ports declared for the automata.

52. The connections between the symbols placed on the diagram are done with a wire. After

selecting the Wire button, draw the lines between the terminals and the symbols as shown in the figure. To create a wire connection, anchor the wire by clicking the symbol pin and drag it

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towards the target pin of the remaining symbol. Complete the connection by clicking the desired destination pin once. Following this method, create the rest of the connections according to the figure. Save diagrams by using the Ctrl + S keyboard shortcut.

53. Place the counter and converter symbols, created at the beginning of this tutorial, onto the

schematic. By clicking the Symbol Toolbox toolbar button, open the following window. Notice the presence of the design symbols compiled into working library.

54. To place the symbol on the schematic, drag it from the Symbol Toolbox window dropping over the selected area. In this way place the cnt_10b symbol next to the controlling automata as shown in the figure.

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55. Similarly, put the bin2bcd symbol to the right of the counter. Next, arrange four hex2led symbol to the right of the bin2bcd converter. The results should be as follows:

56. To draw a bus, use the Bus button located in the main toolbar. By clicking the button, the cursor will change its shape to . Similarly to drawing the wire, create the following connections between the BCD converter and four LED display converters. Then, connect the LED converters with output terminals:

57. Using the Bus button draw the connection between the COUNT counter output and BIN(9:0) input.

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58. Now, clicking the Wire button, draw the following wire connections as shown in the figure: Connect the ENABLE output of the control machine with the ENABLE input of the

bin2bcd converter. Connect the GATE output of the control machine with the ENABLE input of the cnt_10b

counter. Connect the END_MEASURE output of the control machine with the RESET inputs of the

cnt_10b counter and bin2bcd converter. The FULL counter output should be connected with the FULL output terminal located in

the far right side of the schematic.

59. Now, connect the input terminals using the Wire button. Create the following connections:

F_INPUT input terminal with the CLK input of the cnt_10b counter PATTERN input terminal with the CLK input of the Control automata RESET input terminal with the RESET input of the Control automata START input terminal with the START input of the Control automata F_CONV input terminal with the CLK input of the bin2bcd converter.

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60. The completed schematic should resemble the one presented in the figure below.

61. A complete schematic can now be compiled with the Compile button located in the main toolbar. The results are immediately updated in the Design Browser window. Notice that Active-HDL automatically converted the schematic into a corresponding Verilog description and compiled modules have been placed in the working library.

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Simulation

Compiled and saved schematic can now be prepared for functional simulation in the Standard Waveform Editor.

Setting Top-Level 1. The next most important thing is to specify the design module for the functional simulation. This module is called in the Active-HDL Top-Level. To set the architecture as Top-Level, click the sign next to the freq_m.v file in the Design Browser window to expand the contents. Select the freq_m branch and right-click it to call the pop-up menu. Choose the Set as Top-Level option and notice how the branch is displayed in bold.

Initializing the Simulation 2. In this step, you will initialize the simulation by choosing the Initialize Simulation from the Simulation menu. The simulation initialization is indicated by an automatic change in the Design Browser where the Structure tab is brought to front.

3. To open the Standard Waveform Editor, click the New Waveform button located in the main Active-HDL toolbar. At the same time select the freq_m branch in the upper part of the Design Browser window to display the signals visible for the selected unit in the lower part of the window.

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Select the following signals by holding down the Ctrl key and clicking their names with the mouse pointer (Also, you can select the first signal by holding down the Shift key. Click the last one to select the entire set):

FULL, F_CONV, F_INPUT, LED_A, LED_B, LED_C, LED_D, PATTERN, RESET, START.

Drag the selected signals to the Waveform Editor window by dropping them over the empty area in the left part of the window.

Applying stimulators 4. In this step, you will force the signals with test vectors. Select the RESET signal and by right-clicking it, choose the Stimulators... option from the pop-up menu. This will open the Stimulators window where you can apply predefined test vectors to signals.

5. In the Stimulators window, select the stimulator type for the signal by choosing an appropriate one from the Type: list. For the RESET signal, choose the Formula stimulator type. In the Enter Formula field type the following instruction: 1 0 ns, 0 200 ns. This means that the RESET signal will be forced with logic 1 and after 200 ns with logic 0.

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Accept the formula settings by clicking the Apply button. 6. To set the test vectors for the remaining signals, it does not require closing the Stimulators window. Move the window aside to see the signals in the Waveform Editor window and click the START signal name. Notice how the name is automatically added to the Signals list in the Stimulators window. Choose the Value formula type and select 1 from the drop-down list in the Force value field.

Accept it with the Apply button. 7. The F_CONV signal utilizes the Clock stimulator type. Change the default settings from 100 ns to 1000 ns. To do this, click the editing field with the 100 ns value displayed and type the new 1000 ns value as shown in the figure. Accept the settings by clicking the Apply button.

8. The PATTERN signal uses the Clock stimulator as well. This time, change its duty cycle to 10000ns. Accept the changes clicking the Apply button.

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9. The last signal to set is the F_INPUT. Similar to the previous two signals, choose the Clock stimulator type. Make sure that the duty cycle is set to 100 ns and accept the settings with the Apply button. Close the window by selecting the Close button.

Running Simulation 10. Now, change the simulation duration time to 50 us in the Run For field

located next to the Run For button.

Clicking the Run For button starts and runs the simulation for the specified time. The results are displayed in the Standard Waveform Editor window as shown in the figure.

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11. You can save the simulation results as waveforms in a native .awf file. Save the simulation

run clicking the Save button located in the main toolbar or choosing the Save option from the File menu.

Type the vectors name in the File name field and push the Save button.

Simulation with Testbench

1. The simulation results saved in the vectors.awf file will serve as test vectors for the testbench automatically created by the wizard. Expand the freq_m.v branch to display the freq_m module and select it. Next, right-click it to display the pop-up menu and choose the Generate Testbench option to start the Testbench wizard.

2. As a result, the Testbench wizard window appears. Make sure that the freq_m module is displayed in the Module drop-down list. Click Next to go to the next window.

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3. In the next window, check the Test vectors from file check box and click the Browse button.

4. In the Files of type: field change the format to waveform files (*.awf) and select the exported vectors.awf file. After selecting the file, click the Open button.

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5. Active-HDL will automatically search the file for signals and adds them to the Signal found in file: window. Notice that these signals match the tested model signals. Otherwise an error message is displayed.

Click the Next button. 6. The next wizard window displays the module name for the generated testbench files as well as the folder name containing these files.

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Accept the default settings and advance to the next window by clicking the Next button. 7. Finish the testbench generation process by clicking the Finish button. 8. As you may notice, the Design Browser window displays a new Testbench folder with two files:

freq_m_TB.v the testbench file freq_m_TB_runtest.do macro command file for automatic testbench execution

9. Select the freq_m_TB_runtest.do file and by right-clicking it, choose the Execute option to start the automatic compilation and simulation.

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10. During the simulation, a new Waveform Editor window is opened where the signals are automatically attached and the results are updated accordingly.

Debugging Active-HDL offers several useful tools designed for efficient line-by-line code debugging and simulation results tracing.

Verilog Code Debugging 1. Before starting the debugging session you need to restart the simulation by using the Restart Simulation option from the Simulation menu. Active-HDL offers step-by-step code debugging of Verilog source code with signal and code breakpoints enabled. You can advance the simulation until a breakpoint is encountered by using

the Trace buttons located in the main toolbar. In this tutorial, you will set a breakpoint inside the description of a cnt_10b.v counter. Go to the cnt_10b.v file by double-clicking the file name in the Design Browser window. If the file is already opened, you can click the corresponding tab in the HDL Editor. In the counter description, find the following line responsible for enabling the counter:

if (ENABLE) Place the insertion point there by clicking the mouse cursor. Right-click this line and choose the Toggle Breakpoint option from the pop-up menu.

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2. After setting the breakpoint in the selected line a mark is placed on the left side. You can toggle any breakpoint using the F9 keyboard key or by choosing the Disable Breakpoint option from the pop-up menu. The HDL Editor with a breakpoint set is shown below.

3. To observe the values of selected signals, use the Watch window. To open the Watch window

click the View Watch Window button located in the main toolbar. Clicking this button opens an empty Watch window as shown in the figure.

4. In the next step you will add the COUNT_I signal of the cnt_10b.v file counters. To do this, expand the freq_m_tb branch in the Structure tab of the Design Browser as shown in the figure. Locate the cnt_10b branch and select it to display its signals in the lower part of the Design Browser window. Select the COUNT_I signal and drag it to the Watch window.

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5. The following figure represents the Watch window with the COUNT_I signal added. Notice that the initial signal value equals XXX.

6. To observe the status of executed processes, open the Processes window by choosing the Processes option from the View menu. The following window appears.

7. Start the simulation by clicking the Run For button. Since the breakpoint has been set in the counter's code, the simulation will stop upon reaching the selected line. The line with the breakpoint is highlighted in yellow.

To execute the code line-by-line, use the Trace into button located in the HDL Editor toolbar. Each click on the Trace button executes a single code line. You can use the F7 keyboard key to achieve the same result.

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8. Repetitive Run For button uses are reflected by value changes of the COUNT_I signals in the Watch window.

9. The Processes window reflects the changes in the behavior of the counter. The processes displayed must have the Ready status.

10. To trace the modules signal changes you can use the Design Browser window as well. Switch to the Structure tab and select the required design branch. For example to watch the hex2led display decoder signals expand the freq_m_tb tree and select the U7: hex2led branch. Observe the HEX and LED signal values in the lower part of Design Browser.

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11. Additionally, you can check the current value of the signal directly in the HDL Editor. After resting the cursor on any signal name appearing in the code, a tooltip window appears as shown in the figure. To check the COUNT_I signal value, rest the cursor over the COUNT_I signal name.

Tracing Signal Changes in Block Diagram Editor 1. Apart from many editing features, the Block Diagram Editor interactively displays the current values in the schematic. Before you take advantage of this convenient feature, you need to remove the breakpoint set in the counters code. To do so, go back to the cnt_10b.v file and locate the line with the breakpoint. This line as you may remember, is indicated with a mark. Place the cursor somewhere in the line and press the F9 keyboard key. This will remove the breakpoint from the line. 2. To observe signal changes in Block Diagram Editor, switch to the freq_m.bde file. You can achieve this by clicking the freq_m.bde file tab or by double-clicking the same file name in the Design Browser window. Moreover, restart the simulation by choosing the Restart Simulation option from the Simulation menu. The Block Diagram contents are shown in the figure.

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As you can see, all initial signal values equal X.

3. Press the Run For toolbar button and observe how the values of all symbols instances are interactively changed.

Exemplary contents of the Block Diagram Editor after repetitive Run For button uses are shown in the figure below.

As you can see, the values are updated immediately.

State Diagram Debugging Active-HDL offers interactive debugging animation of state diagrams in the State Diagram Editor. This is achieved by advancing the simulation until a state transition is encountered. 1. To trace the value changes in the subsequent states, switch to the previously described control.asf diagram. There are two ways to open the control.asf file. Either click the corresponding tab or double-click the file name in Design Browser. As usual, restart the simulation using the Restart Simulation command from the Simulation menu. Locate the control module in the Structure tab of the Design Browser window.

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2. If the Watch window is closed, open it by clicking the View Watch Window button located in the toolbar. You may also choose the Watch option from the View menu. Select and drag the following signals from Design Browser to the Watch window:

CurrState_Sreg0, GATE, END_MEASURE.

3. To initialize the simulation and reset the state diagram, click the Trace over Transition

button located in the State Diagram toolbar. This is indicated by a transition to the Idle state highlighted with a yellow background.

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4. Observe the simultaneous signal changes in the Watch window.

The subsequent Trace over Transition button pushes advance the simulation until the next transition between the state diagram states occurs. This is immediately reflected in the Watch window by a corresponding signal update. Thank You for using Active-HDL!

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Verilog Entry and Simulation Tutorial Introduction Design Entry Simulation Simulation with Testbench

verilog entry and simulation tutorial

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