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  • V-Series Transceiver PHY IP Core UserGuide

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    UG-010802017.07.06

    101 Innovation DriveSan Jose, CA 95134www.altera.com

    https://www.altera.com/servlets/subscriptions/alert?id=UG-01080mailto:[email protected]?subject=Feedback%20on%20V-Series%20Transceiver%20PHY%20IP%20Core%20User%20Guide%20(UG-01080%202017.07.06)&body=We%20appreciate%20your%20feedback.%20In%20your%20comments,%20also%20specify%20the%20page%20number%20or%20paragraph.%20Thank%20you.

  • Contents

    Introduction to the Protocol-Specific and Native Transceiver PHYs................ 1-1Protocol-Specific Transceiver PHYs..........................................................................................................1-1Native Transceiver PHYs ........................................................................................................................... 1-2Non-Protocol-Specific Transceiver PHYs.................................................................................................1-4Transceiver PHY Modules.......................................................................................................................... 1-4Transceiver Reconfiguration Controller................................................................................................... 1-5Resetting the Transceiver PHY...................................................................................................................1-5Running a Simulation Testbench............................................................................................................... 1-6Unsupported Features................................................................................................................................. 1-9

    Getting Started Overview....................................................................................2-1Installation and Licensing of IP Cores...................................................................................................... 2-1Design Flows.................................................................................................................................................2-2MegaWizard Plug-In Manager Flow......................................................................................................... 2-3

    Specifying Parameters..................................................................................................................... 2-3Simulate the IP Core........................................................................................................................ 2-4

    10GBASE-R PHY IP Core................................................................................... 3-110GBASE-R PHY Release Information.....................................................................................................3-610GBASE-R PHY Device Family Support................................................................................................3-610GBASE-R PHY Performance and Resource Utilization for Stratix IV Devices.............................. 3-710GBASE-R PHY Performance and Resource Utilization for Arria V GT Devices........................... 3-710GBASE-R PHY Performance and Resource Utilization for Arria V GZ and Stratix V Devices

    ...................................................................................................................................................................3-8Parameterizing the 10GBASE-R PHY.......................................................................................................3-8General Option Parameters........................................................................................................................ 3-9Analog Parameters for Stratix IV Devices.............................................................................................. 3-1210GBASE-R PHY Interfaces.....................................................................................................................3-1310GBASE-R PHY Data Interfaces........................................................................................................... 3-1410GBASE-R PHY Status, 1588, and PLL Reference Clock Interfaces.................................................3-17Optional Reset Control and Status Interface..........................................................................................3-1810GBASE-R PHY Clocks for Arria V GT Devices................................................................................ 3-1910GBASE-R PHY Clocks for Arria V GZ Devices................................................................................ 3-2010GBASE-R PHY Clocks for Stratix IV Devices................................................................................... 3-2110GBASE-R PHY Clocks for Stratix V Devices.....................................................................................3-2210GBASE-R PHY Register Interface and Register Descriptions......................................................... 3-2310GBASE-R PHY Dynamic Reconfiguration for Stratix IV Devices................................................. 3-2810GBASE-R PHY Dynamic Reconfiguration for Arria V and Stratix V Devices.............................3-281588 Delay Requirements......................................................................................................................... 3-2910GBASE-R PHY TimeQuest Timing Constraints...............................................................................3-2910GBASE-R PHY Simulation Files and Example Testbench............................................................... 3-31

    TOC-2 Introduction

    Altera Corporation

  • Backplane Ethernet 10GBASE-KR PHY IP Core............................................... 4-110GBASE-KR PHY Release Information..................................................................................................4-3Device Family Support................................................................................................................................ 4-310GBASE-KR PHY Performance and Resource Utilization.................................................................. 4-3Parameterizing the 10GBASE-KR PHY....................................................................................................4-4

    10GBASE-KR Link Training Parameters .....................................................................................4-510GBASE-KR Auto-Negotiation and Link Training Parameters.............................................. 4-610GBASE-R Parameters.................................................................................................................. 4-71GbE Parameters..............................................................................................................................4-8Speed Detection Parameters........................................................................................................... 4-9PHY Analog Parameters............................................................................................................... 4-10

    10GBASE-KR PHY IP Core Functional Description............................................................................4-1010GBASE-KR Dynamic Reconfiguration from 1G to 10GbE............................................................. 4-1410GBASE-KR PHY Arbitration Logic Requirements...........................................................................4-1610GBASE-KR PHY State Machine Logic Requirements...................................................................... 4-16Forward Error Correction (Clause 74)................................................................................................... 4-1610BASE-KR PHY Interfaces..................................................................................................................... 4-2010GBASE-KR PHY Clock and Reset Interfaces.....................................................................................4-21

    10GBASE-KR PHY Data Interfaces.............................................................................................4-2310GBASE-KR PHY Control and Status Interfaces.................................................................... 4-26Daisy-Chain Interface Signals...................................................................................................... 4-29Embedded Processor Interface Signals....................................................................................... 4-30Dynamic Reconfiguration Interface Signals...............................................................................4-31

    Register Interface Signals.......................................................................................................................... 4-3310GBASE-KR PHY Register Definitions................................................................................................ 4-34PMA Registers............................................................................................................................................ 4-53PCS Registers.............................................................................................................................................. 4-55Creating a 10GBASE-KR Design............................................................................................................. 4-58Editing a 10GBASE-KR MIF File ............................................................................................................4-59Design Example..........................................................................................................................................4-61SDC Timing Constraints...........................................................................................................................4-62Acronyms.........


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